1/* 2 * Copyright (c) 2019-2021, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19 20/* -------------------------------------------------- 21 * Errata Workaround for A78 Erratum 1688305. 22 * This applies to revision r0p0 and r1p0 of A78. 23 * Inputs: 24 * x0: variant[4:7] and revision[0:3] of current cpu. 25 * Shall clobber: x0-x17 26 * -------------------------------------------------- 27 */ 28func errata_a78_1688305_wa 29 /* Compare x0 against revision r1p0 */ 30 mov x17, x30 31 bl check_errata_1688305 32 cbz x0, 1f 33 mrs x1, CORTEX_A78_ACTLR2_EL1 34 orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1 35 msr CORTEX_A78_ACTLR2_EL1, x1 36 isb 371: 38 ret x17 39endfunc errata_a78_1688305_wa 40 41func check_errata_1688305 42 /* Applies to r0p0 and r1p0 */ 43 mov x1, #0x10 44 b cpu_rev_var_ls 45endfunc check_errata_1688305 46 47 /* -------------------------------------------------- 48 * Errata Workaround for Cortex A78 Errata #1941498. 49 * This applies to revisions r0p0, r1p0, and r1p1. 50 * x0: variant[4:7] and revision[0:3] of current cpu. 51 * Shall clobber: x0-x17 52 * -------------------------------------------------- 53 */ 54func errata_a78_1941498_wa 55 /* Compare x0 against revision <= r1p1 */ 56 mov x17, x30 57 bl check_errata_1941498 58 cbz x0, 1f 59 60 /* Set bit 8 in ECTLR_EL1 */ 61 mrs x1, CORTEX_A78_CPUECTLR_EL1 62 orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8 63 msr CORTEX_A78_CPUECTLR_EL1, x1 64 isb 651: 66 ret x17 67endfunc errata_a78_1941498_wa 68 69func check_errata_1941498 70 /* Check for revision <= r1p1, might need to be updated later. */ 71 mov x1, #0x11 72 b cpu_rev_var_ls 73endfunc check_errata_1941498 74 75 /* ------------------------------------------------- 76 * The CPU Ops reset function for Cortex-A78 77 * ------------------------------------------------- 78 */ 79func cortex_a78_reset_func 80 mov x19, x30 81 bl cpu_get_rev_var 82 mov x18, x0 83 84#if ERRATA_A78_1688305 85 mov x0, x18 86 bl errata_a78_1688305_wa 87#endif 88 89#if ERRATA_A78_1941498 90 mov x0, x18 91 bl errata_a78_1941498_wa 92#endif 93 94#if ENABLE_AMU 95 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 96 mrs x0, actlr_el3 97 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 98 msr actlr_el3, x0 99 100 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 101 mrs x0, actlr_el2 102 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 103 msr actlr_el2, x0 104 105 /* Enable group0 counters */ 106 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 107 msr CPUAMCNTENSET0_EL0, x0 108 109 /* Enable group1 counters */ 110 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 111 msr CPUAMCNTENSET1_EL0, x0 112#endif 113 114 isb 115 ret x19 116endfunc cortex_a78_reset_func 117 118 /* --------------------------------------------- 119 * HW will do the cache maintenance while powering down 120 * --------------------------------------------- 121 */ 122func cortex_a78_core_pwr_dwn 123 /* --------------------------------------------- 124 * Enable CPU power down bit in power control register 125 * --------------------------------------------- 126 */ 127 mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 128 orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 129 msr CORTEX_A78_CPUPWRCTLR_EL1, x0 130 isb 131 ret 132endfunc cortex_a78_core_pwr_dwn 133 134 /* 135 * Errata printing function for cortex_a78. Must follow AAPCS. 136 */ 137#if REPORT_ERRATA 138func cortex_a78_errata_report 139 stp x8, x30, [sp, #-16]! 140 141 bl cpu_get_rev_var 142 mov x8, x0 143 144 /* 145 * Report all errata. The revision-variant information is passed to 146 * checking functions of each errata. 147 */ 148 report_errata ERRATA_A78_1688305, cortex_a78, 1688305 149 report_errata ERRATA_A78_1941498, cortex_a78, 1941498 150 151 ldp x8, x30, [sp], #16 152 ret 153endfunc cortex_a78_errata_report 154#endif 155 156 /* --------------------------------------------- 157 * This function provides cortex_a78 specific 158 * register information for crash reporting. 159 * It needs to return with x6 pointing to 160 * a list of register names in ascii and 161 * x8 - x15 having values of registers to be 162 * reported. 163 * --------------------------------------------- 164 */ 165.section .rodata.cortex_a78_regs, "aS" 166cortex_a78_regs: /* The ascii list of register names to be reported */ 167 .asciz "cpuectlr_el1", "" 168 169func cortex_a78_cpu_reg_dump 170 adr x6, cortex_a78_regs 171 mrs x8, CORTEX_A78_CPUECTLR_EL1 172 ret 173endfunc cortex_a78_cpu_reg_dump 174 175declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ 176 cortex_a78_reset_func, \ 177 cortex_a78_core_pwr_dwn 178