| 4a6ebeec | 01-Jan-2022 |
Anders Dellien <anders.dellien@arm.com> |
feat(tc): enable SMMU for DPU
The SMMU needs to be enabled to support 8GB RAM
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ie81f2fc59886c52e9d6ed799ea73f49eb7a7c307 |
| ad60a42c | 08-Dec-2021 |
Anders Dellien <anders.dellien@arm.com> |
feat(tc): add reserved memory region for Gralloc
Gralloc for Android S uses dmabuf, we need to add reserved memory area
for these allocations
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
feat(tc): add reserved memory region for Gralloc
Gralloc for Android S uses dmabuf, we need to add reserved memory area
for these allocations
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: If869ac930fadc374ec435cae3847ba374584275b
show more ...
|
| 82117bb4 | 01-Jan-2022 |
Anders Dellien <anders.dellien@arm.com> |
feat(tc): enable GPU
Add DTS node for GPU to support hardware rendering in Android
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: I2cf2badf5b15e59a910f6cf7d3d30fdfaf4fe9ce |
| 68fe3cec | 08-Dec-2021 |
Anders Dellien <anders.dellien@arm.com> |
fix(tc): remove the bootargs node
We need to keep the kernel command line in Yocto, otherwise we
can't support AVB.
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ic291eb13620b30
fix(tc): remove the bootargs node
We need to keep the kernel command line in Yocto, otherwise we
can't support AVB.
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ic291eb13620b307f10354c2c2797c6fc9b053e83
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|
| 375b79bb | 10-Sep-2019 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
feat(stm32mp1-fdts): update NVMEM nodes
Set non-secure property on platform secure OTP nodes that non-secure
world is allowed to access through secure world services.
These are the SoC MAC address a
feat(stm32mp1-fdts): update NVMEM nodes
Set non-secure property on platform secure OTP nodes that non-secure
world is allowed to access through secure world services.
These are the SoC MAC address and the ST boards board_id OTPs.
Most of these were already done but it was missing for ED1 board.
Change-Id: Idfa6322d9d5c35285706d0b2d32ae09af38684a7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
show more ...
|
| ff8767cb | 25-Sep-2020 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
feat(stm32mp1-fdts): add nvmem_layout node and OTP definitions
A new nvmem_layout node includes nvmem platform-dependent layout
information, such as OTP NVMEM cell lists (phandle, name).
This list a
feat(stm32mp1-fdts): add nvmem_layout node and OTP definitions
A new nvmem_layout node includes nvmem platform-dependent layout
information, such as OTP NVMEM cell lists (phandle, name).
This list allows easy access to OTP offsets defined in BSEC node,
where more OTP definitions with offsets in bytes and length have
been added (replace hard-coded values).
Each board may redefine this list, especially for board_id info.
Change-Id: I910ae671b3bf3320ee6500fecc9ec335ae67bbda
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
show more ...
|
| a0e97243 | 28-Jan-2022 |
Yann Gautier <yann.gautier@st.com> |
fix(stm32mp1-fdts): remove mmc1 alias if not needed
If a board declares an mmc1 alias in its DT and is compiled without flags
STM32MP_EMMC or STM32MP_SDMMC, the DT will fail to build.
Add /delete-pr
fix(stm32mp1-fdts): remove mmc1 alias if not needed
If a board declares an mmc1 alias in its DT and is compiled without flags
STM32MP_EMMC or STM32MP_SDMMC, the DT will fail to build.
Add /delete-property/ mmc1; to correct this.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I1938ff99dc3d883f9174ee886f9ffa195ec60373
show more ...
|
| 59da207e | 13-Oct-2021 |
Davidson K <davidson.kumaresan@arm.com> |
feat(tc): enable tracing
Total Compute has ETE and TRBE tracing components and they have
to be enabled to capture the execution trace of the processor.
Signed-off-by: Davidson K <davidson.kumaresan
feat(tc): enable tracing
Total Compute has ETE and TRBE tracing components and they have
to be enabled to capture the execution trace of the processor.
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I3c86c11be2c655a61ecefa3eb2e4e3951577a113
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|
| 26cf5cf6 | 30-Apr-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
refactor(stm32mp1): remove the support of calibration result
The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when
refactor(stm32mp1): remove the support of calibration result
The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.
The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by CubeMX.
This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
the optional "st,phy-cal"
After this patch the built-in calibration is always executed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159
show more ...
|
| 67d95409 | 07-Jan-2021 |
Pascal Paillet <p.paillet@st.com> |
refactor(stm32mp1-fdts): update regulator description
Update regulator description to match with pmic driver updates.
vref_ddr does not support over-current protection.
vtt_ddr is set to sink source
refactor(stm32mp1-fdts): update regulator description
Update regulator description to match with pmic driver updates.
vref_ddr does not support over-current protection.
vtt_ddr is set to sink source mode.
Change-Id: I725f35b091ca8c230994c2b5f81693ebc97bf4aa
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
show more ...
|
| 87639aab | 03-Dec-2021 |
Anurag Koul <anurag.koul@arm.com> |
feat(morello): expose scmi protocols in fdts
Add 'firmware' node in morello-soc.dts to expose SCMI
support to the kernel. The SCMI protocols supported at
the moment are SCMI Base, Clock and Perf (DV
feat(morello): expose scmi protocols in fdts
Add 'firmware' node in morello-soc.dts to expose SCMI
support to the kernel. The SCMI protocols supported at
the moment are SCMI Base, Clock and Perf (DVFS).
The current mailbox memory region in MHU SRAM has an issue
with any access not aligned to a 4-byte boundary. So, the SCMI
mailbox memory region has been relocated to AP non-trusted
RAM to get around the problem.
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Change-Id: Ibcbce8823b751a0fc3be7e9bc3588c1dc47ae024
show more ...
|
| 572c8ce2 | 15-Sep-2021 |
Manoj Kumar <manoj.kumar3@arm.com> |
feat(morello): add DTS for Morello SoC platform
Added Morello SoC specific DTS file.
Change-Id: I099e74ec95ed9e1b47f7d5a68b0dd1e251439e11
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-of
feat(morello): add DTS for Morello SoC platform
Added Morello SoC specific DTS file.
Change-Id: I099e74ec95ed9e1b47f7d5a68b0dd1e251439e11
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
show more ...
|
| e8b7a804 | 25-Aug-2021 |
Anurag Koul <anurag.koul@arm.com> |
fix(morello): fix SoC reference clock frequency
Morello Specification specifies the system
reference clock frequency as 50MHz so the frequency
has been changed from 100MHz to 50MHz.
Change-Id: I255
fix(morello): fix SoC reference clock frequency
Morello Specification specifies the system
reference clock frequency as 50MHz so the frequency
has been changed from 100MHz to 50MHz.
Change-Id: I25577b04aa54ed82b7e9df69ac8e40ac54a9b111
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
show more ...
|
| ae2289b9 | 08-Nov-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(arm_fpga): Change PL011 UART IRQ" into integration |
| 683bb4d7 | 06-Nov-2021 |
André Przywara <andre.przywara@arm.com> |
Merge changes from topic "arm_fpga_auto" into integration
* changes:
feat(arm_fpga): write UART baud base clock frequency into DTB
feat(arm_fpga): query PL011 to learn system frequency
refacto
Merge changes from topic "arm_fpga_auto" into integration
* changes:
feat(arm_fpga): write UART baud base clock frequency into DTB
feat(arm_fpga): query PL011 to learn system frequency
refactor(arm_fpga): move command line code into separate function
fix(fdt): avoid output on missing DT property
feat(arm_fpga): add ITS autodetection
feat(arm_fpga): determine GICR base by probing
feat(gicv3): introduce GIC component identification
feat(libfdt): also allow changing base address
fix(arm_fpga): avoid re-linking from executable ELF file
show more ...
|
| 8d260291 | 02-Nov-2021 |
Yann Gautier <yann.gautier@st.com> |
fix(fdts stm32mp1): correct copyright dates
Add 2021 year in the file header Copyright line.
Change-Id: I09f7bef1f746c429ff308286169354e58648a1cd
Signed-off-by: Yann Gautier <yann.gautier@st.com> |
| 195381a9 | 14-May-2021 |
Andre Przywara <andre.przywara@arm.com> |
fix(arm_fpga): Change PL011 UART IRQ
About a year ago there was a change in the underlying Arm platform design
framework, which lead to a reorganisation of the interrupt map (to make
room for multi-
fix(arm_fpga): Change PL011 UART IRQ
About a year ago there was a change in the underlying Arm platform design
framework, which lead to a reorganisation of the interrupt map (to make
room for multi-chip designs).
This lead to the PL011 debug UART interrupt to move from SPI 115 to SPI
415. Unfortunately there is not a good or easy way to auto-detect this
change: Flooding the TX FIFO and checking GICD_ISPENDR registers might
be possible, but sounds a bit over the top for BL31.
So we would need to break one group of images: newer ones, as we do right
now, or older ones.
By now every interesting FPGA image seems to use the newer IRQ, so in
the interest of having a smooth experience for most users, lets switch
to this IRQ.
When people are interested in older images, they can either change the
number back in the .dts file, or provide a patched DTB on the FPGA
command line.
Change-Id: I3c7e7b711f5142813bd94eecde3095a4fc555bb3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
show more ...
|
| d850169c | 01-Sep-2021 |
Andre Przywara <andre.przywara@arm.com> |
feat(arm_fpga): query PL011 to learn system frequency
The Arm FPGAs run in mostly one clock domain, which is used for the CPU
cores, the generic timer, and also the UART baudrate base clock. This
si
feat(arm_fpga): query PL011 to learn system frequency
The Arm FPGAs run in mostly one clock domain, which is used for the CPU
cores, the generic timer, and also the UART baudrate base clock. This
single clock can have different rates, to compensate for different IP
complexity. So far most images used 10 MHz, but different rates start to
appear.
To avoid patching both the arch timer frequency and UART baud base fixed
clock in the DTB manually, we would like to set the clock rate
automatically. Fortunately the SCP firmware has the actual clock rate
hard coded, and already programs the PL011 UART baud divider register
with the correct value to achieve a 38400 bps baudrate.
So read the two PL011 baudrate divider values and re-calculate the
original base clock from there, to use as the arch timer frequency. If
the arch timer DT node contains a clock-frequency property, we use that
instead, to support overriding and disabling this autodetection.
Change-Id: I9857fbb418deb4644aeb2816f1102796f9bfd3bb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
show more ...
|
| d7e39c43 | 20-Jul-2021 |
Andre Przywara <andre.przywara@arm.com> |
feat(arm_fpga): add ITS autodetection
Some FPGAs come with a GIC that has an ITS block configured. Since the
ITS sits between the distributor and redistributors, we can autodetect
that, and already
feat(arm_fpga): add ITS autodetection
Some FPGAs come with a GIC that has an ITS block configured. Since the
ITS sits between the distributor and redistributors, we can autodetect
that, and already adjust the GICR base address.
To also make this ITS usable, add an ITS node to our base DTB, and
remove that should we not find an ITS during the scan for the
redistributor. This allows to use the same TF-A binary for FPGA images
with or without an ITS.
Change-Id: I4c0417dec7bccdbad8cbca26fa2634950fc50a66
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
show more ...
|
| fea7f369 | 29-Oct-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "st_dt_update" into integration
* changes:
fix(fdts stm32mp1): update PLL nodes for ED1/EV1 boards
fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards
feat(fdts st
Merge changes from topic "st_dt_update" into integration
* changes:
fix(fdts stm32mp1): update PLL nodes for ED1/EV1 boards
fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards
feat(fdts stm32mp1): delete nodes for non-used boot devices
fix(fdts stm32mp1): use 'kHz' as kilohertz abbreviation
refactor(fdts stm32mp1): move STM32MP DDR node
feat(fdts stm32mp1): align DT with latest kernel
show more ...
|
| cdbbb9f7 | 17-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(fdts stm32mp1): update PLL nodes for ED1/EV1 boards
Align STM32MP157C-ED1/EV1 boards PLL nodes with what is done
for DK boards.
Change-Id: I91be408ea1d9b0474caf4965175df33792b7e11e
Signed-off-b
fix(fdts stm32mp1): update PLL nodes for ED1/EV1 boards
Align STM32MP157C-ED1/EV1 boards PLL nodes with what is done
for DK boards.
Change-Id: I91be408ea1d9b0474caf4965175df33792b7e11e
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
show more ...
|
| 3e881a88 | 17-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards
Set Ethernet source clock on PLL4P. This is required to enable PTP.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ia64fbb
fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards
Set Ethernet source clock on PLL4P. This is required to enable PTP.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ia64fbb681d3f04f2b90f373c5eb044f5daa2836c
show more ...
|
| 4357db5b | 16-Dec-2020 |
Yann Gautier <yann.gautier@st.com> |
feat(fdts stm32mp1): delete nodes for non-used boot devices
Cleanup the BL2 device tree file by removing the nodes for the devices
that are not used to boot, depending on compilation flags.
In SDMMC
feat(fdts stm32mp1): delete nodes for non-used boot devices
Cleanup the BL2 device tree file by removing the nodes for the devices
that are not used to boot, depending on compilation flags.
In SDMMC boot, the gain for the dtb file is about 2.3kB.
Change-Id: I3ba13e06dd22b52cff96f51db2dac94b532c81ae
Signed-off-by: Yann Gautier <yann.gautier@st.com>
show more ...
|
| 4955d08d | 09-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
fix(fdts stm32mp1): use 'kHz' as kilohertz abbreviation
The kilohertz unit abbreviation should read 'kHz' in DDR
settings files of stm32mp15.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.
fix(fdts stm32mp1): use 'kHz' as kilohertz abbreviation
The kilohertz unit abbreviation should read 'kHz' in DDR
settings files of stm32mp15.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifa363094f58dd943ef78c653c3e470a216739b41
show more ...
|
| 8cafbda6 | 25-Feb-2021 |
Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> |
refactor(fdts stm32mp1): move STM32MP DDR node
Move the generic part of DDR node in SOC dtsi file.
DDR dtsi files only include the part configured by CubeMX tool.
Signed-off-by: Patrick Delaunay <p
refactor(fdts stm32mp1): move STM32MP DDR node
Move the generic part of DDR node in SOC dtsi file.
DDR dtsi files only include the part configured by CubeMX tool.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I8c211e9782604da32aeaab98d0ef75fb1cd9c58d
show more ...
|