| b9f7fcc9 | 28-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I8d334231,Icd1ce8ec,Ic963c21c into integration
* changes:
feat(tc0): add cpu capacity to provide scheduling information
fix(tc0): remove "arm,psci" from psci node
feat(tc0): upda
Merge changes I8d334231,Icd1ce8ec,Ic963c21c into integration
* changes:
feat(tc0): add cpu capacity to provide scheduling information
fix(tc0): remove "arm,psci" from psci node
feat(tc0): update mhuv2 dts node to align with upstream driver
show more ...
|
| 814646b4 | 27-May-2021 |
Usama Arif <usama.arif@arm.com> |
fix(tc0): remove "arm,psci" from psci node
"arm,psci" expects the FIDs for cpu-on, cpu-off and cpu-suspend, which
arent present in the device tree, so remove it from psci compatible.
Signed-off-by:
fix(tc0): remove "arm,psci" from psci node
"arm,psci" expects the FIDs for cpu-on, cpu-off and cpu-suspend, which
arent present in the device tree, so remove it from psci compatible.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: Icd1ce8ec7fd3f270925e4b3d5d0187088ffe4ba5
show more ...
|
| c3c6732f | 21-Apr-2021 |
Grzegorz Szymaszek <gszymaszek@short.pl> |
fdts: stm32mp1: add support for the Seeed Odyssey SoM and board
Seeed Studio’s SoM‐STM32MP157C is a System‐on‐Module that integrates the
STM32MP157C MPU (the 650 MHz dual‐core variant with a GPU and
fdts: stm32mp1: add support for the Seeed Odyssey SoM and board
Seeed Studio’s SoM‐STM32MP157C is a System‐on‐Module that integrates the
STM32MP157C MPU (the 650 MHz dual‐core variant with a GPU and a
cryptographic processor) the STPMIC1A PMIC, 512 MB of DDR3 RAM and a
4 GB eMMC. There are two LEDs as well, one hardwired to the PMIC’s VDD
output, and the other available at the MPU’s port PG3. The SoM can be
plugged into a carrier board using its three 70‑pin connectors.
Seeed Odyssey‐STM32MP157C is the reference carrier board for the SoM in
a Raspberry Pi‐like form factor. It features a WiFi/Bluetooth chip, a
microSD card port and various I/O interfaces.
The device tree is based on the DKx boards. TF‑A was successfully tested
on the board with Buildroot 2021.02 and U-Boot 2021.04.
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: I2c9aecc925561e8d338dddbb192d3bb23a533914
show more ...
|
| 0e480e0e | 21-Apr-2021 |
Grzegorz Szymaszek <gszymaszek@short.pl> |
fdts: stm32mp1: add alternative SDMMC2 pins to the pinctrl
The new pins—PA8, PA9, PE5, and PC7—are described in a new pinctrl node
named “sdmmc2-d47-3”, AKA phandle “sdmmc2_d47_pins_d”. These names
fdts: stm32mp1: add alternative SDMMC2 pins to the pinctrl
The new pins—PA8, PA9, PE5, and PC7—are described in a new pinctrl node
named “sdmmc2-d47-3”, AKA phandle “sdmmc2_d47_pins_d”. These names are
identical to their Linux kernel counterparts (commit
7af08140979a6e7e12b78c93b8625c8d25b084e2).
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: Ie6a019f4361790f6b5d4910ce1e7b507a6c6a21a
show more ...
|
| 214b4f9a | 21-Apr-2021 |
Grzegorz Szymaszek <gszymaszek@short.pl> |
fdts: stm32mp1: add I2C2 pins in the pinctrl
Some STM32MP1‐based boards, like Seeed Studio’s SoM‐STM32MP157C, have
the SoC connected to the PMIC via I2C2 instead of I2C4 (which is used on
the offici
fdts: stm32mp1: add I2C2 pins in the pinctrl
Some STM32MP1‐based boards, like Seeed Studio’s SoM‐STM32MP157C, have
the SoC connected to the PMIC via I2C2 instead of I2C4 (which is used on
the official ST development boards). This commit brings TF‑A one step
closer to boot on such boards.
The pins used, PH4 and PH5, are described in a new pinctrl node named
“i2c2-0”, AKA phandle “i2c2_pins_a”. These names are identical to their
Linux kernel counterparts (commit
7af08140979a6e7e12b78c93b8625c8d25b084e2).
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Change-Id: Ief6f0a632cfa992dcf3fed95d266ad6a07a96fe0
show more ...
|
| dfa6c540 | 12-Apr-2021 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Plat FVP: Fix Generic Timer interrupt types
The Arm Generic Timer specification mandates that the
interrupt associated with each timer is low level triggered,
see:
Arm Cortex-A76 Core:
"Each timer
Plat FVP: Fix Generic Timer interrupt types
The Arm Generic Timer specification mandates that the
interrupt associated with each timer is low level triggered,
see:
Arm Cortex-A76 Core:
"Each timer provides an active-LOW interrupt output to the SoC."
Arm Cortex-A53 MPCore Processor:
"It generates timer events as active-LOW interrupt outputs and
event streams."
The following files in fdts\
fvp-base-gicv3-psci-common.dtsi
fvp-base-gicv3-psci-aarch32-common.dtsi
fvp-base-gicv2-psci-aarch32.dts
fvp-base-gicv2-psci.dts
fvp-foundation-gicv2-psci.dts
fvp-foundation-gicv3-psci.dts
describe interrupt types as edge rising
IRQ_TYPE_EDGE_RISING = 0x01:
interrupts = <1 13 0xff01>,
<1 14 0xff01>,
<1 11 0xff01>,
<1 10 0xff01>;
, see include\dt-bindings\interrupt-controller\arm-gic.h:
which causes Linux to generate the warnings below:
arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low
arch_timer: WARNING: Please fix your firmware
This patch adds GIC_CPU_MASK_RAW macro definition to
include\dt-bindings\interrupt-controller\arm-gic.h,
modifies interrupt type to IRQ_TYPE_LEVEL_LOW and
makes use of type definitions in arm-gic.h.
Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
show more ...
|