1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/pinctrl/stm32-pinfunc.h> 7 8&pinctrl { 9 fmc_pins_a: fmc-0 { 10 pins1 { 11 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ 12 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ 13 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */ 14 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */ 15 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ 16 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ 17 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ 18 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ 19 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ 20 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ 21 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ 22 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ 23 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */ 24 bias-disable; 25 drive-push-pull; 26 slew-rate = <1>; 27 }; 28 pins2 { 29 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */ 30 bias-pull-up; 31 }; 32 }; 33 34 i2c2_pins_a: i2c2-0 { 35 pins { 36 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ 37 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 38 bias-disable; 39 drive-open-drain; 40 slew-rate = <0>; 41 }; 42 }; 43 44 qspi_clk_pins_a: qspi-clk-0 { 45 pins { 46 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ 47 bias-disable; 48 drive-push-pull; 49 slew-rate = <3>; 50 }; 51 }; 52 53 qspi_bk1_pins_a: qspi-bk1-0 { 54 pins1 { 55 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ 56 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ 57 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ 58 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ 59 bias-disable; 60 drive-push-pull; 61 slew-rate = <1>; 62 }; 63 pins2 { 64 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ 65 bias-pull-up; 66 drive-push-pull; 67 slew-rate = <1>; 68 }; 69 }; 70 71 qspi_bk2_pins_a: qspi-bk2-0 { 72 pins1 { 73 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ 74 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ 75 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ 76 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ 77 bias-disable; 78 drive-push-pull; 79 slew-rate = <1>; 80 }; 81 pins2 { 82 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ 83 bias-pull-up; 84 drive-push-pull; 85 slew-rate = <1>; 86 }; 87 }; 88 89 rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 { 90 pins { 91 pinmux = <STM32_PINMUX('I', 8, ANALOG)>; /* RTC_OUT2_RMP */ 92 }; 93 }; 94 95 sdmmc1_b4_pins_a: sdmmc1-b4-0 { 96 pins1 { 97 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 98 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 99 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 100 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ 101 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 102 slew-rate = <1>; 103 drive-push-pull; 104 bias-disable; 105 }; 106 pins2 { 107 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 108 slew-rate = <2>; 109 drive-push-pull; 110 bias-disable; 111 }; 112 }; 113 114 sdmmc1_dir_pins_a: sdmmc1-dir-0 { 115 pins1 { 116 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 117 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ 118 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 119 slew-rate = <1>; 120 drive-push-pull; 121 bias-pull-up; 122 }; 123 pins2{ 124 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ 125 bias-pull-up; 126 }; 127 }; 128 129 sdmmc2_b4_pins_a: sdmmc2-b4-0 { 130 pins1 { 131 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 132 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 133 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 134 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 135 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 136 slew-rate = <1>; 137 drive-push-pull; 138 bias-pull-up; 139 }; 140 pins2 { 141 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 142 slew-rate = <2>; 143 drive-push-pull; 144 bias-pull-up; 145 }; 146 }; 147 148 sdmmc2_b4_pins_b: sdmmc2-b4-1 { 149 pins1 { 150 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 151 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 152 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 153 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 154 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 155 slew-rate = <1>; 156 drive-push-pull; 157 bias-disable; 158 }; 159 pins2 { 160 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 161 slew-rate = <2>; 162 drive-push-pull; 163 bias-disable; 164 }; 165 }; 166 167 sdmmc2_d47_pins_a: sdmmc2-d47-0 { 168 pins { 169 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 170 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 171 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ 172 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ 173 slew-rate = <1>; 174 drive-push-pull; 175 bias-pull-up; 176 }; 177 }; 178 179 uart4_pins_a: uart4-0 { 180 pins1 { 181 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ 182 bias-disable; 183 drive-push-pull; 184 slew-rate = <0>; 185 }; 186 pins2 { 187 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 188 bias-disable; 189 }; 190 }; 191 192 uart4_pins_b: uart4-1 { 193 pins1 { 194 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ 195 bias-disable; 196 drive-push-pull; 197 slew-rate = <0>; 198 }; 199 pins2 { 200 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 201 bias-disable; 202 }; 203 }; 204 205 uart7_pins_a: uart7-0 { 206 pins1 { 207 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */ 208 bias-disable; 209 drive-push-pull; 210 slew-rate = <0>; 211 }; 212 pins2 { 213 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */ 214 <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */ 215 <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */ 216 bias-disable; 217 }; 218 }; 219 220 uart7_pins_b: uart7-1 { 221 pins1 { 222 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */ 223 bias-disable; 224 drive-push-pull; 225 slew-rate = <0>; 226 }; 227 pins2 { 228 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */ 229 bias-disable; 230 }; 231 }; 232 233 usart2_pins_a: usart2-0 { 234 pins1 { 235 pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ 236 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 237 bias-disable; 238 drive-push-pull; 239 slew-rate = <3>; 240 }; 241 pins2 { 242 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ 243 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ 244 bias-disable; 245 }; 246 }; 247 248 usart3_pins_a: usart3-0 { 249 pins1 { 250 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 251 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 252 bias-disable; 253 drive-push-pull; 254 slew-rate = <0>; 255 }; 256 pins2 { 257 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ 258 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ 259 bias-disable; 260 }; 261 }; 262 263 usart3_pins_b: usart3-1 { 264 pins1 { 265 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 266 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 267 bias-disable; 268 drive-push-pull; 269 slew-rate = <0>; 270 }; 271 pins2 { 272 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ 273 <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ 274 bias-disable; 275 }; 276 }; 277 278 usbotg_hs_pins_a: usbotg_hs-0 { 279 pins { 280 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ 281 }; 282 }; 283 284 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { 285 pins { 286 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */ 287 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */ 288 }; 289 }; 290}; 291 292&pinctrl_z { 293 i2c4_pins_a: i2c4-0 { 294 pins { 295 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ 296 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ 297 bias-disable; 298 drive-open-drain; 299 slew-rate = <0>; 300 }; 301 }; 302}; 303