| 7585ec4d | 02-Jul-2021 |
Sughosh Ganu <sughosh.ganu@linaro.org> |
feat(partition): copy the partition GUID into the partition structure
Copy the UniquePartitionGUID member of a GPT partition entry into the partition_entry structure. This GUID is subsequently used
feat(partition): copy the partition GUID into the partition structure
Copy the UniquePartitionGUID member of a GPT partition entry into the partition_entry structure. This GUID is subsequently used to identify the image to boot on a platform which supports multiple partitions of firmware components using the FWU metadata structure.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Change-Id: I8b55a1ee7deb1353886fbd8ebde53055d677fee0
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| 0b1cfc29 | 27-Jan-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(st-ddr): add missing debug.h" into integration |
| e3a23497 | 30-Dec-2021 |
Maninder Singh <maninder.singh_1@nxp.com> |
fix(nxp-drivers): ddr: corrects mapping of HNFs nodes
Corrects mapping of HNFs nodes with SNFs nodes based on their proximity in CCN508 ring when disabling unused ddr controller.
When DDRC 2 disabl
fix(nxp-drivers): ddr: corrects mapping of HNFs nodes
Corrects mapping of HNFs nodes with SNFs nodes based on their proximity in CCN508 ring when disabling unused ddr controller.
When DDRC 2 disabled and DDR 1 is active the mapping is 0x3/3/8/8/8/8/3/3. When DDRC 1 is disabled and DDR2 is active the mapping is 0x 18/18/13/13/13/13/18/18 .
Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com> Signed-off-by: JaiPrakash Singh <JaiPrakash.singh@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I6ec1e02f8ad7e8bb8628913625ff5313a054dcc6
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| b1963003 | 25-Jan-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "decouple-tb-mb" into integration
* changes: refactor(renesas): disable CRYPTO_SUPPORT option refactor(fvp): avoid Measured-Boot dependency on Trusted-Boot refactor(me
Merge changes from topic "decouple-tb-mb" into integration
* changes: refactor(renesas): disable CRYPTO_SUPPORT option refactor(fvp): avoid Measured-Boot dependency on Trusted-Boot refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot build: introduce CRYPTO_SUPPORT build option
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| b57d9d6f | 20-Jan-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "new_ls1043a" into integration
* changes: docs(maintainers): update nxp layerscape maintainers docs(plat/nxp/layerscape): add ls1043a soc and board support feat(plat/n
Merge changes from topic "new_ls1043a" into integration
* changes: docs(maintainers): update nxp layerscape maintainers docs(plat/nxp/layerscape): add ls1043a soc and board support feat(plat/nxp/ls1043ardb): add ls1043ardb board support feat(plat/nxp/ls1043a): add ls1043a soc support refactor(plat/ls1043): remove old implementation for platform ls1043 feat(nxp/driver/dcfg): add some macro definition fix(nxp/common/setup): increase soc name maximum length feat(nxp/common/errata): add SoC erratum a008850 feat(nxp/driver/tzc380): add tzc380 platform driver support feat(tzc380): add sub-region register definition feat(nxp/common/io): add ifc nor and nand as io devices feat(nxp/driver/ifc_nand): add IFC NAND flash driver feat(nxp/driver/ifc_nor): add IFC nor flash driver feat(nxp/driver/csu): add bypass bit mask definition feat(nxp/driver/dcfg): add gic address align register definition feat(nxp/common/rcpm): add RCPM2 registers definition fix(nxp/common/setup): fix total dram size checking feat(nxp/common): add CORTEX A53 helper functions
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| de9e57ff | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/driver/tzc380): add tzc380 platform driver support
Added TZC380 platform driver support.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Id0aa6cb64fa7af79dd44e0dbb0e62cb2fd4cb824 |
| 28279cf2 | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/driver/ifc_nand): add IFC NAND flash driver
Support IFC NAND flash as boot device.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Chang
feat(nxp/driver/ifc_nand): add IFC NAND flash driver
Support IFC NAND flash as boot device.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I1aba7035ff70b179915e181c04e7b00be2066abe
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| e2fdc77b | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/driver/ifc_nor): add IFC nor flash driver
Add IFC Nor flash driver.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I3275664b8848d0fe3c15ed92d95fb19adbf57f84 |
| 15ca2c5e | 19-Jan-2022 |
Yann Gautier <yann.gautier@st.com> |
fix(st-ddr): add missing debug.h
In a later patch, the stm32mp1_def.h will be reworked. The inclusion of common/debug.h may not be done there through another included file. Add this header inclusion
fix(st-ddr): add missing debug.h
In a later patch, the stm32mp1_def.h will be reworked. The inclusion of common/debug.h may not be done there through another included file. Add this header inclusion in the files that need it.
Change-Id: I83687f7910032ca38c0856796580a650e1e41a68 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 44fb470b | 07-Sep-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(st-clock): correct types in error messages
Replace wrong %d with the correct types. This issue was found with the compilation flag: -Wformat-signedness
Change-Id: Iec3817a245f964ce444b59561b777
fix(st-clock): correct types in error messages
Replace wrong %d with the correct types. This issue was found with the compilation flag: -Wformat-signedness
Change-Id: Iec3817a245f964ce444b59561b777ce06c51a60a Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| b208e3da | 15-May-2020 |
Gabriel Fernandez <gabriel.fernandez@st.com> |
refactor(st-clock): directly use oscillator name
Instead of transmitting an 'enum stm32mp_osc_id', just send directly the clock name with a 'const char *'
Change-Id: I866b05cbb1685a9b9f80e63dcd5ba7
refactor(st-clock): directly use oscillator name
Instead of transmitting an 'enum stm32mp_osc_id', just send directly the clock name with a 'const char *'
Change-Id: I866b05cbb1685a9b9f80e63dcd5ba7b1d35fc932 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
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| 31e9750b | 02-Jul-2019 |
Lionel Debieve <lionel.debieve@st.com> |
feat(st-clock): check HSE configuration in serial boot
In case of programmer mode, the bootrom manages to auto-detect HSE clock configuration. In order to detect a bad device tree setting in BL2, it
feat(st-clock): check HSE configuration in serial boot
In case of programmer mode, the bootrom manages to auto-detect HSE clock configuration. In order to detect a bad device tree setting in BL2, it will crash during programming if the configuration is not aligned with the auto-detection.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I230697695745d6282d14b1ebfa6e4c4caa0cd8e2
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| bcccdacc | 01-Jul-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
feat(st-clock): manage disabled oscillator
Support "disabled" status for oscillator in device tree.
At boot time, the clock tree initialization performs the following tasks: - enabling of the oscil
feat(st-clock): manage disabled oscillator
Support "disabled" status for oscillator in device tree.
At boot time, the clock tree initialization performs the following tasks: - enabling of the oscillators present in the device tree and not disabled, - disabling of the HSI oscillator if the node is absent or disabled (always activated by bootROM).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Change-Id: I176276022334f3d97ba0250b54062f0ae970e239
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| 964e5ff1 | 13-Nov-2019 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
refactor(st-clock): improve DT parsing for PLL nodes
Add a function to get PLL settings from DT: "cfg" property is mandatory, an error is generated if not found. "frac" is optional, default value is
refactor(st-clock): improve DT parsing for PLL nodes
Add a function to get PLL settings from DT: "cfg" property is mandatory, an error is generated if not found. "frac" is optional, default value is returned if not found. "csg" is optional too, a boolean value indicates if it has been found, and its value is updated.
Store each PLL node validity information, this avoids parsing DT several times.
Change-Id: I039466fbe1e67d160f7112814e7bb63b661804d0 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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| 0aa0b3af | 16-Dec-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot
Measured-Boot and Trusted-Boot are orthogonal to each other and hence removed dependency of Trusted-Boot on Measured-Boot by m
refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot
Measured-Boot and Trusted-Boot are orthogonal to each other and hence removed dependency of Trusted-Boot on Measured-Boot by making below changes - 1. BL1 and BL2 main functions are used for initializing Crypto module instead of the authentication module 2. Updated Crypto module registration macro for MEASURED_BOOT with only necessary callbacks for calculating image hashes 3. The 'load_auth_image' function is now used for the image measurement during Trusted or Non-Trusted Boot flow
Change-Id: I3570e80bae8ce8f5b58d84bd955aa43e925d9fff Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| f7a92518 | 07-Jan-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "st_ddr_updates" into integration
* changes: refactor(st-ddr): move basic tests in a dedicated file refactor(st-ddr): reorganize generic and specific elements feat(stm
Merge changes from topic "st_ddr_updates" into integration
* changes: refactor(st-ddr): move basic tests in a dedicated file refactor(st-ddr): reorganize generic and specific elements feat(stm32mp1): allow configuration of DDR AXI ports number refactor(st-ddr): update parameter array initialization feat(st-ddr): add read valid training support refactor(stm32mp1): remove the support of calibration result fix(st-ddr): correct DDR warnings
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| 5b096283 | 05-Jan-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I19f713de,Ib5bda93d,Id5dafc04,Id20e65e2 into integration
* changes: feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3 feat(plat/rcar3): modify type for Internal function ar
Merge changes I19f713de,Ib5bda93d,Id5dafc04,Id20e65e2 into integration
* changes: feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3 feat(plat/rcar3): modify type for Internal function argument feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53 fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53
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| f8183f4d | 05-Jan-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(ufs): delete call to inv_dcache_range for utrd" into integration |
| 63d21598 | 02-Mar-2021 |
Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> |
refactor(st-ddr): move basic tests in a dedicated file
These basic tests are generic and should be used independently of the driver, depending on the plaftorm characteristics.
Change-Id: I38161b659
refactor(st-ddr): move basic tests in a dedicated file
These basic tests are generic and should be used independently of the driver, depending on the plaftorm characteristics.
Change-Id: I38161b659ef2a23fd30a56e1c9b1bd98461a2fe4 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
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| 06e55dc8 | 18-May-2021 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
refactor(st-ddr): reorganize generic and specific elements
stm32mp_ddrctl structure contains DDRCTRL registers definitions. stm32mp_ddr_info contains general DDR information extracted from DT. stm32
refactor(st-ddr): reorganize generic and specific elements
stm32mp_ddrctl structure contains DDRCTRL registers definitions. stm32mp_ddr_info contains general DDR information extracted from DT. stm32mp_ddr_size moves to the generic side. stm32mp1_ddr_priv contains platform private data.
stm32mp_ddr_dt_get_info() and stm32mp_ddr_dt_get_param() allow to retrieve data from DT. They are located in new generic c/h files in which stm32mp_ddr_param structure is declared. Platform makefile is updated.
Adapt driver with this new classification.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: I4187376c9fff1a30e7a94407d188391547107997
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| 88f4fb8f | 17-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp1): allow configuration of DDR AXI ports number
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default. It will allow choosing single or dual AXI ports for DDR.
Change-Id
feat(stm32mp1): allow configuration of DDR AXI ports number
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default. It will allow choosing single or dual AXI ports for DDR.
Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| ba7d2e26 | 25-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
refactor(st-ddr): update parameter array initialization
Force alignment of the size of parameters array with the expected value by the binding. The registers dynamic structs are removed as not used
refactor(st-ddr): update parameter array initialization
Force alignment of the size of parameters array with the expected value by the binding. The registers dynamic structs are removed as not used in TF-A.
Change-Id: I7a41f355a435f54fbf23f468cca87c7f8f7e69e8 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 5def13eb | 10-Sep-2021 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
feat(st-ddr): add read valid training support
Add the read data eye training = training for optimal read valid placement (RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.
Sig
feat(st-ddr): add read valid training support
Add the read data eye training = training for optimal read valid placement (RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: I7ac1c77c21ebc30315b532741f2f255c2312d5b2
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| 26cf5cf6 | 30-Apr-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
refactor(stm32mp1): remove the support of calibration result
The support of a predefined DDR PHY tuning result is removed for STM32MP1 driver because it is not needed at the supported frequency when
refactor(stm32mp1): remove the support of calibration result
The support of a predefined DDR PHY tuning result is removed for STM32MP1 driver because it is not needed at the supported frequency when built-in calibration is executed.
The calibration parameters were provided in the device tree by the optional node "st,phy-cal", activated in ddr helper file by the compilation flag DDR_PHY_CAL_SKIP and filled with values generated by CubeMX.
This patch - updates the binding file to remove "st,phy-cal" support - updates the device trees and remove the associated defines - simplifies the STM32MP1 DDR driver and remove the support of the optional "st,phy-cal"
After this patch the built-in calibration is always executed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159
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| a078134e | 07-Sep-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(st-ddr): correct DDR warnings
Replace %d with %u in logs, to avoid warning when -Wformat-signedness is enabled. And correct the order of includes.
Change-Id: I7c711a37fc1deceb8853831a8a09ae5042
fix(st-ddr): correct DDR warnings
Replace %d with %u in logs, to avoid warning when -Wformat-signedness is enabled. And correct the order of includes.
Change-Id: I7c711a37fc1deceb8853831a8a09ae50422859c9 Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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