| 4490b796 | 18-Jun-2021 |
Christophe Kerello <christophe.kerello@foss.st.com> |
fix(spi_nand): check correct manufacturer id
On most of SPI NAND, the read id command needs a dummy byte,
except GIGADEVICE SPI NAND that needs an address.
To be compliant with all memories provider
fix(spi_nand): check correct manufacturer id
On most of SPI NAND, the read id command needs a dummy byte,
except GIGADEVICE SPI NAND that needs an address.
To be compliant with all memories providers, the first byte returns
by the READ_ID command is not relevant (garbage).
Change-Id: Ife74ccab333dd1a04799abe230d3f07fa6ea1edb
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| c3327408 | 24-Nov-2020 |
Lionel Debieve <lionel.debieve@st.com> |
fix(drivers/mtd): macronix quad enable bit issue
Invert test logic on the status register control to
fix issue when the bit SR_QUAD_EN_MX is not set.
Change-Id: I8b2f140219f124336bf96462abf9d9445d0
fix(drivers/mtd): macronix quad enable bit issue
Invert test logic on the status register control to
fix issue when the bit SR_QUAD_EN_MX is not set.
Change-Id: I8b2f140219f124336bf96462abf9d9445d0308bc
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| ea306945 | 26-Aug-2020 |
Lionel Debieve <lionel.debieve@st.com> |
nand: raw_nand: fix timeout issue in nand_wait_ready
nand_wait_ready is called with a millisecond delay
but the timeout used a micro second. Fixing the conversion
in the timeout call.
The prototype
nand: raw_nand: fix timeout issue in nand_wait_ready
nand_wait_ready is called with a millisecond delay
but the timeout used a micro second. Fixing the conversion
in the timeout call.
The prototype of the function is also changed to use an unsigned int
parameter.
Change-Id: Ia3281be7980477dfbfdb842308d35ecd8b926fb8
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| a13550d0 | 24-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
Add SPI-NOR framework
SPI-NOR framework is based on SPI-MEM framework using
spi_mem_op execution interface.
It implements read functions and allows NOR configuration
up to quad mode.
Default manage
Add SPI-NOR framework
SPI-NOR framework is based on SPI-MEM framework using
spi_mem_op execution interface.
It implements read functions and allows NOR configuration
up to quad mode.
Default management is 1 data line but it can be overridden
by platform.
It also includes specific quad mode configuration for
Spansion, Micron and Macronix memories.
Change-Id: If49502b899b4a75f6ebc3190f6bde1013651197f
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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| c3e57739 | 25-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
Add SPI-NAND framework
This framework supports SPI-NAND and is based on the
SPI-MEM framework for SPI operations. It uses a common high
level access using the io_mtd.
It is limited to the read func
Add SPI-NAND framework
This framework supports SPI-NAND and is based on the
SPI-MEM framework for SPI operations. It uses a common high
level access using the io_mtd.
It is limited to the read functionalities.
Default behavior is the basic one data line operation
but it could be overridden by platform.
Change-Id: Icb4e0887c4003a826f47c876479dd004a323a32b
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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| 05e6a563 | 24-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
Add SPI-MEM framework
This framework supports SPI operations using a common
spi_mem_op structure:
- command
- addr
- dummy
- data
The framework manages SPI bus configuration:
- speed
- bus wi
Add SPI-MEM framework
This framework supports SPI operations using a common
spi_mem_op structure:
- command
- addr
- dummy
- data
The framework manages SPI bus configuration:
- speed
- bus width (Up to quad mode)
- chip select
Change-Id: Idc2736c59bfc5ac6e55429eba5d385275ea3fbde
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
show more ...
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