Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration

* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls102

Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration

* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls1028ardb board support
feat(plat/nxp/ls1028a): add ls1028a soc support
feat(plat/nxp/common): define default SD buffer
feat(driver/nxp/xspi): add MT35XU02G flash info
feat(plat/nxp/common): add SecMon register definition for ch_3_2
feat(driver/nxp/dcfg): define RSTCR_RESET_REQ
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
feat(plat/nxp/common): define default PSCI features if not defined
feat(plat/nxp/common): define common macro for ARM registers
feat(plat/nxp/common): add CCI and EPU address definition

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errata: workaround for Cortex-A710 erratum 2083908

Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.

S

errata: workaround for Cortex-A710 erratum 2083908

Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I876d26a7ac6ab0d7c567a9ec9f34fc0f952589d8

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Merge "refactor(spmd): boot interface and pass core id" into integration

feat(docs/nxp/layerscape): add ls1028a soc and board support

Update nxp-layerscape to add ls1028a SoC and ls1028ardb board
support.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I9c7cc5

feat(docs/nxp/layerscape): add ls1028a soc and board support

Update nxp-layerscape to add ls1028a SoC and ls1028ardb board
support.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I9c7cc586f3718b488a6757994d65f6df69e7e165

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docs(maintainers): update qti maintainer

Add lachit and Sreevyshanavi in qti maintainer

Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I48d2378551775a3ad63bc7c3a4e2b62b15c4770d

feat(plat/qti/sc7280): support for qti sc7280 plat

new qti platform sc7280 support addition

Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f216

feat(plat/qti/sc7280): support for qti sc7280 plat

new qti platform sc7280 support addition

Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f21656c1

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Merge changes from topic "TrcDbgExt" into integration

* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS E

Merge changes from topic "TrcDbgExt" into integration

* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS EL
feat(trf): initialize trap settings of trace filter control registers access
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
feat(sys_reg_trace): initialize trap settings of trace system registers access
feat(trbe): enable access to trace buffer control registers from lower NS EL
feat(trbe): initialize trap settings of trace buffer control registers access

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Merge "refactor(tc): use internal trusted storage" into integration

refactor(tc): use internal trusted storage

Trusted Services had removed secure storage and added two new
trusted services - Protected Storage and Internal Trusted Storage.
Hence we are removing secu

refactor(tc): use internal trusted storage

Trusted Services had removed secure storage and added two new
trusted services - Protected Storage and Internal Trusted Storage.
Hence we are removing secure storage and adding support for the
internal trusted storage.

And enable external SP images in BL2 config for TC, so that
we do not have to modify this file whenever the list of SPs
changes. It is already implemented for fvp in the below commit.

commit 33993a3737737a03ee5a9d386d0a027bdc947c9c
Author: Balint Dobszay <balint.dobszay@arm.com>
Date: Fri Mar 26 15:19:11 2021 +0100

feat(fvp): enable external SP images in BL2 config

Change-Id: I3e0a0973df3644413ca5c3a32f36d44c8efd49c7
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>

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Merge "docs(ff-a): fix specification naming" into integration

Merge "docs(ff-a): managed exit parameter separation" into integration

Merge "fix(docs-contributing.rst): fix formatting for code snippet" into integration

Merge "docs(stm32mp1): update doc for FIP/FCONF" into integration

refactor(spmd): boot interface and pass core id

This change refactors the SPMD to setup SPMC CPU contexts once and early
from spmd_spmc_init (single call to cm_setup_context rather than on each
and

refactor(spmd): boot interface and pass core id

This change refactors the SPMD to setup SPMC CPU contexts once and early
from spmd_spmc_init (single call to cm_setup_context rather than on each
and every warm boot).
Pass the core linear ID through a GP register as an implementation
defined behavior helping FF-A adoption to legacy TOSes (essentially
when secure virtualization is not used).

A first version of this change was originally submitted by Lukas [1].
Pasting below the original justification:

Our TEE, Kinibi, is used to receive the core linear ID in the x3
register of booting secondary cores.
This patch is necessary to bring up secondary cores with Kinibi as an
SPMC in SEL1.

In Kinibi, the TEE is mostly platform-independent and all platform-
specifics like topology is concentrated in TF-A of our customers.
That is why we don't have the MPIDR - linear ID mapping in Kinibi.
We need the correct linear ID to program the GICv2 target register,
for example in power management case.
It is not needed on GICv3/v4, because of using a fixed mapping from
MPIDR to ICDIPTR/GICD_ITARGETSRn register.

For debug and power management purpose, we also want a unified view to
linear id between Linux and the TEE.
E.g. to disable a core, to see what cores are printing a trace /
an event.

In the past, Kinibi had several other designs, but the complexity was
getting out of control:
* Platform-specific assembler macros in the kernel.
* A per-core SMC from Linux to tell the linear ID after the boot.
* With DynamiQ, it seems SIPs were playing with MPIDR register values,
reusing them between cores and changing them during boot.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/10235

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Lukas Hanel <lukas.hanel@trustonic.com>
Change-Id: Ifa8fa208e9b8eb1642c80b5f7b54152dadafa75e

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fix(docs-contributing.rst): fix formatting for code snippet

This patch will fix the formatting errors concerning code snippet,
lines 245 and 256 respectively.
The code snippet is updated to 'shell'

fix(docs-contributing.rst): fix formatting for code snippet

This patch will fix the formatting errors concerning code snippet,
lines 245 and 256 respectively.
The code snippet is updated to 'shell' to lex it appropriately.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I53aefd81da350b6511e7a97b5fee7b0d6f9dde2d

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docs(stm32mp1): update doc for FIP/FCONF

Describe the boot using FIP, and how to compile it.
The STM32IMAGE boot chain is still available but it is not recommended.
Update the build command lines, f

docs(stm32mp1): update doc for FIP/FCONF

Describe the boot using FIP, and how to compile it.
The STM32IMAGE boot chain is still available but it is not recommended.
Update the build command lines, for FIP.
The memory mapping is also updated.

Change-Id: I2b1e0df5500b6213d33dc558b0e0da38340a4d79
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge "docs(contribution-guidelines): add coverity build configuration section" into integration

Merge changes from topic "advk-serror" into integration

* changes:
fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default
fix(plat/marvell/a3k): update information about PCIe abort hack

docs(contribution-guidelines): add coverity build configuration section

Added a sub-section in the "Processes and Policies" chapter under
Contributor's guide on how to add new build configurations w

docs(contribution-guidelines): add coverity build configuration section

Added a sub-section in the "Processes and Policies" chapter under
Contributor's guide on how to add new build configurations when new
source files are added to the TF-A repository. This will help the patch
contributor to update their files to get analysed by Coverity Scan.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I71f410a061028f89bd0e984e48e61e5935616d71

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Merge "docs: nxp soc-lx2160a based platforms" into integration

Merge "feat(gic600ae): introduce support for Fault Management Unit" into integration

docs(ff-a): fix specification naming

Rename the FF-A specification to:
Arm Firmware Framework for Arm A-profile

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4f9d29409d048e7a49

docs(ff-a): fix specification naming

Rename the FF-A specification to:
Arm Firmware Framework for Arm A-profile

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4f9d29409d048e7a49832b95d39d2583c1fb5792

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Merge "feat(fvp): enable external SP images in BL2 config" into integration

Merge changes from topic "erratas" into integration

* changes:
errata: workaround for Neoverse N2 erratum 2138956
errata: workaround for Neoverse N2 erratum 2189731
errata: workaround for Cort

Merge changes from topic "erratas" into integration

* changes:
errata: workaround for Neoverse N2 erratum 2138956
errata: workaround for Neoverse N2 erratum 2189731
errata: workaround for Cortex-A710 erratum 2017096
errata: workaround for Cortex-A710 erratum 2055002

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errata: workaround for Neoverse N2 erratum 2138956

Neoverse N2 erratum 2138956 is a Cat B erratum that applies to
revision r0p0 and is still open. This erratum can be avoided by
inserting a sequence

errata: workaround for Neoverse N2 erratum 2138956

Neoverse N2 erratum 2138956 is a Cat B erratum that applies to
revision r0p0 and is still open. This erratum can be avoided by
inserting a sequence of 16 DMB ST instructions prior to WFI or WFE.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I1aac87b3075992f875451e4767b21857f596d0b2

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