1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/bsec.h> 18 #include <drivers/st/regulator_fixed.h> 19 #include <drivers/st/stm32_iwdg.h> 20 #include <drivers/st/stm32_uart.h> 21 #include <drivers/st/stm32mp1_clk.h> 22 #include <drivers/st/stm32mp1_pwr.h> 23 #include <drivers/st/stm32mp1_ram.h> 24 #include <drivers/st/stm32mp_pmic.h> 25 #include <lib/fconf/fconf.h> 26 #include <lib/fconf/fconf_dyn_cfg_getter.h> 27 #include <lib/mmio.h> 28 #include <lib/optee_utils.h> 29 #include <lib/xlat_tables/xlat_tables_v2.h> 30 #include <plat/common/platform.h> 31 32 #include <platform_def.h> 33 #include <stm32mp_common.h> 34 #include <stm32mp1_dbgmcu.h> 35 36 static struct stm32mp_auth_ops stm32mp1_auth_ops; 37 38 static void print_reset_reason(void) 39 { 40 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 41 42 if (rstsr == 0U) { 43 WARN("Reset reason unknown\n"); 44 return; 45 } 46 47 INFO("Reset reason (0x%x):\n", rstsr); 48 49 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 50 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 51 INFO("System exits from STANDBY\n"); 52 return; 53 } 54 55 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 56 INFO("MPU exits from CSTANDBY\n"); 57 return; 58 } 59 } 60 61 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 62 INFO(" Power-on Reset (rst_por)\n"); 63 return; 64 } 65 66 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 67 INFO(" Brownout Reset (rst_bor)\n"); 68 return; 69 } 70 71 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 72 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 73 INFO(" System reset generated by MCU (MCSYSRST)\n"); 74 } else { 75 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 76 } 77 return; 78 } 79 80 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 81 INFO(" System reset generated by MPU (MPSYSRST)\n"); 82 return; 83 } 84 85 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 86 INFO(" Reset due to a clock failure on HSE\n"); 87 return; 88 } 89 90 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 91 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 92 return; 93 } 94 95 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 96 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 97 return; 98 } 99 100 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 101 INFO(" MPU Processor 0 Reset\n"); 102 return; 103 } 104 105 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 106 INFO(" MPU Processor 1 Reset\n"); 107 return; 108 } 109 110 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 111 INFO(" Pad Reset from NRST\n"); 112 return; 113 } 114 115 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 116 INFO(" Reset due to a failure of VDD_CORE\n"); 117 return; 118 } 119 120 ERROR(" Unidentified reset reason\n"); 121 } 122 123 void bl2_el3_early_platform_setup(u_register_t arg0, 124 u_register_t arg1 __unused, 125 u_register_t arg2 __unused, 126 u_register_t arg3 __unused) 127 { 128 stm32mp_save_boot_ctx_address(arg0); 129 } 130 131 void bl2_platform_setup(void) 132 { 133 int ret; 134 135 ret = stm32mp1_ddr_probe(); 136 if (ret < 0) { 137 ERROR("Invalid DDR init: error %d\n", ret); 138 panic(); 139 } 140 141 /* Map DDR for binary load, now with cacheable attribute */ 142 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 143 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 144 if (ret < 0) { 145 ERROR("DDR mapping: error %d\n", ret); 146 panic(); 147 } 148 149 #if STM32MP_USE_STM32IMAGE 150 #ifdef AARCH32_SP_OPTEE 151 INFO("BL2 runs OP-TEE setup\n"); 152 #else 153 INFO("BL2 runs SP_MIN setup\n"); 154 #endif 155 #endif /* STM32MP_USE_STM32IMAGE */ 156 } 157 158 void bl2_el3_plat_arch_setup(void) 159 { 160 const char *board_model; 161 boot_api_context_t *boot_context = 162 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 163 uintptr_t pwr_base; 164 uintptr_t rcc_base; 165 166 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 167 BL_CODE_END - BL_CODE_BASE, 168 MT_CODE | MT_SECURE); 169 170 #if STM32MP_USE_STM32IMAGE 171 #ifdef AARCH32_SP_OPTEE 172 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 173 STM32MP_OPTEE_SIZE, 174 MT_MEMORY | MT_RW | MT_SECURE); 175 #else 176 /* Prevent corruption of preloaded BL32 */ 177 mmap_add_region(BL32_BASE, BL32_BASE, 178 BL32_LIMIT - BL32_BASE, 179 MT_RO_DATA | MT_SECURE); 180 #endif 181 #endif /* STM32MP_USE_STM32IMAGE */ 182 183 /* Prevent corruption of preloaded Device Tree */ 184 mmap_add_region(DTB_BASE, DTB_BASE, 185 DTB_LIMIT - DTB_BASE, 186 MT_RO_DATA | MT_SECURE); 187 188 configure_mmu(); 189 190 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 191 panic(); 192 } 193 194 pwr_base = stm32mp_pwr_base(); 195 rcc_base = stm32mp_rcc_base(); 196 197 /* 198 * Disable the backup domain write protection. 199 * The protection is enable at each reset by hardware 200 * and must be disabled by software. 201 */ 202 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 203 204 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 205 ; 206 } 207 208 if (bsec_probe() != 0) { 209 panic(); 210 } 211 212 /* Reset backup domain on cold boot cases */ 213 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 214 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 215 216 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 217 0U) { 218 ; 219 } 220 221 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 222 } 223 224 /* Disable MCKPROT */ 225 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 226 227 /* 228 * Set minimum reset pulse duration to 31ms for discrete power 229 * supplied boards. 230 */ 231 if (dt_pmic_status() <= 0) { 232 mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, 233 RCC_RDLSICR_MRD_MASK, 234 31U << RCC_RDLSICR_MRD_SHIFT); 235 } 236 237 generic_delay_timer_init(); 238 239 #if STM32MP_UART_PROGRAMMER 240 /* Disable programmer UART before changing clock tree */ 241 if (boot_context->boot_interface_selected == 242 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) { 243 uintptr_t uart_prog_addr = 244 get_uart_address(boot_context->boot_interface_instance); 245 246 stm32_uart_stop(uart_prog_addr); 247 } 248 #endif 249 if (stm32mp1_clk_probe() < 0) { 250 panic(); 251 } 252 253 if (stm32mp1_clk_init() < 0) { 254 panic(); 255 } 256 257 stm32_save_boot_interface(boot_context->boot_interface_selected, 258 boot_context->boot_interface_instance); 259 260 #if STM32MP_USB_PROGRAMMER 261 /* Deconfigure all UART RX pins configured by ROM code */ 262 stm32mp1_deconfigure_uart_pins(); 263 #endif 264 265 if (stm32mp_uart_console_setup() != 0) { 266 goto skip_console_init; 267 } 268 269 stm32mp_print_cpuinfo(); 270 271 board_model = dt_get_board_model(); 272 if (board_model != NULL) { 273 NOTICE("Model: %s\n", board_model); 274 } 275 276 stm32mp_print_boardinfo(); 277 278 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 279 NOTICE("Bootrom authentication %s\n", 280 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 281 "failed" : "succeeded"); 282 } 283 284 skip_console_init: 285 if (fixed_regulator_register() != 0) { 286 panic(); 287 } 288 289 if (dt_pmic_status() > 0) { 290 initialize_pmic(); 291 print_pmic_info_and_debug(); 292 } 293 294 stm32mp1_syscfg_init(); 295 296 if (stm32_iwdg_init() < 0) { 297 panic(); 298 } 299 300 stm32_iwdg_refresh(); 301 302 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; 303 stm32mp1_auth_ops.verify_signature = 304 boot_context->bootrom_ecdsa_verify_signature; 305 306 stm32mp_init_auth(&stm32mp1_auth_ops); 307 308 stm32mp1_arch_security_setup(); 309 310 print_reset_reason(); 311 312 stm32mp1_syscfg_enable_io_compensation_finish(); 313 314 #if !STM32MP_USE_STM32IMAGE 315 fconf_populate("TB_FW", STM32MP_DTB_BASE); 316 #endif /* !STM32MP_USE_STM32IMAGE */ 317 318 stm32mp_io_setup(); 319 } 320 321 /******************************************************************************* 322 * This function can be used by the platforms to update/use image 323 * information for given `image_id`. 324 ******************************************************************************/ 325 int bl2_plat_handle_post_image_load(unsigned int image_id) 326 { 327 int err = 0; 328 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 329 bl_mem_params_node_t *bl32_mem_params; 330 bl_mem_params_node_t *pager_mem_params __unused; 331 bl_mem_params_node_t *paged_mem_params __unused; 332 #if !STM32MP_USE_STM32IMAGE 333 const struct dyn_cfg_dtb_info_t *config_info; 334 bl_mem_params_node_t *tos_fw_mem_params; 335 unsigned int i; 336 unsigned int idx; 337 unsigned long long ddr_top __unused; 338 const unsigned int image_ids[] = { 339 BL32_IMAGE_ID, 340 BL33_IMAGE_ID, 341 HW_CONFIG_ID, 342 TOS_FW_CONFIG_ID, 343 }; 344 #endif /* !STM32MP_USE_STM32IMAGE */ 345 346 assert(bl_mem_params != NULL); 347 348 switch (image_id) { 349 #if !STM32MP_USE_STM32IMAGE 350 case FW_CONFIG_ID: 351 /* Set global DTB info for fixed fw_config information */ 352 set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID); 353 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 354 355 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID); 356 357 /* Iterate through all the fw config IDs */ 358 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 359 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) { 360 continue; 361 } 362 363 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 364 assert(bl_mem_params != NULL); 365 366 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 367 if (config_info == NULL) { 368 continue; 369 } 370 371 bl_mem_params->image_info.image_base = config_info->config_addr; 372 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 373 374 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 375 376 switch (image_ids[i]) { 377 case BL32_IMAGE_ID: 378 bl_mem_params->ep_info.pc = config_info->config_addr; 379 380 /* In case of OPTEE, initialize address space with tos_fw addr */ 381 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 382 pager_mem_params->image_info.image_base = config_info->config_addr; 383 pager_mem_params->image_info.image_max_size = 384 config_info->config_max_size; 385 386 /* Init base and size for pager if exist */ 387 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 388 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 389 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 390 STM32MP_DDR_SHMEM_SIZE); 391 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 392 break; 393 394 case BL33_IMAGE_ID: 395 bl_mem_params->ep_info.pc = config_info->config_addr; 396 break; 397 398 case HW_CONFIG_ID: 399 case TOS_FW_CONFIG_ID: 400 break; 401 402 default: 403 return -EINVAL; 404 } 405 } 406 break; 407 #endif /* !STM32MP_USE_STM32IMAGE */ 408 409 case BL32_IMAGE_ID: 410 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { 411 /* BL32 is OP-TEE header */ 412 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 413 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 414 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 415 assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); 416 417 #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) 418 /* Set OP-TEE extra image load areas at run-time */ 419 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 420 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; 421 422 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 423 dt_get_ddr_size() - 424 STM32MP_DDR_S_SIZE - 425 STM32MP_DDR_SHMEM_SIZE; 426 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 427 #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ 428 429 err = parse_optee_header(&bl_mem_params->ep_info, 430 &pager_mem_params->image_info, 431 &paged_mem_params->image_info); 432 if (err) { 433 ERROR("OPTEE header parse error.\n"); 434 panic(); 435 } 436 437 /* Set optee boot info from parsed header data */ 438 bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; 439 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 440 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 441 } else { 442 #if !STM32MP_USE_STM32IMAGE 443 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 444 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); 445 bl_mem_params->image_info.image_max_size += 446 tos_fw_mem_params->image_info.image_max_size; 447 #endif /* !STM32MP_USE_STM32IMAGE */ 448 bl_mem_params->ep_info.args.arg0 = 0; 449 } 450 break; 451 452 case BL33_IMAGE_ID: 453 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 454 assert(bl32_mem_params != NULL); 455 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 456 #if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT 457 stm32mp1_fwu_set_boot_idx(); 458 #endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ 459 break; 460 461 default: 462 /* Do nothing in default case */ 463 break; 464 } 465 466 #if STM32MP_SDMMC || STM32MP_EMMC 467 /* 468 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 469 * We take the worst case which is 2 MMC blocks. 470 */ 471 if ((image_id != FW_CONFIG_ID) && 472 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 473 inv_dcache_range(bl_mem_params->image_info.image_base + 474 bl_mem_params->image_info.image_size, 475 2U * MMC_BLOCK_SIZE); 476 } 477 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 478 479 return err; 480 } 481 482 void bl2_el3_plat_prepare_exit(void) 483 { 484 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 485 486 switch (boot_itf) { 487 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 488 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 489 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 490 /* Invalidate the downloaded buffer used with io_memmap */ 491 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 492 break; 493 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 494 default: 495 /* Do nothing in default case */ 496 break; 497 } 498 499 stm32mp1_security_setup(); 500 } 501