1/* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* -------------------------------------------------- 25 * Errata Workaround for Cortex X2 Errata #2002765. 26 * This applies to revisions r0p0, r1p0, and r2p0 and 27 * is open. 28 * x0: variant[4:7] and revision[0:3] of current cpu. 29 * Shall clobber: x0, x1, x17 30 * -------------------------------------------------- 31 */ 32func errata_cortex_x2_2002765_wa 33 /* Check workaround compatibility. */ 34 mov x17, x30 35 bl check_errata_2002765 36 cbz x0, 1f 37 38 ldr x0, =0x6 39 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 40 ldr x0, =0xF3A08002 41 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 42 ldr x0, =0xFFF0F7FE 43 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 44 ldr x0, =0x40000001003ff 45 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 46 isb 47 481: 49 ret x17 50endfunc errata_cortex_x2_2002765_wa 51 52func check_errata_2002765 53 /* Applies to r0p0 - r2p0 */ 54 mov x1, #0x20 55 b cpu_rev_var_ls 56endfunc check_errata_2002765 57 58 /* -------------------------------------------------- 59 * Errata Workaround for Cortex X2 Errata #2058056. 60 * This applies to revisions r0p0, r1p0, and r2p0 and 61 * is open. 62 * x0: variant[4:7] and revision[0:3] of current cpu. 63 * Shall clobber: x0, x1, x17 64 * -------------------------------------------------- 65 */ 66func errata_cortex_x2_2058056_wa 67 /* Check workaround compatibility. */ 68 mov x17, x30 69 bl check_errata_2058056 70 cbz x0, 1f 71 72 mrs x1, CORTEX_X2_CPUECTLR2_EL1 73 mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV 74 bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH 75 msr CORTEX_X2_CPUECTLR2_EL1, x1 76 771: 78 ret x17 79endfunc errata_cortex_x2_2058056_wa 80 81func check_errata_2058056 82 /* Applies to r0p0 - r2p0 */ 83 mov x1, #0x20 84 b cpu_rev_var_ls 85endfunc check_errata_2058056 86 87 /* -------------------------------------------------- 88 * Errata Workaround for Cortex X2 Errata #2083908. 89 * This applies to revision r2p0 and is open. 90 * x0: variant[4:7] and revision[0:3] of current cpu. 91 * Shall clobber: x0-x2, x17 92 * -------------------------------------------------- 93 */ 94func errata_cortex_x2_2083908_wa 95 /* Check workaround compatibility. */ 96 mov x17, x30 97 bl check_errata_2083908 98 cbz x0, 1f 99 100 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 101 mrs x1, CORTEX_X2_CPUACTLR5_EL1 102 orr x1, x1, #BIT(13) 103 msr CORTEX_X2_CPUACTLR5_EL1, x1 104 1051: 106 ret x17 107endfunc errata_cortex_x2_2083908_wa 108 109func check_errata_2083908 110 /* Applies to r2p0 */ 111 mov x1, #0x20 112 mov x2, #0x20 113 b cpu_rev_var_range 114endfunc check_errata_2083908 115 116 /* -------------------------------------------------- 117 * Errata Workaround for Cortex-X2 Errata 2017096. 118 * This applies only to revisions r0p0, r1p0 and r2p0 119 * and is fixed in r2p1. 120 * Inputs: 121 * x0: variant[4:7] and revision[0:3] of current cpu. 122 * Shall clobber: x0, x1, x17 123 * -------------------------------------------------- 124 */ 125func errata_x2_2017096_wa 126 /* Compare x0 against revision r0p0 to r2p0 */ 127 mov x17, x30 128 bl check_errata_2017096 129 cbz x0, 1f 130 mrs x1, CORTEX_X2_CPUECTLR_EL1 131 orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 132 msr CORTEX_X2_CPUECTLR_EL1, x1 133 1341: 135 ret x17 136endfunc errata_x2_2017096_wa 137 138func check_errata_2017096 139 /* Applies to r0p0, r1p0, r2p0 */ 140 mov x1, #0x20 141 b cpu_rev_var_ls 142endfunc check_errata_2017096 143 144 /* -------------------------------------------------- 145 * Errata Workaround for Cortex-X2 Errata 2081180. 146 * This applies to revision r0p0, r1p0 and r2p0 147 * and is fixed in r2p1. 148 * Inputs: 149 * x0: variant[4:7] and revision[0:3] of current cpu. 150 * Shall clobber: x0, x1, x17 151 * -------------------------------------------------- 152 */ 153func errata_x2_2081180_wa 154 /* Check revision. */ 155 mov x17, x30 156 bl check_errata_2081180 157 cbz x0, 1f 158 159 /* Apply instruction patching sequence */ 160 ldr x0, =0x3 161 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 162 ldr x0, =0xF3A08002 163 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 164 ldr x0, =0xFFF0F7FE 165 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 166 ldr x0, =0x10002001003FF 167 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 168 ldr x0, =0x4 169 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 170 ldr x0, =0xBF200000 171 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 172 ldr x0, =0xFFEF0000 173 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 174 ldr x0, =0x10002001003F3 175 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 176 isb 1771: 178 ret x17 179endfunc errata_x2_2081180_wa 180 181func check_errata_2081180 182 /* Applies to r0p0, r1p0 and r2p0 */ 183 mov x1, #0x20 184 b cpu_rev_var_ls 185endfunc check_errata_2081180 186 187 /* ---------------------------------------------------- 188 * HW will do the cache maintenance while powering down 189 * ---------------------------------------------------- 190 */ 191func cortex_x2_core_pwr_dwn 192 /* --------------------------------------------------- 193 * Enable CPU power down bit in power control register 194 * --------------------------------------------------- 195 */ 196 mrs x0, CORTEX_X2_CPUPWRCTLR_EL1 197 orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 198 msr CORTEX_X2_CPUPWRCTLR_EL1, x0 199 isb 200 ret 201endfunc cortex_x2_core_pwr_dwn 202 203 /* 204 * Errata printing function for Cortex X2. Must follow AAPCS. 205 */ 206#if REPORT_ERRATA 207func cortex_x2_errata_report 208 stp x8, x30, [sp, #-16]! 209 210 bl cpu_get_rev_var 211 mov x8, x0 212 213 /* 214 * Report all errata. The revision-variant information is passed to 215 * checking functions of each errata. 216 */ 217 report_errata ERRATA_X2_2002765, cortex_x2, 2002765 218 report_errata ERRATA_X2_2058056, cortex_x2, 2058056 219 report_errata ERRATA_X2_2083908, cortex_x2, 2083908 220 report_errata ERRATA_X2_2017096, cortex_x2, 2017096 221 report_errata ERRATA_X2_2081180, cortex_x2, 2081180 222 223 ldp x8, x30, [sp], #16 224 ret 225endfunc cortex_x2_errata_report 226#endif 227 228func cortex_x2_reset_func 229 mov x19, x30 230 231 /* Disable speculative loads */ 232 msr SSBS, xzr 233 isb 234 235 /* Get the CPU revision and stash it in x18. */ 236 bl cpu_get_rev_var 237 mov x18, x0 238 239#if ERRATA_X2_2002765 240 mov x0, x18 241 bl errata_cortex_x2_2002765_wa 242#endif 243 244#if ERRATA_X2_2058056 245 mov x0, x18 246 bl errata_cortex_x2_2058056_wa 247#endif 248 249#if ERRATA_X2_2083908 250 mov x0, x18 251 bl errata_cortex_x2_2083908_wa 252#endif 253 254#if ERRATA_X2_2017096 255 mov x0, x18 256 bl errata_x2_2017096_wa 257#endif 258 259#if ERRATA_X2_2081180 260 mov x0, x18 261 bl errata_x2_2081180_wa 262#endif 263 264 ret x19 265endfunc cortex_x2_reset_func 266 267 /* --------------------------------------------- 268 * This function provides Cortex X2 specific 269 * register information for crash reporting. 270 * It needs to return with x6 pointing to 271 * a list of register names in ascii and 272 * x8 - x15 having values of registers to be 273 * reported. 274 * --------------------------------------------- 275 */ 276.section .rodata.cortex_x2_regs, "aS" 277cortex_x2_regs: /* The ascii list of register names to be reported */ 278 .asciz "cpuectlr_el1", "" 279 280func cortex_x2_cpu_reg_dump 281 adr x6, cortex_x2_regs 282 mrs x8, CORTEX_X2_CPUECTLR_EL1 283 ret 284endfunc cortex_x2_cpu_reg_dump 285 286declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 287 cortex_x2_reset_func, \ 288 cortex_x2_core_pwr_dwn 289