1/* 2 * Copyright (c) 2022, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a510.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* -------------------------------------------------- 25 * Errata Workaround for Cortex-A510 Errata #1922240. 26 * This applies only to revision r0p0 (fixed in r0p1) 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0, x1, x17 29 * -------------------------------------------------- 30 */ 31func errata_cortex_a510_1922240_wa 32 /* Check workaround compatibility. */ 33 mov x17, x30 34 bl check_errata_1922240 35 cbz x0, 1f 36 37 /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ 38 mrs x0, CORTEX_A510_CMPXACTLR_EL1 39 mov x1, #3 40 bfi x0, x1, #10, #2 41 msr CORTEX_A510_CMPXACTLR_EL1, x0 42 431: 44 ret x17 45endfunc errata_cortex_a510_1922240_wa 46 47func check_errata_1922240 48 /* Applies to r0p0 only */ 49 mov x1, #0x00 50 b cpu_rev_var_ls 51endfunc check_errata_1922240 52 53 /* -------------------------------------------------- 54 * Errata Workaround for Cortex-A510 Errata #2288014. 55 * This applies only to revisions r0p0, r0p1, r0p2, 56 * r0p3 and r1p0. (fixed in r1p1) 57 * x0: variant[4:7] and revision[0:3] of current cpu. 58 * Shall clobber: x0, x1, x17 59 * -------------------------------------------------- 60 */ 61func errata_cortex_a510_2288014_wa 62 /* Check workaround compatibility. */ 63 mov x17, x30 64 bl check_errata_2288014 65 cbz x0, 1f 66 67 /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ 68 mrs x0, CORTEX_A510_CPUACTLR_EL1 69 mov x1, #1 70 bfi x0, x1, #18, #1 71 msr CORTEX_A510_CPUACTLR_EL1, x0 72 731: 74 ret x17 75endfunc errata_cortex_a510_2288014_wa 76 77func check_errata_2288014 78 /* Applies to r1p0 and below */ 79 mov x1, #0x10 80 b cpu_rev_var_ls 81endfunc check_errata_2288014 82 83 /* -------------------------------------------------- 84 * Errata Workaround for Cortex-A510 Errata #2042739. 85 * This applies only to revisions r0p0, r0p1 and r0p2. 86 * (fixed in r0p3) 87 * x0: variant[4:7] and revision[0:3] of current cpu. 88 * Shall clobber: x0, x1, x17 89 * -------------------------------------------------- 90 */ 91func errata_cortex_a510_2042739_wa 92 /* Check workaround compatibility. */ 93 mov x17, x30 94 bl check_errata_2042739 95 cbz x0, 1f 96 97 /* Apply the workaround by disabling ReadPreferUnique. */ 98 mrs x0, CORTEX_A510_CPUECTLR_EL1 99 mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE 100 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1 101 msr CORTEX_A510_CPUECTLR_EL1, x0 102 1031: 104 ret x17 105endfunc errata_cortex_a510_2042739_wa 106 107func check_errata_2042739 108 /* Applies to revisions r0p0 - r0p2 */ 109 mov x1, #0x02 110 b cpu_rev_var_ls 111endfunc check_errata_2042739 112 113 /* ---------------------------------------------------- 114 * HW will do the cache maintenance while powering down 115 * ---------------------------------------------------- 116 */ 117func cortex_a510_core_pwr_dwn 118 /* --------------------------------------------------- 119 * Enable CPU power down bit in power control register 120 * --------------------------------------------------- 121 */ 122 mrs x0, CORTEX_A510_CPUPWRCTLR_EL1 123 orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 124 msr CORTEX_A510_CPUPWRCTLR_EL1, x0 125 isb 126 ret 127endfunc cortex_a510_core_pwr_dwn 128 129 /* 130 * Errata printing function for Cortex-A510. Must follow AAPCS. 131 */ 132#if REPORT_ERRATA 133func cortex_a510_errata_report 134 stp x8, x30, [sp, #-16]! 135 136 bl cpu_get_rev_var 137 mov x8, x0 138 139 /* 140 * Report all errata. The revision-variant information is passed to 141 * checking functions of each errata. 142 */ 143 report_errata ERRATA_A510_1922240, cortex_a510, 1922240 144 report_errata ERRATA_A510_2288014, cortex_a510, 2288014 145 report_errata ERRATA_A510_2042739, cortex_a510, 2042739 146 147 ldp x8, x30, [sp], #16 148 ret 149endfunc cortex_a510_errata_report 150#endif 151 152func cortex_a510_reset_func 153 mov x19, x30 154 155 /* Disable speculative loads */ 156 msr SSBS, xzr 157 isb 158 159 /* Get the CPU revision and stash it in x18. */ 160 bl cpu_get_rev_var 161 mov x18, x0 162 163#if ERRATA_A510_1922240 164 mov x0, x18 165 bl errata_cortex_a510_1922240_wa 166#endif 167 168#if ERRATA_A510_2288014 169 mov x0, x18 170 bl errata_cortex_a510_2288014_wa 171#endif 172 173#if ERRATA_A510_2042739 174 mov x0, x18 175 bl errata_cortex_a510_2042739_wa 176#endif 177 178 ret x19 179endfunc cortex_a510_reset_func 180 181 /* --------------------------------------------- 182 * This function provides Cortex-A510 specific 183 * register information for crash reporting. 184 * It needs to return with x6 pointing to 185 * a list of register names in ascii and 186 * x8 - x15 having values of registers to be 187 * reported. 188 * --------------------------------------------- 189 */ 190.section .rodata.cortex_a510_regs, "aS" 191cortex_a510_regs: /* The ascii list of register names to be reported */ 192 .asciz "cpuectlr_el1", "" 193 194func cortex_a510_cpu_reg_dump 195 adr x6, cortex_a510_regs 196 mrs x8, CORTEX_A510_CPUECTLR_EL1 197 ret 198endfunc cortex_a510_cpu_reg_dump 199 200declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \ 201 cortex_a510_reset_func, \ 202 cortex_a510_core_pwr_dwn 203