1/* 2 * Copyright (c) 2022, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a510.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* -------------------------------------------------- 25 * Errata Workaround for Cortex-A510 Errata #1922240. 26 * This applies only to revision r0p0 (fixed in r0p1) 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0, x1, x17 29 * -------------------------------------------------- 30 */ 31func errata_cortex_a510_1922240_wa 32 /* Check workaround compatibility. */ 33 mov x17, x30 34 bl check_errata_1922240 35 cbz x0, 1f 36 37 /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ 38 mrs x0, CORTEX_A510_CMPXACTLR_EL1 39 mov x1, #3 40 bfi x0, x1, #10, #2 41 msr CORTEX_A510_CMPXACTLR_EL1, x0 42 431: 44 ret x17 45endfunc errata_cortex_a510_1922240_wa 46 47func check_errata_1922240 48 /* Applies to r0p0 only */ 49 mov x1, #0x00 50 b cpu_rev_var_ls 51endfunc check_errata_1922240 52 53 /* -------------------------------------------------- 54 * Errata Workaround for Cortex-A510 Errata #2288014. 55 * This applies only to revisions r0p0, r0p1, r0p2, 56 * r0p3 and r1p0. (fixed in r1p1) 57 * x0: variant[4:7] and revision[0:3] of current cpu. 58 * Shall clobber: x0, x1, x17 59 * -------------------------------------------------- 60 */ 61func errata_cortex_a510_2288014_wa 62 /* Check workaround compatibility. */ 63 mov x17, x30 64 bl check_errata_2288014 65 cbz x0, 1f 66 67 /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ 68 mrs x0, CORTEX_A510_CPUACTLR_EL1 69 mov x1, #1 70 bfi x0, x1, #18, #1 71 msr CORTEX_A510_CPUACTLR_EL1, x0 72 731: 74 ret x17 75endfunc errata_cortex_a510_2288014_wa 76 77func check_errata_2288014 78 /* Applies to r1p0 and below */ 79 mov x1, #0x10 80 b cpu_rev_var_ls 81endfunc check_errata_2288014 82 83 /* ---------------------------------------------------- 84 * HW will do the cache maintenance while powering down 85 * ---------------------------------------------------- 86 */ 87func cortex_a510_core_pwr_dwn 88 /* --------------------------------------------------- 89 * Enable CPU power down bit in power control register 90 * --------------------------------------------------- 91 */ 92 mrs x0, CORTEX_A510_CPUPWRCTLR_EL1 93 orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 94 msr CORTEX_A510_CPUPWRCTLR_EL1, x0 95 isb 96 ret 97endfunc cortex_a510_core_pwr_dwn 98 99 /* 100 * Errata printing function for Cortex-A510. Must follow AAPCS. 101 */ 102#if REPORT_ERRATA 103func cortex_a510_errata_report 104 stp x8, x30, [sp, #-16]! 105 106 bl cpu_get_rev_var 107 mov x8, x0 108 109 /* 110 * Report all errata. The revision-variant information is passed to 111 * checking functions of each errata. 112 */ 113 report_errata ERRATA_A510_1922240, cortex_a510, 1922240 114 report_errata ERRATA_A510_2288014, cortex_a510, 2288014 115 116 ldp x8, x30, [sp], #16 117 ret 118endfunc cortex_a510_errata_report 119#endif 120 121func cortex_a510_reset_func 122 mov x19, x30 123 124 /* Disable speculative loads */ 125 msr SSBS, xzr 126 isb 127 128 /* Get the CPU revision and stash it in x18. */ 129 bl cpu_get_rev_var 130 mov x18, x0 131 132#if ERRATA_A510_1922240 133 mov x0, x18 134 bl errata_cortex_a510_1922240_wa 135#endif 136 137#if ERRATA_A510_2288014 138 mov x0, x18 139 bl errata_cortex_a510_2288014_wa 140#endif 141 142 ret x19 143endfunc cortex_a510_reset_func 144 145 /* --------------------------------------------- 146 * This function provides Cortex-A510 specific 147 * register information for crash reporting. 148 * It needs to return with x6 pointing to 149 * a list of register names in ascii and 150 * x8 - x15 having values of registers to be 151 * reported. 152 * --------------------------------------------- 153 */ 154.section .rodata.cortex_a510_regs, "aS" 155cortex_a510_regs: /* The ascii list of register names to be reported */ 156 .asciz "cpuectlr_el1", "" 157 158func cortex_a510_cpu_reg_dump 159 adr x6, cortex_a510_regs 160 mrs x8, CORTEX_A510_CPUECTLR_EL1 161 ret 162endfunc cortex_a510_cpu_reg_dump 163 164declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \ 165 cortex_a510_reset_func, \ 166 cortex_a510_core_pwr_dwn 167