docs(fvp): update FVP versions used

Patch series:
https://review.trustedfirmware.org/q/hashtag:%22fvp_migration_11_26%22+(status:open%20OR%20status:merged)

Migrated FVP's to use version 11.26.11 an

docs(fvp): update FVP versions used

Patch series:
https://review.trustedfirmware.org/q/hashtag:%22fvp_migration_11_26%22+(status:open%20OR%20status:merged)

Migrated FVP's to use version 11.26.11 and 11.24.24, also removed
some model testing that are now no more available with newer model
configuration.

Change-Id: Ib93a7148270e2b6fb356a631dcc36061c7c8341c
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "feat(versal2): add support for AMD Versal Gen 2 platform" into integration

docs: update Cortex-A32 FVP model version

Change [1] migrated Cortex-A32 FVP model to the default version used in
the TF-A CI.

[1] https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/29297

S

docs: update Cortex-A32 FVP model version

Change [1] migrated Cortex-A32 FVP model to the default version used in
the TF-A CI.

[1] https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/29297

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I038087af957d3ee2b289944b4af1a8cffb1ec5ff

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feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM

feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM
firmware which loads TF-A(bl31) to memory, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(rockchip): add RK3566/RK3568 Socs support

RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. su

feat(rockchip): add RK3566/RK3568 Socs support

RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I8b98a4d07664de26bd6078f63664cbc3d9c1c68c

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Merge changes from topic "early_console" into integration

* changes:
feat(stm32mp2): use early traces
feat(st-bsec): use early traces
refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CON

Merge changes from topic "early_console" into integration

* changes:
feat(stm32mp2): use early traces
feat(st-bsec): use early traces
refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CONSOLE
feat(console): introduce EARLY_CONSOLE
feat(bl32): create an sp_min_setup function

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Merge changes from topic "add_s32g274ardb2_support" into integration

* changes:
feat(s32g274a): enable BL31 stage
feat(s32g274a): add S32G274ARDB2 board support
feat(nxp-drivers): add Linflex

Merge changes from topic "add_s32g274ardb2_support" into integration

* changes:
feat(s32g274a): enable BL31 stage
feat(s32g274a): add S32G274ARDB2 board support
feat(nxp-drivers): add Linflex driver

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Merge "docs(fvp): restructure FVP platform documentation" into integration

feat(s32g274a): add S32G274ARDB2 board support

S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, a

feat(s32g274a): add S32G274ARDB2 board support

S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, accelerators for automotive networking and many other
peripherals.

The added support is minimal and only includes the BL2 stage, with no
MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies
BL31 and BL33 from FIP to their designated addresses.

Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(rdn1edge): remove RD-N1-Edge from deprecated list

As RD-N1-Edge is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.

Change-Id: I6af06e7bd162747a

feat(rdn1edge): remove RD-N1-Edge from deprecated list

As RD-N1-Edge is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.

Change-Id: I6af06e7bd162747aab72384185951d218b388ed3
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>

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feat(sgi575): remove SGI-575 from deprecated list

As SGI-575 is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.

Change-Id: Ic9171a3e1bec198d9305e75a

feat(sgi575): remove SGI-575 from deprecated list

As SGI-575 is not planned to be deprecated in the upcoming release
cycles, remove it from the deprecated list.

Change-Id: Ic9171a3e1bec198d9305e75ac5cae4b40498537e
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>

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refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CONSOLE

Now that EARLY_CONSOLE is generic, use it instead of the ST flag.
Remove stm32mp_setup_early_console() calls as it is done in common TF

refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CONSOLE

Now that EARLY_CONSOLE is generic, use it instead of the ST flag.
Remove stm32mp_setup_early_console() calls as it is done in common TF-A
code.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Icac29b62a6267303cb5c679d15847c013ead1d23

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docs(fvp): restructure FVP platform documentation

The Arm FVP documentation has grown organically over the years. As a
result, it has become a big document, which can be difficult to digest.

Also,

docs(fvp): restructure FVP platform documentation

The Arm FVP documentation has grown organically over the years. As a
result, it has become a big document, which can be difficult to digest.

Also, the organization of some of the sections does not make sense. In
particular, all "Running on the ... FVP" sections live under a section
named "Booting a preloaded kernel image (Base FVP)". To illustrate this,
here is the current table of contents:

Arm Fixed Virtual Platforms (FVP)
Fixed Virtual Platform (FVP) Support
Arm FVP Platform Specific Build Options
Booting Firmware Update images
Booting an EL3 payload
Booting a preloaded kernel image (Base FVP)
Obtaining the Flattened Device Treesp
Running on the Foundation FVP with reset to BL1 entrypoint
Running on the AEMv8 Base FVP with reset to BL1 entrypoint
Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
Running on the AEMv8 Base FVP with reset to BL31 entrypoint
Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint

This patch breaks down this document in sub-documents, which are now
included from the index file. The table of contents (ToC) reflects the
new documents hierarchy. The depth of the ToC has been reduced to
simplify the index page. Here is what it looks like now:

Arm Fixed Virtual Platforms (FVP)
Fixed Virtual Platform (FVP) Support
Arm FVP Platform Specific Build Options
Running on the Foundation FVP
Running on the AEMv8 Base FVP
Running on the Cortex-A57-A53 Base FVP
Running on the Cortex-A32 Base FVP (AArch32)
Booting Firmware Update images
Booting an EL3 payload
Booting a preloaded kernel image (Base FVP)

Apart from moving information around in separate files, this patch also
makes the following minor changes to the contents:

- Add a brief introduction about FVPs in the index page.
- Change some of the titles names for conciseness.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Icb650e0ec2c7a86ccd6e7eea4e16a84c41442c96

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docs(plat): remove TC1 entry from the deprecation table

Since the TC1 platform has been eliminated from the TF-A source code
and CI script repository, updated the deprecation table to remove its
ent

docs(plat): remove TC1 entry from the deprecation table

Since the TC1 platform has been eliminated from the TF-A source code
and CI script repository, updated the deprecation table to remove its
entry.

Change-Id: I93ae03e1f810666e9a6d0c6172a322ff1e960c71
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "docs: remove entries of the deleted platforms" into integration

Merge changes Id72a0370,I2bafba38,I2bd48441,I164c579c,Iddf8aea0, ... into integration

* changes:
feat(rpi): add Raspberry Pi 5 support
fix(rpi): consider MT when calculating core index from MPID

Merge changes Id72a0370,I2bafba38,I2bd48441,I164c579c,Iddf8aea0, ... into integration

* changes:
feat(rpi): add Raspberry Pi 5 support
fix(rpi): consider MT when calculating core index from MPIDR
refactor(rpi): move register definitions out of rpi_hw.h
refactor(rpi): add platform macro for the crash UART base address
refactor(rpi): split out console registration logic
refactor(rpi): move more platform-specific code into common

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docs(st): set OP-TEE as default BL32

Recommend OP-TEE as the default BL32 for STMicroelectronics platforms.
SP_MIN is no more supported in STMicroelectronics software [1].
It will then no more recei

docs(st): set OP-TEE as default BL32

Recommend OP-TEE as the default BL32 for STMicroelectronics platforms.
SP_MIN is no more supported in STMicroelectronics software [1].
It will then no more receive new features, but should still remain
as it is in the TF-A code.

[1]: https://wiki.st.com/stm32mpu/wiki/STM32_MPU_OpenSTLinux_release_note_-_v5.0.0#TF-A

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic49338dbba3fdcebcb1e477e6a1dbde32783482b

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docs(st): one device flag for ST platforms

Due to embedded SRAM used to load BL2 and BL31 or BL32 has a limited
size, only one storage device or serial device flag should be selected
in TF-A build c

docs(st): one device flag for ST platforms

Due to embedded SRAM used to load BL2 and BL31 or BL32 has a limited
size, only one storage device or serial device flag should be selected
in TF-A build command line for ST platforms.
This is in line with STMicroelectionics recommendation [1] about those
compilation flags.

[1]: https://wiki.st.com/stm32mpu/wiki/How_to_configure_TF-A_BL2#Build_command_details

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6f6ab17d45d00289989a606d15c143e5710c64ce

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docs: remove entries of the deleted platforms

Remove the details of the platforms from the 'deprecated
platforms' table those are already deleted.
This is in-sync with other depreaction tables [1] w

docs: remove entries of the deleted platforms

Remove the details of the platforms from the 'deprecated
platforms' table those are already deleted.
This is in-sync with other depreaction tables [1] which
only has deprecation entries and not deleted entries.

[1]: https://trustedfirmware-a.readthedocs.io/en/latest/about/release-information.html#removal-of-deprecated-interfaces

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: If8c8e4ba4e7fa88ea83632202d17c7d35cdc200a

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feat(rpi): add Raspberry Pi 5 support

The Raspberry Pi 5 is a single-board computer based on BCM2712 that
contains four Arm Cortex-A76 cores.

This change introduces minimal BL31 support with PSCI t

feat(rpi): add Raspberry Pi 5 support

The Raspberry Pi 5 is a single-board computer based on BCM2712 that
contains four Arm Cortex-A76 cores.

This change introduces minimal BL31 support with PSCI that has been
validated to boot Linux and a private EDK2 build.

It's a drop-in replacement for the custom TF-A armstub now included in
the EEPROM images.

Change-Id: Id72a0370f54e71ac97c3daa1bacedacb7dec148f
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

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Merge changes from topic "xlnx_smc_doc" into integration

* changes:
docs(versal-net): update SMC convention
docs(versal): update SMC convention
docs(zynqmp): update SMC convention

Merge changes from topic "sgi_to_nrd" into integration

* changes:
refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd
refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"
refa

Merge changes from topic "sgi_to_nrd" into integration

* changes:
refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd
refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"
refactor(sgi): move apis and types to "nrd" prefix
refactor(sgi): replace build-option prefix to "NRD"
refactor(sgi): move neoverse_rd out of css
refactor(sgi): move from "sgi" to "neoverse_rd"
feat(sgi): remove unused SGI_PLAT build-option
fix(sgi): align to misra rule for braces
feat(rde1edge): remove support for RD-E1-Edge
fix(rdn2): populate TOS_CONFIG only when SPMC_AT_EL3 is enabled
fix(board): update spi_id max for sgi multichip platforms

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docs(imx8ulp): add imx8ulp platform

Add i.MX8ULP platform introduction.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Idc16bcf5b23542f8a1f394a474309239ddcb9685

docs(versal-net): update SMC convention

Updated documentation for SMC SiP calling conventions for IPI,
PM, and SiP Service queries.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id:

docs(versal-net): update SMC convention

Updated documentation for SMC SiP calling conventions for IPI,
PM, and SiP Service queries.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I4bd71dd8e16c7adf3f9c5cb202f36aa2e275d03a

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docs(versal): update SMC convention

Updated documentation for SMC SiP calling conventions for IPI,
PM, and SiP Service queries.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ic2

docs(versal): update SMC convention

Updated documentation for SMC SiP calling conventions for IPI,
PM, and SiP Service queries.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ic232551bb09152124da5226673c88e1a34a384c4

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