1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <plat/common/common_def.h> 11 12 #define PLATFORM_STACK_SIZE U(0x1000) 13 14 /* Caches */ 15 #define CACHE_WRITEBACK_SHIFT U(6) 16 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 17 18 /* CPU Topology */ 19 #define PLATFORM_CORE_COUNT U(4) 20 #define PLATFORM_SYSTEM_COUNT U(1) 21 #define PLATFORM_PRIMARY_CPU U(0) 22 #define PLATFORM_MPIDR_CPU_MASK_BITS U(1) 23 24 /* Power Domains */ 25 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 26 #define PLAT_MAX_OFF_STATE U(2) 27 #define PLAT_MAX_RET_STATE U(1) 28 #define PLAT_MAX_PWR_LVL_STATES U(2) 29 30 /* BL2 stage */ 31 #define BL2_BASE UL(0x34078000) 32 #define BL2_LIMIT UL(0x34100000) 33 34 /* BL31 stage */ 35 #define BL31_BASE UL(0x34200000) 36 #define BL31_LIMIT UL(0x34300000) 37 38 /* It is a dummy value for now, given the missing DDR */ 39 #define BL33_BASE UL(0x34500000) 40 #define BL33_LIMIT UL(0x345FF000) 41 42 /* Console settings */ 43 #define UART_BASE UL(0x401C8000) 44 #define UART_BAUDRATE U(115200) 45 /* FIRC clock */ 46 #define UART_CLOCK_HZ U(48000000) 47 48 #define S32G_FIP_BASE UL(0x34100000) 49 #define S32G_FIP_SIZE UL(0x100000) 50 51 #define MAX_IO_HANDLES U(2) 52 #define MAX_IO_DEVICES U(2) 53 54 #endif /* PLATFORM_DEF_H */ 55