1 /* 2 * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <inttypes.h> 10 11 #include <drivers/scmi-msg.h> 12 #include <drivers/scmi.h> 13 #include <lib/utils_def.h> 14 #include <platform_def.h> 15 #include <scmi.h> 16 17 #include "plat_private.h" 18 19 #define HIGH (1) 20 #define LOW (0) 21 22 struct scmi_clk { 23 unsigned long clock_id; 24 unsigned long rate; 25 const char *name; 26 bool enabled; 27 }; 28 29 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled, _rate) \ 30 [_scmi_id] = { \ 31 .clock_id = (_id), \ 32 .name = (_name), \ 33 .enabled = (_init_enabled), \ 34 .rate = (_rate), \ 35 } 36 37 static struct scmi_clk scmi0_clock[] = { 38 CLOCK_CELL(CLK_GEM0_0, CLK_GEM0_0, "gem0_pclk", true, 100000000), 39 CLOCK_CELL(CLK_GEM0_1, CLK_GEM0_1, "gem0_hclk", true, 100000000), 40 CLOCK_CELL(CLK_GEM0_2, CLK_GEM0_2, "gem0_tx_clk", true, 125000000), 41 CLOCK_CELL(CLK_GEM0_3, CLK_GEM0_3, "gem0_rx_clk", true, 100000000), 42 CLOCK_CELL(CLK_GEM0_4, CLK_GEM0_4, "gem0_tsu_clk", true, 100000000), 43 CLOCK_CELL(CLK_GEM1_0, CLK_GEM1_0, "gem1_pclk", true, 100000000), 44 CLOCK_CELL(CLK_GEM1_1, CLK_GEM1_1, "gem1_hclk", true, 100000000), 45 CLOCK_CELL(CLK_GEM1_2, CLK_GEM1_2, "gem1_tx_clk", true, 125000000), 46 CLOCK_CELL(CLK_GEM1_3, CLK_GEM1_3, "gem1_rx_clk", true, 100000000), 47 CLOCK_CELL(CLK_GEM1_4, CLK_GEM1_4, "gem1_tsu_clk", true, 100000000), 48 CLOCK_CELL(CLK_SERIAL0_0, CLK_SERIAL0_0, "uart0_uartclk", true, 100000000), 49 CLOCK_CELL(CLK_SERIAL0_1, CLK_SERIAL0_1, "uart0_apb_pclk", true, 100000000), 50 CLOCK_CELL(CLK_SERIAL1_0, CLK_SERIAL1_0, "uart1_uartclk", true, 100000000), 51 CLOCK_CELL(CLK_SERIAL1_1, CLK_SERIAL1_1, "uart1_apb_pclk", true, 100000000), 52 CLOCK_CELL(CLK_UFS0_0, CLK_UFS0_0, "ufs_core_clk", true, 100000000), 53 CLOCK_CELL(CLK_UFS0_1, CLK_UFS0_1, "ufs_phy_clk", true, 100000000), 54 CLOCK_CELL(CLK_UFS0_2, CLK_UFS0_2, "ufs_ref_pclk", true, 100000000), 55 CLOCK_CELL(CLK_USB0_0, CLK_USB0_0, "usb0_bus_clk", true, 100000000), 56 CLOCK_CELL(CLK_USB0_1, CLK_USB0_1, "usb0_ref_clk", true, 100000000), 57 CLOCK_CELL(CLK_USB0_2, CLK_USB0_2, "usb0_dwc_clk", true, 100000000), 58 CLOCK_CELL(CLK_USB1_0, CLK_USB1_0, "usb1_bus_clk", true, 100000000), 59 CLOCK_CELL(CLK_USB1_1, CLK_USB1_1, "usb1_ref_clk", true, 100000000), 60 CLOCK_CELL(CLK_USB1_2, CLK_USB1_2, "usb1_dwc_clk", true, 100000000), 61 CLOCK_CELL(CLK_MMC0_0, CLK_MMC0_0, "mmc0_xin_clk", true, 100000000), 62 CLOCK_CELL(CLK_MMC0_1, CLK_MMC0_1, "mmc0_ahb_clk", true, 100000000), 63 CLOCK_CELL(CLK_MMC0_2, CLK_MMC0_2, "mmc0_gate_clk", true, 100000000), 64 CLOCK_CELL(CLK_MMC1_0, CLK_MMC1_0, "mmc1_xin_clk", true, 100000000), 65 CLOCK_CELL(CLK_MMC1_1, CLK_MMC1_1, "mmc1_ahb_clk", true, 100000000), 66 CLOCK_CELL(CLK_MMC1_2, CLK_MMC1_2, "mmc1_gate_clk", true, 100000000), 67 CLOCK_CELL(CLK_TTC0_0, CLK_TTC0_0, "ttc0_clk", true, 100000000), 68 CLOCK_CELL(CLK_TTC1_0, CLK_TTC1_0, "ttc1_clk", true, 100000000), 69 CLOCK_CELL(CLK_TTC2_0, CLK_TTC2_0, "ttc2_clk", true, 100000000), 70 CLOCK_CELL(CLK_TTC3_0, CLK_TTC3_0, "ttc3_clk", true, 100000000), 71 CLOCK_CELL(CLK_TTC4_0, CLK_TTC4_0, "ttc4_clk", true, 100000000), 72 CLOCK_CELL(CLK_TTC5_0, CLK_TTC5_0, "ttc5_clk", true, 100000000), 73 CLOCK_CELL(CLK_TTC6_0, CLK_TTC6_0, "ttc6_clk", true, 100000000), 74 CLOCK_CELL(CLK_TTC7_0, CLK_TTC7_0, "ttc7_clk", true, 100000000), 75 CLOCK_CELL(CLK_I2C0_0, CLK_I2C0_0, "i2c0_clk", true, 100000000), 76 CLOCK_CELL(CLK_I2C1_0, CLK_I2C1_0, "i2c1_clk", true, 100000000), 77 CLOCK_CELL(CLK_I2C2_0, CLK_I2C2_0, "i2c2_clk", true, 100000000), 78 CLOCK_CELL(CLK_I2C3_0, CLK_I2C3_0, "i2c3_clk", true, 100000000), 79 CLOCK_CELL(CLK_I2C4_0, CLK_I2C4_0, "i2c4_clk", true, 100000000), 80 CLOCK_CELL(CLK_I2C5_0, CLK_I2C5_0, "i2c5_clk", true, 100000000), 81 CLOCK_CELL(CLK_I2C6_0, CLK_I2C6_0, "i2c6_clk", true, 100000000), 82 CLOCK_CELL(CLK_I2C7_0, CLK_I2C7_0, "i2c7_clk", true, 100000000), 83 CLOCK_CELL(CLK_OSPI0_0, CLK_OSPI0_0, "ospi0_clk", true, 100000000), 84 CLOCK_CELL(CLK_QSPI0_0, CLK_QSPI0_0, "qpsi0_ref_clk", true, 100000000), 85 CLOCK_CELL(CLK_QSPI0_1, CLK_QSPI0_1, "qspi0_pclk", true, 100000000), 86 CLOCK_CELL(CLK_WWDT0_0, CLK_WWDT0_0, "wwdt0_clk", true, 100000000), 87 CLOCK_CELL(CLK_WWDT1_0, CLK_WWDT1_0, "wwdt1_clk", true, 100000000), 88 CLOCK_CELL(CLK_WWDT2_0, CLK_WWDT2_0, "wwdt2_clk", true, 100000000), 89 CLOCK_CELL(CLK_WWDT3_0, CLK_WWDT3_0, "wwdt3_clk", true, 100000000), 90 CLOCK_CELL(CLK_ADMA0_0, CLK_ADMA0_0, "adma0_main_clk", true, 100000000), 91 CLOCK_CELL(CLK_ADMA0_1, CLK_ADMA0_1, "adma0_apb_clk", true, 100000000), 92 CLOCK_CELL(CLK_ADMA1_0, CLK_ADMA1_0, "adma1_main_clk", true, 100000000), 93 CLOCK_CELL(CLK_ADMA1_1, CLK_ADMA1_1, "adma1_apb_clk", true, 100000000), 94 CLOCK_CELL(CLK_ADMA2_0, CLK_ADMA2_0, "adma2_main_clk", true, 100000000), 95 CLOCK_CELL(CLK_ADMA2_1, CLK_ADMA2_1, "adma2_apb_clk", true, 100000000), 96 CLOCK_CELL(CLK_ADMA3_0, CLK_ADMA3_0, "adma3_main_clk", true, 100000000), 97 CLOCK_CELL(CLK_ADMA3_1, CLK_ADMA3_1, "adma3_apb_clk", true, 100000000), 98 CLOCK_CELL(CLK_ADMA4_0, CLK_ADMA4_0, "adma4_main_clk", true, 100000000), 99 CLOCK_CELL(CLK_ADMA4_1, CLK_ADMA4_1, "adma4_apb_clk", true, 100000000), 100 CLOCK_CELL(CLK_ADMA5_0, CLK_ADMA5_0, "adma5_main_clk", true, 100000000), 101 CLOCK_CELL(CLK_ADMA5_1, CLK_ADMA5_1, "adma5_apb_clk", true, 100000000), 102 CLOCK_CELL(CLK_ADMA6_0, CLK_ADMA6_0, "adma6_main_clk", true, 100000000), 103 CLOCK_CELL(CLK_ADMA6_1, CLK_ADMA6_1, "adma6_apb_clk", true, 100000000), 104 CLOCK_CELL(CLK_ADMA7_0, CLK_ADMA7_0, "adma7_main_clk", true, 100000000), 105 CLOCK_CELL(CLK_ADMA7_1, CLK_ADMA7_1, "adma7_apb_clk", true, 100000000), 106 CLOCK_CELL(CLK_CAN0_0, CLK_CAN0_0, "can0_can_clk", true, 100000000), 107 CLOCK_CELL(CLK_CAN0_1, CLK_CAN0_1, "can0_axi_clk", true, 100000000), 108 CLOCK_CELL(CLK_CAN1_0, CLK_CAN1_0, "can1_can_clk", true, 100000000), 109 CLOCK_CELL(CLK_CAN1_1, CLK_CAN1_1, "can1_axi_clk", true, 100000000), 110 CLOCK_CELL(CLK_CAN2_0, CLK_CAN2_0, "can2_can_clk", true, 100000000), 111 CLOCK_CELL(CLK_CAN2_1, CLK_CAN2_1, "can2_axi_clk", true, 100000000), 112 CLOCK_CELL(CLK_CAN3_0, CLK_CAN3_0, "can3_can_clk", true, 100000000), 113 CLOCK_CELL(CLK_CAN3_1, CLK_CAN3_1, "can3_axi_clk", true, 100000000), 114 CLOCK_CELL(CLK_PS_GPIO_0, CLK_PS_GPIO_0, "ps_gpio_clk", true, 100000000), 115 CLOCK_CELL(CLK_PMC_GPIO_0, CLK_PMC_GPIO_0, "pmc_gpio_clk", true, 100000000), 116 CLOCK_CELL(CLK_SPI0_0, CLK_SPI0_0, "spi0_ref_clk", true, 100000000), 117 CLOCK_CELL(CLK_SPI0_1, CLK_SPI0_1, "spi0_pclk", true, 100000000), 118 CLOCK_CELL(CLK_SPI1_0, CLK_SPI1_0, "spi1_ref_clk", true, 100000000), 119 CLOCK_CELL(CLK_SPI1_1, CLK_SPI1_1, "spi1_pclk", true, 100000000), 120 CLOCK_CELL(CLK_I3C0_0, CLK_I3C0_0, "i3c0_clk", true, 100000000), 121 CLOCK_CELL(CLK_I3C1_0, CLK_I3C1_0, "i3c1_clk", true, 100000000), 122 CLOCK_CELL(CLK_I3C2_0, CLK_I3C2_0, "i3c2_clk", true, 100000000), 123 CLOCK_CELL(CLK_I3C3_0, CLK_I3C3_0, "i3c3_clk", true, 100000000), 124 CLOCK_CELL(CLK_I3C4_0, CLK_I3C4_0, "i3c4_clk", true, 100000000), 125 CLOCK_CELL(CLK_I3C5_0, CLK_I3C5_0, "i3c5_clk", true, 100000000), 126 CLOCK_CELL(CLK_I3C6_0, CLK_I3C6_0, "i3c6_clk", true, 100000000), 127 CLOCK_CELL(CLK_I3C7_0, CLK_I3C7_0, "i3c7_clk", true, 100000000), 128 }; 129 130 /* 131 * struct scmi_reset - Data for the exposed reset controller 132 * @reset_id: Reset identifier in RCC reset driver 133 * @name: Reset string ID exposed to agent 134 */ 135 struct scmi_reset { 136 unsigned long reset_id; 137 const char *name; 138 }; 139 140 #define RESET_CELL(_scmi_id, _id, _name) \ 141 [_scmi_id] = { \ 142 .reset_id = (_id), \ 143 .name = (_name), \ 144 } 145 146 static struct scmi_reset scmi0_reset[] = { 147 RESET_CELL(RESET_GEM0_0, RESET_GEM0_0, "gem0"), 148 RESET_CELL(RESET_GEM1_0, RESET_GEM1_0, "gem1"), 149 RESET_CELL(RESET_SERIAL0_0, RESET_SERIAL0_0, "serial0"), 150 RESET_CELL(RESET_SERIAL1_0, RESET_SERIAL1_0, "serial1"), 151 RESET_CELL(RESET_UFS0_0, RESET_UFS0_0, "ufs0"), 152 RESET_CELL(RESET_I2C0_0, RESET_I2C0_0, "i2c0"), 153 RESET_CELL(RESET_I2C1_0, RESET_I2C1_0, "i2c1"), 154 RESET_CELL(RESET_I2C2_0, RESET_I2C2_0, "i2c2"), 155 RESET_CELL(RESET_I2C3_0, RESET_I2C3_0, "i2c3"), 156 RESET_CELL(RESET_I2C4_0, RESET_I2C4_0, "i2c4"), 157 RESET_CELL(RESET_I2C5_0, RESET_I2C5_0, "i2c5"), 158 RESET_CELL(RESET_I2C6_0, RESET_I2C6_0, "i2c6"), 159 RESET_CELL(RESET_I2C7_0, RESET_I2C7_0, "i2c7"), 160 RESET_CELL(RESET_I2C8_0, RESET_I2C8_0, "i2c8"), 161 RESET_CELL(RESET_OSPI0_0, RESET_OSPI0_0, "ospi"), 162 RESET_CELL(RESET_USB0_0, RESET_USB0_0, "usb0_0"), 163 RESET_CELL(RESET_USB0_1, RESET_USB0_1, "usb0_1"), 164 RESET_CELL(RESET_USB0_2, RESET_USB0_2, "usb0_2"), 165 RESET_CELL(RESET_USB1_0, RESET_USB1_0, "usb1_0"), 166 RESET_CELL(RESET_USB1_1, RESET_USB1_1, "usb1_1"), 167 RESET_CELL(RESET_USB1_2, RESET_USB1_2, "usb1_2"), 168 RESET_CELL(RESET_MMC0_0, RESET_MMC0_0, "mmc0"), 169 RESET_CELL(RESET_MMC1_0, RESET_MMC1_0, "mmc1"), 170 RESET_CELL(RESET_SPI0_0, RESET_SPI0_0, "spi0"), 171 RESET_CELL(RESET_SPI1_0, RESET_SPI1_0, "spi1"), 172 RESET_CELL(RESET_QSPI0_0, RESET_QSPI0_0, "qspi"), 173 RESET_CELL(RESET_I3C0_0, RESET_I3C0_0, "i3c0"), 174 RESET_CELL(RESET_I3C1_0, RESET_I3C1_0, "i3c1"), 175 RESET_CELL(RESET_I3C2_0, RESET_I3C2_0, "i3c2"), 176 RESET_CELL(RESET_I3C3_0, RESET_I3C3_0, "i3c3"), 177 RESET_CELL(RESET_I3C4_0, RESET_I3C4_0, "i3c4"), 178 RESET_CELL(RESET_I3C5_0, RESET_I3C5_0, "i3c5"), 179 RESET_CELL(RESET_I3C6_0, RESET_I3C6_0, "i3c6"), 180 RESET_CELL(RESET_I3C7_0, RESET_I3C7_0, "i3c7"), 181 RESET_CELL(RESET_I3C8_0, RESET_I3C8_0, "i3c8"), 182 }; 183 184 struct scmi_resources { 185 struct scmi_clk *clock; 186 size_t clock_count; 187 struct scmi_reset *reset; 188 size_t reset_count; 189 190 }; 191 192 static const struct scmi_resources resources[] = { 193 [0] = { 194 .clock = scmi0_clock, 195 .clock_count = ARRAY_SIZE(scmi0_clock), 196 .reset = scmi0_reset, 197 .reset_count = ARRAY_SIZE(scmi0_reset), 198 }, 199 }; 200 201 static const struct scmi_resources *find_resource(unsigned int agent_id) 202 { 203 assert(agent_id < ARRAY_SIZE(resources)); 204 205 return &resources[agent_id]; 206 } 207 208 static struct scmi_clk *clk_find(unsigned int agent_id, unsigned int scmi_id) 209 { 210 const struct scmi_resources *resource = find_resource(agent_id); 211 size_t n = 0U; 212 struct scmi_clk *ret = NULL; 213 214 if (resource != NULL) { 215 for (n = 0U; n < resource->clock_count; n++) { 216 if (n == scmi_id) { 217 ret = &resource->clock[n]; 218 break; 219 } 220 } 221 } 222 223 return ret; 224 } 225 226 size_t plat_scmi_clock_count(unsigned int agent_id) 227 { 228 const struct scmi_resources *resource = find_resource(agent_id); 229 size_t ret; 230 231 if (resource == NULL) { 232 ret = 0U; 233 } else { 234 VERBOSE("SCMI: CLK: %d clocks\n", (unsigned int)resource->clock_count); 235 236 ret = resource->clock_count; 237 } 238 return ret; 239 } 240 241 const char *plat_scmi_clock_get_name(unsigned int agent_id, unsigned int scmi_id) 242 { 243 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 244 const char *ret; 245 246 if (clock == NULL) { 247 ret = NULL; 248 } else { 249 VERBOSE("SCMI: CLK: id: %d, get_name: %s\n", scmi_id, clock->name); 250 251 ret = clock->name; 252 } 253 return ret; 254 }; 255 256 /* Called by Linux */ 257 int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id, 258 unsigned long *array, size_t *nb_elts, 259 uint32_t start_idx) 260 { 261 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 262 263 if (clock == NULL) { 264 return SCMI_NOT_FOUND; 265 } 266 267 if (start_idx > 0) { 268 return SCMI_OUT_OF_RANGE; 269 } 270 271 if (array == NULL) { 272 *nb_elts = 1U; 273 } else if (*nb_elts == 1U) { 274 *array = clock->rate; 275 VERBOSE("SCMI: CLK: id: %d, clk_name: %s, get_rate %lu\n", 276 scmi_id, clock->name, *array); 277 } else { 278 return SCMI_GENERIC_ERROR; 279 } 280 281 return SCMI_SUCCESS; 282 } 283 284 unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, unsigned int scmi_id) 285 { 286 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 287 unsigned long ret; 288 289 if ((clock == NULL)) { 290 ret = SCMI_NOT_FOUND; 291 } else { 292 VERBOSE("SCMI: CLK: id: %d, get_rate: %lu\n", scmi_id, clock->rate); 293 ret = clock->rate; 294 } 295 return ret; 296 } 297 298 int32_t plat_scmi_clock_set_rate(unsigned int agent_id, unsigned int scmi_id, 299 unsigned long rate) 300 { 301 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 302 unsigned long ret = UL(SCMI_SUCCESS); 303 304 if ((clock == NULL)) { 305 ret = SCMI_NOT_FOUND; 306 } else { 307 VERBOSE("SCMI: CLK: id: %d, set_rate: %lu\n", scmi_id, rate); 308 clock->rate = rate; 309 } 310 return ret; 311 } 312 313 int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id) 314 { 315 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 316 int32_t ret; 317 318 if ((clock == NULL)) { 319 ret = SCMI_NOT_FOUND; 320 } else { 321 VERBOSE("SCMI: CLK: id: %d, get_state: %d\n", scmi_id, clock->enabled); 322 323 if (clock->enabled) { 324 ret = HIGH; 325 } else { 326 ret = LOW; 327 } 328 } 329 return ret; 330 } 331 332 int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id, 333 bool enable_not_disable) 334 { 335 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 336 int32_t ret; 337 338 if (clock == NULL) { 339 ret = SCMI_NOT_FOUND; 340 } else { 341 if (enable_not_disable) { 342 if (!clock->enabled) { 343 VERBOSE("SCMI: clock: %u enable\n", scmi_id); 344 clock->enabled = true; 345 } 346 } else { 347 if (clock->enabled) { 348 VERBOSE("SCMI: clock: %u disable\n", scmi_id); 349 clock->enabled = false; 350 } 351 } 352 353 VERBOSE("SCMI: CLK: id: %d, set_state: %d\n", scmi_id, clock->enabled); 354 355 ret = SCMI_SUCCESS; 356 } 357 358 return ret; 359 } 360 361 362 /* 363 * Platform SCMI reset domains 364 */ 365 static struct scmi_reset *find_reset(unsigned int agent_id, 366 unsigned int scmi_id) 367 { 368 const struct scmi_resources *resource = find_resource(agent_id); 369 size_t n; 370 371 if (resource != NULL) { 372 for (n = 0U; n < resource->reset_count; n++) { 373 if (n == scmi_id) { 374 return &resource->reset[n]; 375 } 376 } 377 } 378 379 return NULL; 380 } 381 382 const char *plat_scmi_rstd_get_name(unsigned int agent_id, unsigned int scmi_id) 383 { 384 const struct scmi_reset *reset = find_reset(agent_id, scmi_id); 385 386 if (reset == NULL) { 387 return NULL; 388 } 389 390 return reset->name; 391 } 392 393 size_t plat_scmi_rstd_count(unsigned int agent_id) 394 { 395 const struct scmi_resources *resource = find_resource(agent_id); 396 397 if (resource == NULL) { 398 return 0U; 399 } 400 401 return resource->reset_count; 402 } 403 404 int32_t plat_scmi_rstd_autonomous(unsigned int agent_id, unsigned int scmi_id, 405 uint32_t state) 406 { 407 const struct scmi_reset *reset = find_reset(agent_id, scmi_id); 408 409 if (reset == NULL) { 410 return SCMI_NOT_FOUND; 411 } 412 413 /* Supports only reset with context loss */ 414 if (state != 0U) { 415 return SCMI_NOT_SUPPORTED; 416 } 417 418 NOTICE("SCMI reset on ID %lu/%s\n", 419 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); 420 421 return SCMI_SUCCESS; 422 } 423 424 int32_t plat_scmi_rstd_set_state(unsigned int agent_id, unsigned int scmi_id, 425 bool assert_not_deassert) 426 { 427 const struct scmi_reset *reset = find_reset(agent_id, scmi_id); 428 429 if (reset == NULL) { 430 return SCMI_NOT_FOUND; 431 } 432 433 if (assert_not_deassert) { 434 NOTICE("SCMI reset %lu/%s set\n", 435 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); 436 } else { 437 NOTICE("SCMI reset %lu/%s release\n", 438 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); 439 } 440 441 return SCMI_SUCCESS; 442 } 443 444 /* Currently only one channel is supported. Expectation is that channel 0 is used by NS SW */ 445 static struct scmi_msg_channel scmi_channel[] = { 446 [0] = { 447 .shm_addr = SMT_BUFFER_BASE, 448 .shm_size = SMT_BUF_SLOT_SIZE, 449 }, 450 }; 451 452 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id) 453 { 454 assert(agent_id < ARRAY_SIZE(scmi_channel)); 455 456 VERBOSE("%d: SCMI asking for channel\n", agent_id); 457 458 /* Just in case that code is reused */ 459 return &scmi_channel[agent_id]; 460 } 461 462 /* Base protocol implementations */ 463 const char *plat_scmi_vendor_name(void) 464 { 465 return SCMI_VENDOR; 466 } 467 468 const char *plat_scmi_sub_vendor_name(void) 469 { 470 return SCMI_PRODUCT; 471 } 472 473 /* Currently supporting Clocks and Reset Domains */ 474 static const uint8_t plat_protocol_list[] = { 475 SCMI_PROTOCOL_ID_BASE, 476 SCMI_PROTOCOL_ID_CLOCK, 477 SCMI_PROTOCOL_ID_RESET_DOMAIN, 478 /* 479 *SCMI_PROTOCOL_ID_POWER_DOMAIN, 480 *SCMI_PROTOCOL_ID_SENSOR, 481 */ 482 0U /* Null termination */ 483 }; 484 485 size_t plat_scmi_protocol_count(void) 486 { 487 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1U; 488 489 VERBOSE("SCMI: Protocol count: %d\n", (int32_t)count); 490 491 return count; 492 } 493 494 const uint8_t *plat_scmi_protocol_list(unsigned int agent_id __unused) 495 { 496 return plat_protocol_list; 497 } 498 499 void init_scmi_server(void) 500 { 501 size_t i; 502 int32_t ret; 503 504 for (i = 0U; i < ARRAY_SIZE(scmi_channel); i++) 505 scmi_smt_init_agent_channel(&scmi_channel[i]); 506 507 INFO("SCMI: Server initialized\n"); 508 509 if (platform_id == QEMU) { 510 /* default setting is for QEMU */ 511 } else if (platform_id == SPP) { 512 for (i = 0U; i < ARRAY_SIZE(scmi0_clock); i++) { 513 514 /* Keep i2c on 100MHz to calculate rates properly */ 515 if (i >= CLK_I2C0_0 && i <= CLK_I2C7_0) 516 continue; 517 /* 518 * SPP supports multiple versions. 519 * The cpu_clock value is set to corresponding SPP 520 * version in early platform setup, resuse the same 521 * value here. 522 */ 523 ret = plat_scmi_clock_set_rate(0, i, cpu_clock); 524 if (ret < 0) { 525 NOTICE("Failed to set clock rate for SPP scmi_id=%ld\n", i); 526 } 527 } 528 } else { 529 /* Making MISRA C 2012 15.7 compliant */ 530 } 531 } 532