| 10640d24 | 09-Jun-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "GICv3: GIC-600: Detect GIC-600 at runtime" into integration |
| 452d5e5e | 02-Jun-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
plat/fvp: Add support for dynamic description of secure interrupts
Using the fconf framework, the Group 0 and Group 1 secure interrupt descriptors are moved to device tree and retrieved in runtime.
plat/fvp: Add support for dynamic description of secure interrupts
Using the fconf framework, the Group 0 and Group 1 secure interrupt descriptors are moved to device tree and retrieved in runtime. This feature is enabled by the build flag SEC_INT_DESC_IN_FCONF.
Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
show more ...
|
| b4ad365a | 25-Mar-2020 |
Andre Przywara <andre.przywara@arm.com> |
GICv3: GIC-600: Detect GIC-600 at runtime
The only difference between GIC-500 and GIC-600 relevant to TF-A is the differing power management sequence. A certain GIC implementation is detectable at r
GICv3: GIC-600: Detect GIC-600 at runtime
The only difference between GIC-500 and GIC-600 relevant to TF-A is the differing power management sequence. A certain GIC implementation is detectable at runtime, for instance by checking the IIDR register. Let's add that test before initiating the GIC-600 specific sequence, so the code can be used on both GIC-600 and GIC-500 chips alike, without deciding on a GIC chip at compile time.
This means that the GIC-500 "driver" is now redundant. To allow minimal platform support, add a switch to disable GIC-600 support.
Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
show more ...
|
| b62a5313 | 15-May-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
doc: Fix plat_sdei_validate_entry_point() documentation
Document the second argument of the function. Minor rewording.
Change-Id: I190794b8cc74c99db4cfe6efc225217c32dd0774 Signed-off-by: Sandrine B
doc: Fix plat_sdei_validate_entry_point() documentation
Document the second argument of the function. Minor rewording.
Change-Id: I190794b8cc74c99db4cfe6efc225217c32dd0774 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
show more ...
|
| 6cac724d | 22-Apr-2020 |
johpow01 <john.powell@arm.com> |
Enable v8.6 WFE trap delays
This patch enables the v8.6 extension to add a delay before WFE traps are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in plat/common/aarch64/plat_common
Enable v8.6 WFE trap delays
This patch enables the v8.6 extension to add a delay before WFE traps are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in plat/common/aarch64/plat_common.c that disables this feature by default but platform-specific code can override it when needed.
The only hook provided sets the TWED fields in SCR_EL3, there are similar fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to control WFE trap delays in lower ELs but these should be configured by code running at EL2 and/or EL1 depending on the platform configuration and is outside the scope of TF-A.
Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I0a9bb814205efeab693a3d0a0623e62144abba2d
show more ...
|
| cbf9e84a | 18-Dec-2019 |
Balint Dobszay <balint.dobszay@arm.com> |
plat/arm/fvp: Support performing SDEI platform setup in runtime
This patch introduces dynamic configuration for SDEI setup and is supported when the new build flag SDEI_IN_FCONF is enabled. Instead
plat/arm/fvp: Support performing SDEI platform setup in runtime
This patch introduces dynamic configuration for SDEI setup and is supported when the new build flag SDEI_IN_FCONF is enabled. Instead of using C arrays and processing the configuration at compile time, the config is moved to dts files. It will be retrieved at runtime during SDEI init, using the fconf layer.
Change-Id: If5c35a7517ba00a9f258d7f3e7c8c20cee169a31 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Co-authored-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
show more ...
|
| 45aecff0 | 28-Apr-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
Implement workaround for AT speculative behaviour
During context switching from higher EL (EL2 or higher) to lower EL can cause incorrect translation in TLB due to speculative execution of AT instru
Implement workaround for AT speculative behaviour
During context switching from higher EL (EL2 or higher) to lower EL can cause incorrect translation in TLB due to speculative execution of AT instruction using out-of-context translation regime.
Workaround is implemented as below during EL's (EL1 or EL2) "context_restore" operation: 1. Disable page table walk using SCTLR.M and TCR.EPD0 & EPD1 bits for EL1 or EL2 (stage1 and stage2 disabled) 2. Save all system registers except TCR and SCTLR (for EL1 and EL2) 3. Do memory barrier operation (isb) to ensure all system register writes are done. 4. Restore TCR and SCTLR registers (for EL1 and EL2)
Errata details are available for various CPUs as below: Cortex-A76: 1165522 Cortex-A72: 1319367 Cortex-A57: 1319537 Cortex-A55: 1530923 Cortex-A53: 1530924
More details can be found in mail-chain: https://lists.trustedfirmware.org/pipermail/tf-a/2020-April/000445.html
Currently, Workaround is implemented as build option which is default disabled.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: If8545e61f782cb0c2dda7ffbaf50681c825bd2f0
show more ...
|
| 6e186332 | 17-Apr-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "doc: Set fconf as experimental feature" into integration |
| c2c150e7 | 09-Apr-2020 |
Louis Mayencourt <louis.mayencourt@arm.com> |
doc: Set fconf as experimental feature
Following the messages on the mailing list regarding the possible issue around reading DTB's information, we decided to flag the fconf feature as experimental.
doc: Set fconf as experimental feature
Following the messages on the mailing list regarding the possible issue around reading DTB's information, we decided to flag the fconf feature as experimental. A uniform approach should be used to handle properties miss and DTB validation.
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: Ib3c86e81fb2e89452c593f68d825d3d8f505e1fb
show more ...
|
| 3ba55a3c | 16-Apr-2020 |
laurenw-arm <lauren.wehrmeister@arm.com> |
docs: Update SMCCC doc, other changes for release
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ie842d6a9919776de151a4e9304f870aede07c47a |
| 5875f266 | 06-Apr-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A: Add GICv4 extension for GIC driver
This patch adds support for GICv4 extension. New `GIC_ENABLE_V4_EXTN` option passed to gicv3.mk makefile was added, and enables GICv4 related changes when se
TF-A: Add GICv4 extension for GIC driver
This patch adds support for GICv4 extension. New `GIC_ENABLE_V4_EXTN` option passed to gicv3.mk makefile was added, and enables GICv4 related changes when set to 1. This option defaults to 0.
Change-Id: I30ebe1b7a98d3a54863900f37eda4589c707a288 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
show more ...
|
| 8f3ad766 | 06-Apr-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A GICv3 driver: Add extended PPI and SPI range
This patch provides support for GICv3.1 extended PPI and SPI range. The option is enabled by setting to 1 and passing `GIC_EXT_INTID` build flag to
TF-A GICv3 driver: Add extended PPI and SPI range
This patch provides support for GICv3.1 extended PPI and SPI range. The option is enabled by setting to 1 and passing `GIC_EXT_INTID` build flag to gicv3.mk makefile. This option defaults to 0 with no extended range support.
Change-Id: I7d09086fe22ea531c5df51a8a1efd8928458d394 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
show more ...
|
| 7ff088d1 | 22-Mar-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
Enable MTE support
Enable MTE support by adding memory tag option in Makefile This option is available only when ARMv8.5-MemTag is implemented
MTE options are added in latest clang and armclang com
Enable MTE support
Enable MTE support by adding memory tag option in Makefile This option is available only when ARMv8.5-MemTag is implemented
MTE options are added in latest clang and armclang compiler which support below options: for clang <version 11.0.0> 1. -march=arm8.5-a+memtag 2. -fsanitize=memtag
for armclang <version 6.12> 1. -march=arm8.5-a+memtag 2. -mmemtag-stack
Set the option SUPPORT_STACK_MEMTAG=yes to enable memory stack tagging.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I4e0bbde4e9769ce03ead6f550158e22f32c1c413
show more ...
|
| a6ea06f5 | 23-Mar-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A GICv3 driver: Introduce makefile
This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affectin
TF-A GICv3 driver: Introduce makefile
This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document.
NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles.
Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
show more ...
|
| b3250f58 | 27-Mar-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "doc: add spm and spmd related build options" into integration |
| 4c65b4de | 26-Mar-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
doc: add spm and spmd related build options
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I93892dbe76611a7a4b852af3272a0e6271ae037b |
| 2b06610c | 26-Mar-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
Fix warnings in porting-guide.rst
Fix below warnings appeared in porting-guide.rst WARNING: Title underline too short.
Change-Id: Ibc0eba0da72a53a5f9b61c49a8bf7a10b17bc3b8 Signed-off-by: Manish V B
Fix warnings in porting-guide.rst
Fix below warnings appeared in porting-guide.rst WARNING: Title underline too short.
Change-Id: Ibc0eba0da72a53a5f9b61c49a8bf7a10b17bc3b8 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| ce8dfd28 | 24-Mar-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "fconf: Clean Arm IO" into integration |
| 0e753437 | 22-Feb-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
Implement SMCCC_ARCH_SOC_ID SMC call
Implemented SMCCC_ARCH_SOC_ID call in order to get below SOC information:
1. SOC revision 2. SOC version
Implementation done using below SMCCC specification do
Implement SMCCC_ARCH_SOC_ID SMC call
Implemented SMCCC_ARCH_SOC_ID call in order to get below SOC information:
1. SOC revision 2. SOC version
Implementation done using below SMCCC specification document: https://developer.arm.com/docs/den0028/c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ie0595f1c345a6429a6fb4a7f05534a0ca9c9a48b
show more ...
|
| a6de824f | 28-Feb-2020 |
Louis Mayencourt <louis.mayencourt@arm.com> |
fconf: Clean Arm IO
Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This removes the duplicate io_policies and functions definition.
This patch: - replace arm_io_storage.c
fconf: Clean Arm IO
Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This removes the duplicate io_policies and functions definition.
This patch: - replace arm_io_storage.c with the content of arm_fconf_io_storage.c - rename the USE_FCONF_BASED_IO option into ARM_IO_IN_DTB. - use the ARM_IO_IN_DTB option to compile out io_policies moved in dtb. - propagate DEFINES when parsing dts. - use ARM_IO_IN_DTB to include or not uuid nodes in fw_config dtb. - set the ARM_IO_IN_DTB to 0 by default for fvp. This ensure that the behavior of fvp stays the same as it was before the introduction of fconf.
Change-Id: Ia774a96d1d3a2bccad29f7ce2e2b4c21b26c080e Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
show more ...
|
| 46b3003b | 10-Mar-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Necessary fix in drivers to upgrade to mbedtls-2.18.0" into integration |
| f97062a5 | 15-Nov-2019 |
Sumit Garg <sumit.garg@linaro.org> |
docs: Update docs with firmware encryption feature
Update documentation with optional firmware encryption feature.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I26691b18e1ee52a73090
docs: Update docs with firmware encryption feature
Update documentation with optional firmware encryption feature.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I26691b18e1ee52a73090954260f26f2865c4e05a
show more ...
|
| 93ee2799 | 06-Mar-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Necessary fix in drivers to upgrade to mbedtls-2.18.0
Include x509.h header file explicitly. Update docs.
Change-Id: If2e52c2cd3056654406b7b6779b67eea5cc04a48 Signed-off-by: Madhukar Pappireddy <ma
Necessary fix in drivers to upgrade to mbedtls-2.18.0
Include x509.h header file explicitly. Update docs.
Change-Id: If2e52c2cd3056654406b7b6779b67eea5cc04a48 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
show more ...
|
| 7cda17bb | 15-Nov-2019 |
Sumit Garg <sumit.garg@linaro.org> |
drivers: crypto: Add authenticated decryption framework
Add framework for autheticated decryption of data. Currently this patch optionally imports mbedtls library as a backend if build option "DECRY
drivers: crypto: Add authenticated decryption framework
Add framework for autheticated decryption of data. Currently this patch optionally imports mbedtls library as a backend if build option "DECRYPTION_SUPPORT = aes_gcm" is set to perform authenticated decryption using AES-GCM algorithm.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I2966f0e79033151012bf4ffc66f484cd949e7271
show more ...
|
| 7c72beae | 26-Feb-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "tools: Small improvement to print_memory_map script" into integration |