1# 2# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture major and minor versions: 8.0 by default. 23ARM_ARCH_MAJOR := 8 24ARM_ARCH_MINOR := 0 25 26# Base commit to perform code check on 27BASE_COMMIT := origin/master 28 29# Execute BL2 at EL3 30BL2_AT_EL3 := 0 31 32# BL2 image is stored in XIP memory, for now, this option is only supported 33# when BL2_AT_EL3 is 1. 34BL2_IN_XIP_MEM := 0 35 36# Do dcache invalidate upon BL2 entry at EL3 37BL2_INV_DCACHE := 1 38 39# Select the branch protection features to use. 40BRANCH_PROTECTION := 0 41 42# By default, consider that the platform may release several CPUs out of reset. 43# The platform Makefile is free to override this value. 44COLD_BOOT_SINGLE_CPU := 0 45 46# Flag to compile in coreboot support code. Exclude by default. The coreboot 47# Makefile system will set this when compiling TF as part of a coreboot image. 48COREBOOT := 0 49 50# For Chain of Trust 51CREATE_KEYS := 1 52 53# Build flag to include AArch32 registers in cpu context save and restore during 54# world switch. This flag must be set to 0 for AArch64-only platforms. 55CTX_INCLUDE_AARCH32_REGS := 1 56 57# Include FP registers in cpu context 58CTX_INCLUDE_FPREGS := 0 59 60# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 61# must be set to 1 if the platform wants to use this feature in the Secure 62# world. It is not needed to use it in the Non-secure world. 63CTX_INCLUDE_PAUTH_REGS := 0 64 65# Debug build 66DEBUG := 0 67 68# By default disable authenticated decryption support. 69DECRYPTION_SUPPORT := none 70 71# Build platform 72DEFAULT_PLAT := fvp 73 74# Disable the generation of the binary image (ELF only). 75DISABLE_BIN_GENERATION := 0 76 77# Enable capability to disable authentication dynamically. Only meant for 78# development platforms. 79DYN_DISABLE_AUTH := 0 80 81# Build option to enable MPAM for lower ELs 82ENABLE_MPAM_FOR_LOWER_ELS := 0 83 84# Flag to Enable Position Independant support (PIE) 85ENABLE_PIE := 0 86 87# Flag to enable Performance Measurement Framework 88ENABLE_PMF := 0 89 90# Flag to enable PSCI STATs functionality 91ENABLE_PSCI_STAT := 0 92 93# Flag to enable runtime instrumentation using PMF 94ENABLE_RUNTIME_INSTRUMENTATION := 0 95 96# Flag to enable stack corruption protection 97ENABLE_STACK_PROTECTOR := 0 98 99# Flag to enable exception handling in EL3 100EL3_EXCEPTION_HANDLING := 0 101 102# Flag to enable Branch Target Identification. 103# Internal flag not meant for direct setting. 104# Use BRANCH_PROTECTION to enable BTI. 105ENABLE_BTI := 0 106 107# Flag to enable Pointer Authentication. 108# Internal flag not meant for direct setting. 109# Use BRANCH_PROTECTION to enable PAUTH. 110ENABLE_PAUTH := 0 111 112# Build flag to treat usage of deprecated platform and framework APIs as error. 113ERROR_DEPRECATED := 0 114 115# Fault injection support 116FAULT_INJECTION_SUPPORT := 0 117 118# Byte alignment that each component in FIP is aligned to 119FIP_ALIGN := 0 120 121# Default FIP file name 122FIP_NAME := fip.bin 123 124# Default FWU_FIP file name 125FWU_FIP_NAME := fwu_fip.bin 126 127# For Chain of Trust 128GENERATE_COT := 0 129 130# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 131# default, they are for Secure EL1. 132GICV2_G0_FOR_EL3 := 0 133 134# Route External Aborts to EL3. Disabled by default; External Aborts are handled 135# by lower ELs. 136HANDLE_EA_EL3_FIRST := 0 137 138# Whether system coherency is managed in hardware, without explicit software 139# operations. 140HW_ASSISTED_COHERENCY := 0 141 142# Set the default algorithm for the generation of Trusted Board Boot keys 143KEY_ALG := rsa 144 145# Option to build TF with Measured Boot support 146MEASURED_BOOT := 0 147 148# NS timer register save and restore 149NS_TIMER_SWITCH := 0 150 151# Include lib/libc in the final image 152OVERRIDE_LIBC := 0 153 154# Build PL011 UART driver in minimal generic UART mode 155PL011_GENERIC_UART := 0 156 157# By default, consider that the platform's reset address is not programmable. 158# The platform Makefile is free to override this value. 159PROGRAMMABLE_RESET_ADDRESS := 0 160 161# Flag used to choose the power state format: Extended State-ID or Original 162PSCI_EXTENDED_STATE_ID := 0 163 164# Enable RAS support 165RAS_EXTENSION := 0 166 167# By default, BL1 acts as the reset handler, not BL31 168RESET_TO_BL31 := 0 169 170# For Chain of Trust 171SAVE_KEYS := 0 172 173# Software Delegated Exception support 174SDEI_SUPPORT := 0 175 176# Whether code and read-only data should be put on separate memory pages. The 177# platform Makefile is free to override this value. 178SEPARATE_CODE_AND_RODATA := 0 179 180# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 181# separate memory region, which may be discontiguous from the rest of BL31. 182SEPARATE_NOBITS_REGION := 0 183 184# If the BL31 image initialisation code is recalimed after use for the secondary 185# cores stack 186RECLAIM_INIT_CODE := 0 187 188# SPD choice 189SPD := none 190 191# Enable the Management Mode (MM)-based Secure Partition Manager implementation 192SPM_MM := 0 193 194# Use SPM at S-EL2 as a default config for SPMD 195SPMD_SPM_AT_SEL2 := 1 196 197# Flag to introduce an infinite loop in BL1 just before it exits into the next 198# image. This is meant to help debugging the post-BL2 phase. 199SPIN_ON_BL1_EXIT := 0 200 201# Flags to build TF with Trusted Boot support 202TRUSTED_BOARD_BOOT := 0 203 204# Build option to choose whether Trusted Firmware uses Coherent memory or not. 205USE_COHERENT_MEM := 1 206 207# Build option to add debugfs support 208USE_DEBUGFS := 0 209 210# Build option to fconf based io 211USE_FCONF_BASED_IO := 0 212 213# Build option to choose whether Trusted Firmware uses library at ROM 214USE_ROMLIB := 0 215 216# Build option to choose whether the xlat tables of BL images can be read-only. 217# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 218# which is the per BL-image option that actually enables the read-only tables 219# API. The reason for having this additional option is to have a common high 220# level makefile where we can check for incompatible features/build options. 221ALLOW_RO_XLAT_TABLES := 0 222 223# Chain of trust. 224COT := tbbr 225 226# Use tbbr_oid.h instead of platform_oid.h 227USE_TBBR_DEFS := 1 228 229# Build verbosity 230V := 0 231 232# Whether to enable D-Cache early during warm boot. This is usually 233# applicable for platforms wherein interconnect programming is not 234# required to enable cache coherency after warm reset (eg: single cluster 235# platforms). 236WARMBOOT_ENABLE_DCACHE_EARLY := 0 237 238# Build option to enable/disable the Statistical Profiling Extensions 239ENABLE_SPE_FOR_LOWER_ELS := 1 240 241# SPE is only supported on AArch64 so disable it on AArch32. 242ifeq (${ARCH},aarch32) 243 override ENABLE_SPE_FOR_LOWER_ELS := 0 244endif 245 246# Include Memory Tagging Extension registers in cpu context. This must be set 247# to 1 if the platform wants to use this feature in the Secure world and MTE is 248# enabled at ELX. 249CTX_INCLUDE_MTE_REGS := 0 250 251ENABLE_AMU := 0 252 253# By default, enable Scalable Vector Extension if implemented for Non-secure 254# lower ELs 255# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 256ifneq (${ARCH},aarch32) 257 ENABLE_SVE_FOR_NS := 1 258else 259 override ENABLE_SVE_FOR_NS := 0 260endif 261 262SANITIZE_UB := off 263 264# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 265# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 266# Default: disabled 267USE_SPINLOCK_CAS := 0 268 269# Enable Link Time Optimization 270ENABLE_LTO := 0 271 272# Build flag to include EL2 registers in cpu context save and restore during 273# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option. 274# Default is 0. 275CTX_INCLUDE_EL2_REGS := 0 276