1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/arm/gicv3.h> 14 #include <lib/spinlock.h> 15 16 #include "gicv3_private.h" 17 18 const gicv3_driver_data_t *gicv3_driver_data; 19 20 /* 21 * Spinlock to guard registers needing read-modify-write. APIs protected by this 22 * spinlock are used either at boot time (when only a single CPU is active), or 23 * when the system is fully coherent. 24 */ 25 static spinlock_t gic_lock; 26 27 /* 28 * Redistributor power operations are weakly bound so that they can be 29 * overridden 30 */ 31 #pragma weak gicv3_rdistif_off 32 #pragma weak gicv3_rdistif_on 33 34 /* Check interrupt ID for SGI/(E)PPI and (E)SPIs */ 35 static bool is_sgi_ppi(unsigned int id); 36 37 /* 38 * Helper macros to save and restore GICR and GICD registers 39 * corresponding to their numbers to and from the context 40 */ 41 #define RESTORE_GICR_REG(base, ctx, name, i) \ 42 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)]) 43 44 #define SAVE_GICR_REG(base, ctx, name, i) \ 45 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i)) 46 47 /* Helper macros to save and restore GICD registers to and from the context */ 48 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 49 do { \ 50 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 51 int_id += (1U << REG##R_SHIFT)) { \ 52 gicd_write_##reg((base), int_id, \ 53 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 54 REG##R_SHIFT]); \ 55 } \ 56 } while (false) 57 58 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 59 do { \ 60 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 61 int_id += (1U << REG##R_SHIFT)) { \ 62 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 63 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \ 64 } \ 65 } while (false) 66 67 #if GIC_EXT_INTID 68 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 69 do { \ 70 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 71 int_id += (1U << REG##R_SHIFT)) { \ 72 gicd_write_##reg((base), int_id, \ 73 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - MIN_SPI_ID))\ 74 >> REG##R_SHIFT]); \ 75 } \ 76 } while (false) 77 78 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 79 do { \ 80 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 81 int_id += (1U << REG##R_SHIFT)) { \ 82 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - MIN_SPI_ID))\ 83 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\ 84 } \ 85 } while (false) 86 #else 87 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) 88 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) 89 #endif /* GIC_EXT_INTID */ 90 91 /******************************************************************************* 92 * This function initialises the ARM GICv3 driver in EL3 with provided platform 93 * inputs. 94 ******************************************************************************/ 95 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 96 { 97 unsigned int gic_version; 98 unsigned int gicv2_compat; 99 100 assert(plat_driver_data != NULL); 101 assert(plat_driver_data->gicd_base != 0U); 102 assert(plat_driver_data->rdistif_num != 0U); 103 assert(plat_driver_data->rdistif_base_addrs != NULL); 104 105 assert(IS_IN_EL3()); 106 107 assert((plat_driver_data->interrupt_props_num != 0U) ? 108 (plat_driver_data->interrupt_props != NULL) : 1); 109 110 /* Check for system register support */ 111 #ifndef __aarch64__ 112 assert((read_id_pfr1() & 113 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); 114 #else 115 assert((read_id_aa64pfr0_el1() & 116 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); 117 #endif /* !__aarch64__ */ 118 119 /* The GIC version should be 3 */ 120 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 121 gic_version >>= PIDR2_ARCH_REV_SHIFT; 122 gic_version &= PIDR2_ARCH_REV_MASK; 123 assert(gic_version == ARCH_REV_GICV3); 124 125 /* 126 * Find out whether the GIC supports the GICv2 compatibility mode. 127 * The ARE_S bit resets to 0 if supported 128 */ 129 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 130 gicv2_compat >>= CTLR_ARE_S_SHIFT; 131 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK; 132 133 if (plat_driver_data->gicr_base != 0U) { 134 /* 135 * Find the base address of each implemented Redistributor interface. 136 * The number of interfaces should be equal to the number of CPUs in the 137 * system. The memory for saving these addresses has to be allocated by 138 * the platform port 139 */ 140 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 141 plat_driver_data->rdistif_num, 142 plat_driver_data->gicr_base, 143 plat_driver_data->mpidr_to_core_pos); 144 #if !HW_ASSISTED_COHERENCY 145 /* 146 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 147 */ 148 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs), 149 plat_driver_data->rdistif_num * 150 sizeof(*(plat_driver_data->rdistif_base_addrs))); 151 #endif 152 } 153 gicv3_driver_data = plat_driver_data; 154 155 /* 156 * The GIC driver data is initialized by the primary CPU with caches 157 * enabled. When the secondary CPU boots up, it initializes the 158 * GICC/GICR interface with the caches disabled. Hence flush the 159 * driver data to ensure coherency. This is not required if the 160 * platform has HW_ASSISTED_COHERENCY enabled. 161 */ 162 #if !HW_ASSISTED_COHERENCY 163 flush_dcache_range((uintptr_t)&gicv3_driver_data, 164 sizeof(gicv3_driver_data)); 165 flush_dcache_range((uintptr_t)gicv3_driver_data, 166 sizeof(*gicv3_driver_data)); 167 #endif 168 169 INFO("GICv3 with%s legacy support detected." 170 " ARM GICv3 driver initialized in EL3\n", 171 (gicv2_compat == 0U) ? "" : "out"); 172 } 173 174 /******************************************************************************* 175 * This function initialises the GIC distributor interface based upon the data 176 * provided by the platform while initialising the driver. 177 ******************************************************************************/ 178 void __init gicv3_distif_init(void) 179 { 180 unsigned int bitmap; 181 182 assert(gicv3_driver_data != NULL); 183 assert(gicv3_driver_data->gicd_base != 0U); 184 185 assert(IS_IN_EL3()); 186 187 /* 188 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 189 * the ARE_S bit. The Distributor might generate a system error 190 * otherwise. 191 */ 192 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 193 CTLR_ENABLE_G0_BIT | 194 CTLR_ENABLE_G1S_BIT | 195 CTLR_ENABLE_G1NS_BIT, 196 RWP_TRUE); 197 198 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 199 gicd_set_ctlr(gicv3_driver_data->gicd_base, 200 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 201 202 /* Set the default attribute of all (E)SPIs */ 203 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 204 205 bitmap = gicv3_secure_spis_config_props( 206 gicv3_driver_data->gicd_base, 207 gicv3_driver_data->interrupt_props, 208 gicv3_driver_data->interrupt_props_num); 209 210 /* Enable the secure (E)SPIs now that they have been configured */ 211 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 212 } 213 214 /******************************************************************************* 215 * This function initialises the GIC Redistributor interface of the calling CPU 216 * (identified by the 'proc_num' parameter) based upon the data provided by the 217 * platform while initialising the driver. 218 ******************************************************************************/ 219 void gicv3_rdistif_init(unsigned int proc_num) 220 { 221 uintptr_t gicr_base; 222 unsigned int bitmap; 223 uint32_t ctlr; 224 225 assert(gicv3_driver_data != NULL); 226 assert(proc_num < gicv3_driver_data->rdistif_num); 227 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 228 assert(gicv3_driver_data->gicd_base != 0U); 229 230 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 231 assert((ctlr & CTLR_ARE_S_BIT) != 0U); 232 233 assert(IS_IN_EL3()); 234 235 /* Power on redistributor */ 236 gicv3_rdistif_on(proc_num); 237 238 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 239 assert(gicr_base != 0U); 240 241 /* Set the default attribute of all SGIs and (E)PPIs */ 242 gicv3_ppi_sgi_config_defaults(gicr_base); 243 244 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 245 gicv3_driver_data->interrupt_props, 246 gicv3_driver_data->interrupt_props_num); 247 248 /* Enable interrupt groups as required, if not already */ 249 if ((ctlr & bitmap) != bitmap) { 250 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 251 } 252 } 253 254 /******************************************************************************* 255 * Functions to perform power operations on GIC Redistributor 256 ******************************************************************************/ 257 void gicv3_rdistif_off(unsigned int proc_num) 258 { 259 } 260 261 void gicv3_rdistif_on(unsigned int proc_num) 262 { 263 } 264 265 /******************************************************************************* 266 * This function enables the GIC CPU interface of the calling CPU using only 267 * system register accesses. 268 ******************************************************************************/ 269 void gicv3_cpuif_enable(unsigned int proc_num) 270 { 271 uintptr_t gicr_base; 272 u_register_t scr_el3; 273 unsigned int icc_sre_el3; 274 275 assert(gicv3_driver_data != NULL); 276 assert(proc_num < gicv3_driver_data->rdistif_num); 277 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 278 assert(IS_IN_EL3()); 279 280 /* Mark the connected core as awake */ 281 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 282 gicv3_rdistif_mark_core_awake(gicr_base); 283 284 /* Disable the legacy interrupt bypass */ 285 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 286 287 /* 288 * Enable system register access for EL3 and allow lower exception 289 * levels to configure the same for themselves. If the legacy mode is 290 * not supported, the SRE bit is RAO/WI 291 */ 292 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 293 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 294 295 scr_el3 = read_scr_el3(); 296 297 /* 298 * Switch to NS state to write Non secure ICC_SRE_EL1 and 299 * ICC_SRE_EL2 registers. 300 */ 301 write_scr_el3(scr_el3 | SCR_NS_BIT); 302 isb(); 303 304 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 305 write_icc_sre_el1(ICC_SRE_SRE_BIT); 306 isb(); 307 308 /* Switch to secure state. */ 309 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 310 isb(); 311 312 /* Write the secure ICC_SRE_EL1 register */ 313 write_icc_sre_el1(ICC_SRE_SRE_BIT); 314 isb(); 315 316 /* Program the idle priority in the PMR */ 317 write_icc_pmr_el1(GIC_PRI_MASK); 318 319 /* Enable Group0 interrupts */ 320 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 321 322 /* Enable Group1 Secure interrupts */ 323 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 324 IGRPEN1_EL3_ENABLE_G1S_BIT); 325 isb(); 326 } 327 328 /******************************************************************************* 329 * This function disables the GIC CPU interface of the calling CPU using 330 * only system register accesses. 331 ******************************************************************************/ 332 void gicv3_cpuif_disable(unsigned int proc_num) 333 { 334 uintptr_t gicr_base; 335 336 assert(gicv3_driver_data != NULL); 337 assert(proc_num < gicv3_driver_data->rdistif_num); 338 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 339 340 assert(IS_IN_EL3()); 341 342 /* Disable legacy interrupt bypass */ 343 write_icc_sre_el3(read_icc_sre_el3() | 344 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 345 346 /* Disable Group0 interrupts */ 347 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 348 ~IGRPEN1_EL1_ENABLE_G0_BIT); 349 350 /* Disable Group1 Secure and Non-Secure interrupts */ 351 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 352 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 353 IGRPEN1_EL3_ENABLE_G1S_BIT)); 354 355 /* Synchronise accesses to group enable registers */ 356 isb(); 357 358 /* Mark the connected core as asleep */ 359 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 360 assert(gicr_base != 0U); 361 gicv3_rdistif_mark_core_asleep(gicr_base); 362 } 363 364 /******************************************************************************* 365 * This function returns the id of the highest priority pending interrupt at 366 * the GIC cpu interface. 367 ******************************************************************************/ 368 unsigned int gicv3_get_pending_interrupt_id(void) 369 { 370 unsigned int id; 371 372 assert(IS_IN_EL3()); 373 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 374 375 /* 376 * If the ID is special identifier corresponding to G1S or G1NS 377 * interrupt, then read the highest pending group 1 interrupt. 378 */ 379 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) { 380 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 381 } 382 383 return id; 384 } 385 386 /******************************************************************************* 387 * This function returns the type of the highest priority pending interrupt at 388 * the GIC cpu interface. The return values can be one of the following : 389 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 390 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 391 * 0 - 1019 : The interrupt type is secure Group 0. 392 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 393 * sufficient priority to be signaled 394 ******************************************************************************/ 395 unsigned int gicv3_get_pending_interrupt_type(void) 396 { 397 assert(IS_IN_EL3()); 398 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 399 } 400 401 /******************************************************************************* 402 * This function returns the type of the interrupt id depending upon the group 403 * this interrupt has been configured under by the interrupt controller i.e. 404 * group0 or group1 Secure / Non Secure. The return value can be one of the 405 * following : 406 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 407 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 408 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 409 * interrupt. 410 ******************************************************************************/ 411 unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int proc_num) 412 { 413 unsigned int igroup, grpmodr; 414 uintptr_t gicr_base; 415 416 assert(IS_IN_EL3()); 417 assert(gicv3_driver_data != NULL); 418 419 /* Ensure the parameters are valid */ 420 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID)); 421 assert(proc_num < gicv3_driver_data->rdistif_num); 422 423 /* All LPI interrupts are Group 1 non secure */ 424 if (id >= MIN_LPI_ID) { 425 return INTR_GROUP1NS; 426 } 427 428 /* Check interrupt ID */ 429 if (is_sgi_ppi(id)) { 430 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 431 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 432 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 433 igroup = gicr_get_igroupr(gicr_base, id); 434 grpmodr = gicr_get_igrpmodr(gicr_base, id); 435 } else { 436 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 437 assert(gicv3_driver_data->gicd_base != 0U); 438 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); 439 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); 440 } 441 442 /* 443 * If the IGROUP bit is set, then it is a Group 1 Non secure 444 * interrupt 445 */ 446 if (igroup != 0U) { 447 return INTR_GROUP1NS; 448 } 449 450 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 451 if (grpmodr != 0U) { 452 return INTR_GROUP1S; 453 } 454 455 /* Else it is a Group 0 Secure interrupt */ 456 return INTR_GROUP0; 457 } 458 459 /***************************************************************************** 460 * Function to save and disable the GIC ITS register context. The power 461 * management of GIC ITS is implementation-defined and this function doesn't 462 * save any memory structures required to support ITS. As the sequence to save 463 * this state is implementation defined, it should be executed in platform 464 * specific code. Calling this function alone and then powering down the GIC and 465 * ITS without implementing the aforementioned platform specific code will 466 * corrupt the ITS state. 467 * 468 * This function must be invoked after the GIC CPU interface is disabled. 469 *****************************************************************************/ 470 void gicv3_its_save_disable(uintptr_t gits_base, 471 gicv3_its_ctx_t * const its_ctx) 472 { 473 unsigned int i; 474 475 assert(gicv3_driver_data != NULL); 476 assert(IS_IN_EL3()); 477 assert(its_ctx != NULL); 478 assert(gits_base != 0U); 479 480 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 481 482 /* Disable the ITS */ 483 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 484 485 /* Wait for quiescent state */ 486 gits_wait_for_quiescent_bit(gits_base); 487 488 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 489 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 490 491 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 492 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 493 } 494 } 495 496 /***************************************************************************** 497 * Function to restore the GIC ITS register context. The power 498 * management of GIC ITS is implementation defined and this function doesn't 499 * restore any memory structures required to support ITS. The assumption is 500 * that these structures are in memory and are retained during system suspend. 501 * 502 * This must be invoked before the GIC CPU interface is enabled. 503 *****************************************************************************/ 504 void gicv3_its_restore(uintptr_t gits_base, 505 const gicv3_its_ctx_t * const its_ctx) 506 { 507 unsigned int i; 508 509 assert(gicv3_driver_data != NULL); 510 assert(IS_IN_EL3()); 511 assert(its_ctx != NULL); 512 assert(gits_base != 0U); 513 514 /* Assert that the GITS is disabled and quiescent */ 515 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 516 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U); 517 518 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 519 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 520 521 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 522 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 523 } 524 525 /* Restore the ITS CTLR but leave the ITS disabled */ 526 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 527 } 528 529 /***************************************************************************** 530 * Function to save the GIC Redistributor register context. This function 531 * must be invoked after CPU interface disable and prior to Distributor save. 532 *****************************************************************************/ 533 void gicv3_rdistif_save(unsigned int proc_num, 534 gicv3_redist_ctx_t * const rdist_ctx) 535 { 536 uintptr_t gicr_base; 537 unsigned int i, ppi_regs_num, regs_num; 538 539 assert(gicv3_driver_data != NULL); 540 assert(proc_num < gicv3_driver_data->rdistif_num); 541 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 542 assert(IS_IN_EL3()); 543 assert(rdist_ctx != NULL); 544 545 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 546 547 #if GIC_EXT_INTID 548 /* Calculate number of PPI registers */ 549 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 550 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 551 /* All other values except PPInum [0-2] are reserved */ 552 if (ppi_regs_num > 3U) { 553 ppi_regs_num = 1U; 554 } 555 #else 556 ppi_regs_num = 1U; 557 #endif 558 /* 559 * Wait for any write to GICR_CTLR to complete before trying to save any 560 * state. 561 */ 562 gicr_wait_for_pending_write(gicr_base); 563 564 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 565 566 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 567 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 568 569 /* 32 interrupt IDs per register */ 570 for (i = 0U; i < ppi_regs_num; ++i) { 571 SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 572 SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 573 SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 574 SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 575 SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 576 } 577 578 /* 16 interrupt IDs per GICR_ICFGR register */ 579 regs_num = ppi_regs_num << 1; 580 for (i = 0U; i < regs_num; ++i) { 581 SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 582 } 583 584 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 585 586 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 587 regs_num = ppi_regs_num << 3; 588 for (i = 0U; i < regs_num; ++i) { 589 SAVE_GICR_REG(gicr_base, rdist_ctx, ipriorityr, i); 590 } 591 592 /* 593 * Call the pre-save hook that implements the IMP DEF sequence that may 594 * be required on some GIC implementations. As this may need to access 595 * the Redistributor registers, we pass it proc_num. 596 */ 597 gicv3_distif_pre_save(proc_num); 598 } 599 600 /***************************************************************************** 601 * Function to restore the GIC Redistributor register context. We disable 602 * LPI and per-cpu interrupts before we start restore of the Redistributor. 603 * This function must be invoked after Distributor restore but prior to 604 * CPU interface enable. The pending and active interrupts are restored 605 * after the interrupts are fully configured and enabled. 606 *****************************************************************************/ 607 void gicv3_rdistif_init_restore(unsigned int proc_num, 608 const gicv3_redist_ctx_t * const rdist_ctx) 609 { 610 uintptr_t gicr_base; 611 unsigned int i, ppi_regs_num, regs_num; 612 613 assert(gicv3_driver_data != NULL); 614 assert(proc_num < gicv3_driver_data->rdistif_num); 615 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 616 assert(IS_IN_EL3()); 617 assert(rdist_ctx != NULL); 618 619 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 620 621 #if GIC_EXT_INTID 622 /* Calculate number of PPI registers */ 623 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 624 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 625 /* All other values except PPInum [0-2] are reserved */ 626 if (ppi_regs_num > 3U) { 627 ppi_regs_num = 1U; 628 } 629 #else 630 ppi_regs_num = 1U; 631 #endif 632 /* Power on redistributor */ 633 gicv3_rdistif_on(proc_num); 634 635 /* 636 * Call the post-restore hook that implements the IMP DEF sequence that 637 * may be required on some GIC implementations. As this may need to 638 * access the Redistributor registers, we pass it proc_num. 639 */ 640 gicv3_distif_post_restore(proc_num); 641 642 /* 643 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 644 * This is a more scalable approach as it avoids clearing the enable 645 * bits in the GICD_CTLR. 646 */ 647 for (i = 0U; i < ppi_regs_num; ++i) { 648 gicr_write_icenabler(gicr_base, i, ~0U); 649 } 650 651 /* Wait for pending writes to GICR_ICENABLER */ 652 gicr_wait_for_pending_write(gicr_base); 653 654 /* 655 * Disable the LPIs to avoid unpredictable behavior when writing to 656 * GICR_PROPBASER and GICR_PENDBASER. 657 */ 658 gicr_write_ctlr(gicr_base, 659 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 660 661 /* Restore registers' content */ 662 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 663 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 664 665 /* 32 interrupt IDs per register */ 666 for (i = 0U; i < ppi_regs_num; ++i) { 667 RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 668 RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 669 } 670 671 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 672 regs_num = ppi_regs_num << 3; 673 for (i = 0U; i < regs_num; ++i) { 674 RESTORE_GICR_REG(gicr_base, rdist_ctx, ipriorityr, i); 675 } 676 677 /* 16 interrupt IDs per GICR_ICFGR register */ 678 regs_num = ppi_regs_num << 1; 679 for (i = 0U; i < regs_num; ++i) { 680 RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 681 } 682 683 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 684 685 /* Restore after group and priorities are set. 686 * 32 interrupt IDs per register 687 */ 688 for (i = 0U; i < ppi_regs_num; ++i) { 689 RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 690 RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 691 } 692 693 /* 694 * Wait for all writes to the Distributor to complete before enabling 695 * the SGI and (E)PPIs. 696 */ 697 gicr_wait_for_upstream_pending_write(gicr_base); 698 699 /* 32 interrupt IDs per GICR_ISENABLER register */ 700 for (i = 0U; i < ppi_regs_num; ++i) { 701 RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 702 } 703 704 /* 705 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 706 * the first write to GICR_CTLR was still in flight (this write only 707 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 708 * bit). 709 */ 710 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 711 gicr_wait_for_pending_write(gicr_base); 712 } 713 714 /***************************************************************************** 715 * Function to save the GIC Distributor register context. This function 716 * must be invoked after CPU interface disable and Redistributor save. 717 *****************************************************************************/ 718 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 719 { 720 unsigned int typer_reg, num_ints; 721 #if GIC_EXT_INTID 722 unsigned int num_eints; 723 #endif 724 725 assert(gicv3_driver_data != NULL); 726 assert(gicv3_driver_data->gicd_base != 0U); 727 assert(IS_IN_EL3()); 728 assert(dist_ctx != NULL); 729 730 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 731 732 typer_reg = gicd_read_typer(gicd_base); 733 734 /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */ 735 num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 736 737 /* Filter out special INTIDs 1020-1023 */ 738 if (num_ints > (MAX_SPI_ID + 1U)) { 739 num_ints = MAX_SPI_ID + 1U; 740 } 741 742 #if GIC_EXT_INTID 743 /* Check if extended SPI range is implemented */ 744 if ((typer_reg & TYPER_ESPI) != 0U) { 745 /* 746 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095 747 */ 748 num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 749 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID - 1; 750 } else { 751 num_eints = 0U; 752 } 753 #endif 754 /* Wait for pending write to complete */ 755 gicd_wait_for_pending_write(gicd_base); 756 757 /* Save the GICD_CTLR */ 758 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 759 760 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */ 761 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 762 763 /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */ 764 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 765 766 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */ 767 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 768 769 /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 770 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 771 772 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */ 773 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 774 775 /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */ 776 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 777 778 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */ 779 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 780 781 /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 782 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 783 784 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */ 785 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 786 787 /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 788 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 789 790 /* Save GICD_ICFGR for INTIDs 32 - 1019 */ 791 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 792 793 /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */ 794 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 795 796 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */ 797 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 798 799 /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 800 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 801 802 /* Save GICD_NSACR for INTIDs 32 - 1019 */ 803 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 804 805 /* Save GICD_NSACRE for INTIDs 4096 - 5119 */ 806 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 807 808 /* Save GICD_IROUTER for INTIDs 32 - 1019 */ 809 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 810 811 /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */ 812 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 813 814 /* 815 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 816 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 817 * driver. 818 */ 819 } 820 821 /***************************************************************************** 822 * Function to restore the GIC Distributor register context. We disable G0, G1S 823 * and G1NS interrupt groups before we start restore of the Distributor. This 824 * function must be invoked prior to Redistributor restore and CPU interface 825 * enable. The pending and active interrupts are restored after the interrupts 826 * are fully configured and enabled. 827 *****************************************************************************/ 828 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 829 { 830 unsigned int typer_reg, num_ints; 831 #if GIC_EXT_INTID 832 unsigned int num_eints; 833 #endif 834 835 assert(gicv3_driver_data != NULL); 836 assert(gicv3_driver_data->gicd_base != 0U); 837 assert(IS_IN_EL3()); 838 assert(dist_ctx != NULL); 839 840 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 841 842 /* 843 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 844 * the ARE_S bit. The Distributor might generate a system error 845 * otherwise. 846 */ 847 gicd_clr_ctlr(gicd_base, 848 CTLR_ENABLE_G0_BIT | 849 CTLR_ENABLE_G1S_BIT | 850 CTLR_ENABLE_G1NS_BIT, 851 RWP_TRUE); 852 853 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 854 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 855 856 typer_reg = gicd_read_typer(gicd_base); 857 858 /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */ 859 num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 860 861 /* Filter out special INTIDs 1020-1023 */ 862 if (num_ints > (MAX_SPI_ID + 1U)) { 863 num_ints = MAX_SPI_ID + 1U; 864 } 865 866 #if GIC_EXT_INTID 867 /* Check if extended SPI range is implemented */ 868 if ((typer_reg & TYPER_ESPI) != 0U) { 869 /* 870 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095 871 */ 872 num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 873 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID - 1; 874 } else { 875 num_eints = 0U; 876 } 877 #endif 878 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */ 879 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 880 881 /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */ 882 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 883 884 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */ 885 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 886 887 /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 888 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 889 890 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */ 891 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 892 893 /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */ 894 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 895 896 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */ 897 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 898 899 /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 900 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 901 902 /* Restore GICD_NSACR for INTIDs 32 - 1019 */ 903 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 904 905 /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */ 906 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 907 908 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */ 909 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 910 911 /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */ 912 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 913 914 /* 915 * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after 916 * the interrupts are configured. 917 */ 918 919 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */ 920 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 921 922 /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 923 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 924 925 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */ 926 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 927 928 /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */ 929 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 930 931 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */ 932 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 933 934 /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 935 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 936 937 /* Restore the GICD_CTLR */ 938 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 939 gicd_wait_for_pending_write(gicd_base); 940 } 941 942 /******************************************************************************* 943 * This function gets the priority of the interrupt the processor is currently 944 * servicing. 945 ******************************************************************************/ 946 unsigned int gicv3_get_running_priority(void) 947 { 948 return (unsigned int)read_icc_rpr_el1(); 949 } 950 951 /******************************************************************************* 952 * This function checks if the interrupt identified by id is active (whether the 953 * state is either active, or active and pending). The proc_num is used if the 954 * interrupt is SGI or (E)PPI and programs the corresponding Redistributor 955 * interface. 956 ******************************************************************************/ 957 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 958 { 959 assert(gicv3_driver_data != NULL); 960 assert(gicv3_driver_data->gicd_base != 0U); 961 assert(proc_num < gicv3_driver_data->rdistif_num); 962 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 963 964 /* Check interrupt ID */ 965 if (is_sgi_ppi(id)) { 966 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 967 return gicr_get_isactiver( 968 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 969 } 970 971 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 972 return gicd_get_isactiver(gicv3_driver_data->gicd_base, id); 973 } 974 975 /******************************************************************************* 976 * This function enables the interrupt identified by id. The proc_num 977 * is used if the interrupt is SGI or PPI, and programs the corresponding 978 * Redistributor interface. 979 ******************************************************************************/ 980 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 981 { 982 assert(gicv3_driver_data != NULL); 983 assert(gicv3_driver_data->gicd_base != 0U); 984 assert(proc_num < gicv3_driver_data->rdistif_num); 985 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 986 987 /* 988 * Ensure that any shared variable updates depending on out of band 989 * interrupt trigger are observed before enabling interrupt. 990 */ 991 dsbishst(); 992 993 /* Check interrupt ID */ 994 if (is_sgi_ppi(id)) { 995 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 996 gicr_set_isenabler( 997 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 998 } else { 999 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1000 gicd_set_isenabler(gicv3_driver_data->gicd_base, id); 1001 } 1002 } 1003 1004 /******************************************************************************* 1005 * This function disables the interrupt identified by id. The proc_num 1006 * is used if the interrupt is SGI or PPI, and programs the corresponding 1007 * Redistributor interface. 1008 ******************************************************************************/ 1009 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 1010 { 1011 assert(gicv3_driver_data != NULL); 1012 assert(gicv3_driver_data->gicd_base != 0U); 1013 assert(proc_num < gicv3_driver_data->rdistif_num); 1014 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1015 1016 /* 1017 * Disable interrupt, and ensure that any shared variable updates 1018 * depending on out of band interrupt trigger are observed afterwards. 1019 */ 1020 1021 /* Check interrupt ID */ 1022 if (is_sgi_ppi(id)) { 1023 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1024 gicr_set_icenabler( 1025 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1026 1027 /* Write to clear enable requires waiting for pending writes */ 1028 gicr_wait_for_pending_write( 1029 gicv3_driver_data->rdistif_base_addrs[proc_num]); 1030 } else { 1031 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1032 gicd_set_icenabler(gicv3_driver_data->gicd_base, id); 1033 1034 /* Write to clear enable requires waiting for pending writes */ 1035 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base); 1036 } 1037 1038 dsbishst(); 1039 } 1040 1041 /******************************************************************************* 1042 * This function sets the interrupt priority as supplied for the given interrupt 1043 * id. 1044 ******************************************************************************/ 1045 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 1046 unsigned int priority) 1047 { 1048 uintptr_t gicr_base; 1049 1050 assert(gicv3_driver_data != NULL); 1051 assert(gicv3_driver_data->gicd_base != 0U); 1052 assert(proc_num < gicv3_driver_data->rdistif_num); 1053 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1054 1055 /* Check interrupt ID */ 1056 if (is_sgi_ppi(id)) { 1057 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1058 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1059 gicr_set_ipriorityr(gicr_base, id, priority); 1060 } else { 1061 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1062 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority); 1063 } 1064 } 1065 1066 /******************************************************************************* 1067 * This function assigns group for the interrupt identified by id. The proc_num 1068 * is used if the interrupt is SGI or (E)PPI, and programs the corresponding 1069 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 1070 ******************************************************************************/ 1071 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 1072 unsigned int type) 1073 { 1074 bool igroup = false, grpmod = false; 1075 uintptr_t gicr_base; 1076 1077 assert(gicv3_driver_data != NULL); 1078 assert(gicv3_driver_data->gicd_base != 0U); 1079 assert(proc_num < gicv3_driver_data->rdistif_num); 1080 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1081 1082 switch (type) { 1083 case INTR_GROUP1S: 1084 igroup = false; 1085 grpmod = true; 1086 break; 1087 case INTR_GROUP0: 1088 igroup = false; 1089 grpmod = false; 1090 break; 1091 case INTR_GROUP1NS: 1092 igroup = true; 1093 grpmod = false; 1094 break; 1095 default: 1096 assert(false); 1097 break; 1098 } 1099 1100 /* Check interrupt ID */ 1101 if (is_sgi_ppi(id)) { 1102 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1103 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1104 1105 igroup ? gicr_set_igroupr(gicr_base, id) : 1106 gicr_clr_igroupr(gicr_base, id); 1107 grpmod ? gicr_set_igrpmodr(gicr_base, id) : 1108 gicr_clr_igrpmodr(gicr_base, id); 1109 } else { 1110 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1111 1112 /* Serialize read-modify-write to Distributor registers */ 1113 spin_lock(&gic_lock); 1114 1115 igroup ? gicd_set_igroupr(gicv3_driver_data->gicd_base, id) : 1116 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id); 1117 grpmod ? gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id) : 1118 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id); 1119 1120 spin_unlock(&gic_lock); 1121 } 1122 } 1123 1124 /******************************************************************************* 1125 * This function raises the specified Secure Group 0 SGI. 1126 * 1127 * The target parameter must be a valid MPIDR in the system. 1128 ******************************************************************************/ 1129 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target) 1130 { 1131 unsigned int tgt, aff3, aff2, aff1, aff0; 1132 uint64_t sgi_val; 1133 1134 /* Verify interrupt number is in the SGI range */ 1135 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 1136 1137 /* Extract affinity fields from target */ 1138 aff0 = MPIDR_AFFLVL0_VAL(target); 1139 aff1 = MPIDR_AFFLVL1_VAL(target); 1140 aff2 = MPIDR_AFFLVL2_VAL(target); 1141 aff3 = MPIDR_AFFLVL3_VAL(target); 1142 1143 /* 1144 * Make target list from affinity 0, and ensure GICv3 SGI can target 1145 * this PE. 1146 */ 1147 assert(aff0 < GICV3_MAX_SGI_TARGETS); 1148 tgt = BIT_32(aff0); 1149 1150 /* Raise SGI to PE specified by its affinity */ 1151 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 1152 tgt); 1153 1154 /* 1155 * Ensure that any shared variable updates depending on out of band 1156 * interrupt trigger are observed before raising SGI. 1157 */ 1158 dsbishst(); 1159 write_icc_sgi0r_el1(sgi_val); 1160 isb(); 1161 } 1162 1163 /******************************************************************************* 1164 * This function sets the interrupt routing for the given (E)SPI interrupt id. 1165 * The interrupt routing is specified in routing mode and mpidr. 1166 * 1167 * The routing mode can be either of: 1168 * - GICV3_IRM_ANY 1169 * - GICV3_IRM_PE 1170 * 1171 * The mpidr is the affinity of the PE to which the interrupt will be routed, 1172 * and is ignored for routing mode GICV3_IRM_ANY. 1173 ******************************************************************************/ 1174 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 1175 { 1176 unsigned long long aff; 1177 uint64_t router; 1178 1179 assert(gicv3_driver_data != NULL); 1180 assert(gicv3_driver_data->gicd_base != 0U); 1181 1182 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 1183 1184 assert(IS_SPI(id)); 1185 1186 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 1187 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff); 1188 1189 /* 1190 * In implementations that do not require 1 of N distribution of SPIs, 1191 * IRM might be RAZ/WI. Read back and verify IRM bit. 1192 */ 1193 if (irm == GICV3_IRM_ANY) { 1194 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id); 1195 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) { 1196 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1197 panic(); 1198 } 1199 } 1200 } 1201 1202 /******************************************************************************* 1203 * This function clears the pending status of an interrupt identified by id. 1204 * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the 1205 * corresponding Redistributor interface. 1206 ******************************************************************************/ 1207 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1208 { 1209 assert(gicv3_driver_data != NULL); 1210 assert(gicv3_driver_data->gicd_base != 0U); 1211 assert(proc_num < gicv3_driver_data->rdistif_num); 1212 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1213 1214 /* 1215 * Clear pending interrupt, and ensure that any shared variable updates 1216 * depending on out of band interrupt trigger are observed afterwards. 1217 */ 1218 1219 /* Check interrupt ID */ 1220 if (is_sgi_ppi(id)) { 1221 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1222 gicr_set_icpendr( 1223 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1224 } else { 1225 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1226 gicd_set_icpendr(gicv3_driver_data->gicd_base, id); 1227 } 1228 1229 dsbishst(); 1230 } 1231 1232 /******************************************************************************* 1233 * This function sets the pending status of an interrupt identified by id. 1234 * The proc_num is used if the interrupt is SGI or PPI and programs the 1235 * corresponding Redistributor interface. 1236 ******************************************************************************/ 1237 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1238 { 1239 assert(gicv3_driver_data != NULL); 1240 assert(gicv3_driver_data->gicd_base != 0U); 1241 assert(proc_num < gicv3_driver_data->rdistif_num); 1242 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1243 1244 /* 1245 * Ensure that any shared variable updates depending on out of band 1246 * interrupt trigger are observed before setting interrupt pending. 1247 */ 1248 dsbishst(); 1249 1250 /* Check interrupt ID */ 1251 if (is_sgi_ppi(id)) { 1252 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1253 gicr_set_ispendr( 1254 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1255 } else { 1256 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1257 gicd_set_ispendr(gicv3_driver_data->gicd_base, id); 1258 } 1259 } 1260 1261 /******************************************************************************* 1262 * This function sets the PMR register with the supplied value. Returns the 1263 * original PMR. 1264 ******************************************************************************/ 1265 unsigned int gicv3_set_pmr(unsigned int mask) 1266 { 1267 unsigned int old_mask; 1268 1269 old_mask = (unsigned int)read_icc_pmr_el1(); 1270 1271 /* 1272 * Order memory updates w.r.t. PMR write, and ensure they're visible 1273 * before potential out of band interrupt trigger because of PMR update. 1274 * PMR system register writes are self-synchronizing, so no ISB required 1275 * thereafter. 1276 */ 1277 dsbishst(); 1278 write_icc_pmr_el1(mask); 1279 1280 return old_mask; 1281 } 1282 1283 /******************************************************************************* 1284 * This function delegates the responsibility of discovering the corresponding 1285 * Redistributor frames to each CPU itself. It is a modified version of 1286 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform 1287 * unlike the previous way in which only the Primary CPU did the discovery of 1288 * all the Redistributor frames for every CPU. It also handles the scenario in 1289 * which the frames of various CPUs are not contiguous in physical memory. 1290 ******************************************************************************/ 1291 int gicv3_rdistif_probe(const uintptr_t gicr_frame) 1292 { 1293 u_register_t mpidr; 1294 unsigned int proc_num, proc_self; 1295 uint64_t typer_val; 1296 uintptr_t rdistif_base; 1297 bool gicr_frame_found = false; 1298 1299 assert(gicv3_driver_data->gicr_base == 0U); 1300 1301 /* Ensure this function is called with Data Cache enabled */ 1302 #ifndef __aarch64__ 1303 assert((read_sctlr() & SCTLR_C_BIT) != 0U); 1304 #else 1305 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U); 1306 #endif /* !__aarch64__ */ 1307 1308 proc_self = gicv3_driver_data->mpidr_to_core_pos(read_mpidr_el1()); 1309 rdistif_base = gicr_frame; 1310 do { 1311 typer_val = gicr_read_typer(rdistif_base); 1312 if (gicv3_driver_data->mpidr_to_core_pos != NULL) { 1313 mpidr = mpidr_from_gicr_typer(typer_val); 1314 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr); 1315 } else { 1316 proc_num = (unsigned int)(typer_val >> 1317 TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK; 1318 } 1319 if (proc_num == proc_self) { 1320 /* The base address doesn't need to be initialized on 1321 * every warm boot. 1322 */ 1323 if (gicv3_driver_data->rdistif_base_addrs[proc_num] 1324 != 0U) { 1325 return 0; 1326 } 1327 gicv3_driver_data->rdistif_base_addrs[proc_num] = 1328 rdistif_base; 1329 gicr_frame_found = true; 1330 break; 1331 } 1332 rdistif_base += (uintptr_t)(ULL(1) << GICR_PCPUBASE_SHIFT); 1333 } while ((typer_val & TYPER_LAST_BIT) == 0U); 1334 1335 if (!gicr_frame_found) { 1336 return -1; 1337 } 1338 1339 /* 1340 * Flush the driver data to ensure coherency. This is 1341 * not required if platform has HW_ASSISTED_COHERENCY 1342 * enabled. 1343 */ 1344 #if !HW_ASSISTED_COHERENCY 1345 /* 1346 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 1347 */ 1348 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]), 1349 sizeof(*(gicv3_driver_data->rdistif_base_addrs))); 1350 #endif 1351 return 0; /* Found matching GICR frame */ 1352 } 1353 1354 /****************************************************************************** 1355 * This function checks the interrupt ID and returns true for SGIs and (E)PPIs 1356 * and false for (E)SPIs IDs. 1357 *****************************************************************************/ 1358 static bool is_sgi_ppi(unsigned int id) 1359 { 1360 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 1361 if (IS_SGI_PPI(id)) { 1362 return true; 1363 } 1364 1365 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 1366 if (IS_SPI(id)) { 1367 return false; 1368 } 1369 1370 assert(false); 1371 panic(); 1372 } 1373