| 9def1fb7 | 13-Nov-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_gpio: update and fix RIF configuration handling
The conditions to acquire or release RIF semaphores when applying the CID filtering configuration were incorrect. Add handle_available_
drivers: stm32_gpio: update and fix RIF configuration handling
The conditions to acquire or release RIF semaphores when applying the CID filtering configuration were incorrect. Add handle_available_semaphores() to handle correctly the RIF semaphores. Also remove FMC_NB_MAX_CID_SUPPORTED and use generic MAX_CID_SUPPORTED.
Also add a dummy apply_rif_config() when CFG_STM32_RIF is not defined.
Fix unfreed banks when they are removed from the bank list.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Fixes: bd03c8c3d70f ("drivers: stm32_gpio: add stm32mp25x support")
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| bc9c7c89 | 14-Nov-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_hsem: fix HSEM group CID filtering configuration
Move the check on HSEM group CID filtering configuration consistency before the continuing if the CID filtering is disabled for the fi
drivers: stm32_hsem: fix HSEM group CID filtering configuration
Move the check on HSEM group CID filtering configuration consistency before the continuing if the CID filtering is disabled for the first semaphore of the group.
The HSEM group CID filtering was also broken as it didn't allow more than one CID to access a semaphore group. Fix this by using the semaphore bit-field in the RIFPROT macro to determine what are the processors that should be authorized to take the semaphores.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Fixes: ec9aa1a4114f ("drivers: add RIF support driver for HSEM")
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| 19c6bd04 | 13-Nov-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_hsem: fix unfreed memory
Free hsem_d if parse_dt() fails.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com
drivers: stm32_hsem: fix unfreed memory
Free hsem_d if parse_dt() fails.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Fixes: ec9aa1a4114f ("drivers: add RIF support driver for HSEM")
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| 2a844736 | 13-Nov-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_ipcc: update and fix RIF configuration
Rework the RIF configuration application to apply privilege and secure level configuration only when CID filtering permits it. Also remove unuse
drivers: stm32_ipcc: update and fix RIF configuration
Rework the RIF configuration application to apply privilege and secure level configuration only when CID filtering permits it. Also remove unused IPCC_NB_MAX_CID_SUPPORTED and put the tdcid state in the ipcc_pdata to simplify the driver.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Fixes: e26b8e0f3e4c ("drivers: add IPCC driver and its RIF support")
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| ce5fe041 | 13-Nov-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_ipcc: do not make RIF configuration mandatory
It should not be mandatory to apply a RIF configuration for an IPCC. Remove this constraint by allocating a RIF configuration structure o
drivers: stm32_ipcc: do not make RIF configuration mandatory
It should not be mandatory to apply a RIF configuration for an IPCC. Remove this constraint by allocating a RIF configuration structure only when the "st,protreg" property is present in the device tree to be able to check if it has been allocated later.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 90df040b | 15-Nov-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_fmc: fix check_fmc_rif_conf() and its use
Fix check_fmc_rif_conf() so that it correctly returns with success upon controller 0 being secure. Fix the assert by inverting the logic.
Si
drivers: stm32_fmc: fix check_fmc_rif_conf() and its use
Fix check_fmc_rif_conf() so that it correctly returns with success upon controller 0 being secure. Fix the assert by inverting the logic.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Fixes: 778a36bf91d2 ("drivers: add FMC driver with RIF support")
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| 6e15f946 | 14-Nov-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_fmc: use PM_HINT_IS_STATE macro in pm callbacks
Use dedicated PM_HINT_IS_STATE macro in pm callbacks to determine the targeted pm state.
Signed-off-by: Gatien Chevallier <gatien.chev
drivers: stm32_fmc: use PM_HINT_IS_STATE macro in pm callbacks
Use dedicated PM_HINT_IS_STATE macro in pm callbacks to determine the targeted pm state.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 5da989f3 | 13-Nov-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_fmc: update and fix CID filtering configuration
The conditions to acquire or release RIF semaphores when applying the CID filtering configuration were incorrect. Add handle_available_
drivers: stm32_fmc: update and fix CID filtering configuration
The conditions to acquire or release RIF semaphores when applying the CID filtering configuration were incorrect. Add handle_available_semaphores() to handle correctly the RIF semaphores. Also remove FMC_NB_MAX_CID_SUPPORTED and use generic MAX_CID_SUPPORTED.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Fixes: 778a36bf91d2 ("drivers: add FMC driver with RIF support")
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| b573873c | 14-Nov-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_fmc: do not make RIF configuration mandatory
It should not be mandatory to apply a RIF configuration for a FMC. Remove this constraint by allocating a RIF configuration structure only
drivers: stm32_fmc: do not make RIF configuration mandatory
It should not be mandatory to apply a RIF configuration for a FMC. Remove this constraint by allocating a RIF configuration structure only when the "st,protreg" property is present in the device tree to be able to check if it has been allocated later.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 5c2c026a | 13-Nov-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_hpdma: update and fix CID filtering configuration
The conditions to acquire or release RIF semaphores when applying the CID filtering configuration were incorrect. Add handle_availabl
drivers: stm32_hpdma: update and fix CID filtering configuration
The conditions to acquire or release RIF semaphores when applying the CID filtering configuration were incorrect. Add handle_available_semaphores() to handle correctly the RIF semaphores.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Fixes: 0cf1cd13ceb6 ("drivers: add HPDMA driver with RIF support")
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| 307d268b | 13-Nov-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_hpdma: do not make RIF configuration mandatory
It should not be mandatory to apply a RIF configuration for a HPDMA. Remove this constraint by allocating a RIF configuration structure
drivers: stm32_hpdma: do not make RIF configuration mandatory
It should not be mandatory to apply a RIF configuration for a HPDMA. Remove this constraint by allocating a RIF configuration structure only when the "st,protreg" property is present in the device tree to be able to check if it has been allocated later.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 646ad62b | 13-Nov-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_rif: update and fix RIF configuration parsing
Fix the parsing of the RIF configuration by using device tree bindings, when necessary. Generalize RIF bit fields and use them when deali
drivers: stm32_rif: update and fix RIF configuration parsing
Fix the parsing of the RIF configuration by using device tree bindings, when necessary. Generalize RIF bit fields and use them when dealing with generic RIF functions. Update drivers that use stm32_rif_parse_cfg() accordingly.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Fixes: 1506f47af917 ("drivers: firewall: add stm32_rif driver for common RIF features")
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| 6b1b2b99 | 29-Oct-2024 |
Yitong Cheng <santongding@foxmail.com> |
core: thread: clarify thread_rpc_alloc_*_payload() inline description
The thread_rpc_alloc_*_payload APIs are consistent with the thread_shm_type enumerations, as seen in the alloc_shm function. How
core: thread: clarify thread_rpc_alloc_*_payload() inline description
The thread_rpc_alloc_*_payload APIs are consistent with the thread_shm_type enumerations, as seen in the alloc_shm function. However, the name and comments of thread_rpc_alloc_payload might be misleading, suggesting it is a universal API. To maintain backward compatibility, only the code comments have been updated for clarity.
Signed-off-by: Yitong Cheng <santongding@foxmail.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 116d03ab | 04-Nov-2024 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
drivers: caam: cache align Key blob modifier
An array was used as Key blob modifier, changed it cache aligned dynamic memory.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com> Acked-by: Jens W
drivers: caam: cache align Key blob modifier
An array was used as Key blob modifier, changed it cache aligned dynamic memory.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 132151fb | 10-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: use firewall framework to configure internal RAMs
Use firewall API functions in stm32mp1 platform implementation to configure the secure state of internal RAMs.
This change is a step
plat-stm32mp1: use firewall framework to configure internal RAMs
Use firewall API functions in stm32mp1 platform implementation to configure the secure state of internal RAMs.
This change is a step in the removal of the shared_resource driver that will be deprecated once the stm32mp1 platform drivers fully move to the firewall framework resources.
This change also removes local SCMI_SHM_IS_IN_SRAMX macro (for sake of simplicity) which can be replaced by testing CFG_STM32MP1_SCMI_SHM_BASE!=0 that denotes that the SCMI shared memory is not in an internal RAM in the platform configuration.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| f117e429 | 30-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: firewall: stm32_etzpc: add memory configuration firewall API
Implement the .set_memory_conf() firewall ops that allows to reconfigure memory regions managed by the platform ETZPC firewall c
drivers: firewall: stm32_etzpc: add memory configuration firewall API
Implement the .set_memory_conf() firewall ops that allows to reconfigure memory regions managed by the platform ETZPC firewall controller.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| b114c4af | 30-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: define STM32MP13 SRAMs and STM32MP15 RETRAM
Define some platform internal RAMs base address and sizes for STM32MP13 and STM32MP15 SoCs.
Signed-off-by: Etienne Carriere <etienne.carri
plat-stm32mp1: define STM32MP13 SRAMs and STM32MP15 RETRAM
Define some platform internal RAMs base address and sizes for STM32MP13 and STM32MP15 SoCs.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| d6b3f5f4 | 13-Jun-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
core: firewall: add memory range firewall controller ops
Add a firewall driver operation handle and a firewall framework API function to configure memory access rights, base on physical address rang
core: firewall: add memory range firewall controller ops
Add a firewall driver operation handle and a firewall framework API function to configure memory access rights, base on physical address range arguments.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| bea4f8d3 | 10-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: firewall: stm32_etzpc: allow valid locked configuration
Change stm32_etzpc driver to not trigger an error when the requested firewall configuration matches an already configured and locked
drivers: firewall: stm32_etzpc: allow valid locked configuration
Change stm32_etzpc driver to not trigger an error when the requested firewall configuration matches an already configured and locked configuration.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| f74d3fff | 10-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: firewall: stm32_etzpc: pager SRAMs must be secure
STM32MP15 SRAMs used by pager can only be configured as secure access only.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
drivers: firewall: stm32_etzpc: pager SRAMs must be secure
STM32MP15 SRAMs used by pager can only be configured as secure access only.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| beedc460 | 10-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: remoteproc: stm32_remoteproc: Don't use SRAMs used by pager
Forbid stm32_remoteproc driver to use SRAMx that are used by OP-TEE pager.
Signed-off-by: Etienne Carriere <etienne.carriere@fos
drivers: remoteproc: stm32_remoteproc: Don't use SRAMs used by pager
Forbid stm32_remoteproc driver to use SRAMx that are used by OP-TEE pager.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| a0cac862 | 10-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: add stm32mp1_ram_intersect_pager_ram()
Add stm32mp1_ram_intersect_pager_ram() helper function to ease checking when a memory range falls into OP-TEE pager pool. This will be needed la
plat-stm32mp1: add stm32mp1_ram_intersect_pager_ram()
Add stm32mp1_ram_intersect_pager_ram() helper function to ease checking when a memory range falls into OP-TEE pager pool. This will be needed later to ensure memory used by OP-TEE pager is not re-assigned to another purpose. This change only consider STM32MP15 variant where OP-TEE pager can be used in internal RAMs.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 2714147b | 10-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: add stm32mp1_pa_or_sram_alias_pa()
Add stm32mp1_pa_or_sram_alias_pa() helper function to ease handling SRAMx physical addresses that have aliases on STM32MP15 SoC.
Signed-off-by: Eti
plat-stm32mp1: add stm32mp1_pa_or_sram_alias_pa()
Add stm32mp1_pa_or_sram_alias_pa() helper function to ease handling SRAMx physical addresses that have aliases on STM32MP15 SoC.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 1bbb4042 | 30-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: firewall: stm32_etzpc: fix DECPROT values
Correct sanitize_decprot_config() implementation: label values to enumerated type etzpc_decprot_attributes are prefixed ETZPC_.
Fixes: 9c22da4b29d
drivers: firewall: stm32_etzpc: fix DECPROT values
Correct sanitize_decprot_config() implementation: label values to enumerated type etzpc_decprot_attributes are prefixed ETZPC_.
Fixes: 9c22da4b29de ("firewall: stm32_etzpc: check consistency of RCC vs DECPROT secure config") Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 41f3fcbb | 12-Nov-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: firewall: stm32_etzpc: print DECPROT values as strings
Print ETZPC attribute strings instead of numerical value in trace messages.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st
drivers: firewall: stm32_etzpc: print DECPROT values as strings
Print ETZPC attribute strings instead of numerical value in trace messages.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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