1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2024, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <compiler.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/firewall.h> 13 #include <drivers/gpio.h> 14 #include <drivers/pinctrl.h> 15 #include <drivers/stm32_gpio.h> 16 #include <drivers/stm32_rif.h> 17 #include <dt-bindings/gpio/stm32mp_gpio.h> 18 #include <dt-bindings/pinctrl/stm32-pinfunc.h> 19 #include <io.h> 20 #include <kernel/dt.h> 21 #include <kernel/boot.h> 22 #include <kernel/panic.h> 23 #include <kernel/pm.h> 24 #include <kernel/spinlock.h> 25 #include <libfdt.h> 26 #include <mm/core_memprot.h> 27 #include <stdbool.h> 28 #include <stdint.h> 29 #include <stm32_util.h> 30 #include <sys/queue.h> 31 #include <trace.h> 32 #include <util.h> 33 34 #ifndef CFG_DRIVERS_GPIO 35 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 36 #endif 37 38 #define GPIO_PIN_MAX 15 39 40 #define GPIO_MODER_OFFSET U(0x00) 41 #define GPIO_OTYPER_OFFSET U(0x04) 42 #define GPIO_OSPEEDR_OFFSET U(0x08) 43 #define GPIO_PUPDR_OFFSET U(0x0c) 44 #define GPIO_IDR_OFFSET U(0x10) 45 #define GPIO_ODR_OFFSET U(0x14) 46 #define GPIO_BSRR_OFFSET U(0x18) 47 #define GPIO_AFRL_OFFSET U(0x20) 48 #define GPIO_AFRH_OFFSET U(0x24) 49 #define GPIO_SECR_OFFSET U(0x30) 50 #define GPIO_PRIVCFGR_OFFSET U(0x34) 51 #define GPIO_RCFGLOCKR_OFFSET U(0x38) 52 #define GPIO_CIDCFGR(x) (U(0x50) + U(0x8) * (x)) 53 #define GPIO_SEMCR(x) (U(0x54) + U(0x8) * (x)) 54 55 #define GPIO_ALT_LOWER_LIMIT U(0x8) 56 57 /* 58 * CIDCFGR register bitfields 59 */ 60 #define GPIO_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16) 61 #define GPIO_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 62 #define GPIO_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | _CIDCFGR_SEMEN | \ 63 GPIO_CIDCFGR_SCID_MASK | \ 64 GPIO_CIDCFGR_SEMWL_MASK) 65 66 /* 67 * PRIVCFGR register bitfields 68 */ 69 #define GPIO_PRIVCFGR_MASK GENMASK_32(15, 0) 70 71 /* 72 * SECCFGR register bitfields 73 */ 74 #define GPIO_SECCFGR_MASK GENMASK_32(15, 0) 75 76 /* 77 * RCFGLOCKR register bitfields 78 */ 79 #define GPIO_RCFGLOCKR_MASK GENMASK_32(15, 0) 80 81 /* 82 * SEMCR register bitfields 83 */ 84 #define GPIO_SEMCR_SCID_M GENMASK_32(6, 4) 85 86 #define GPIO_MODE_MASK GENMASK_32(1, 0) 87 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 88 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 89 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 90 91 #define DT_GPIO_BANK_SHIFT U(12) 92 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 93 #define DT_GPIO_PIN_SHIFT U(8) 94 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 95 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 96 97 #define DT_GPIO_BANK_NAME0 "GPIOA" 98 99 #define GPIO_MODE_INPUT U(0x0) 100 #define GPIO_MODE_OUTPUT U(0x1) 101 #define GPIO_MODE_ALTERNATE U(0x2) 102 #define GPIO_MODE_ANALOG U(0x3) 103 104 #define GPIO_OTYPE_PUSH_PULL U(0x0) 105 #define GPIO_OTYPE_OPEN_DRAIN U(0x1) 106 107 #define GPIO_OSPEED_LOW U(0x0) 108 #define GPIO_OSPEED_MEDIUM U(0x1) 109 #define GPIO_OSPEED_HIGH U(0x2) 110 #define GPIO_OSPEED_VERY_HIGH U(0x3) 111 112 #define GPIO_PUPD_NO_PULL U(0x0) 113 #define GPIO_PUPD_PULL_UP U(0x1) 114 #define GPIO_PUPD_PULL_DOWN U(0x2) 115 116 #define GPIO_OD_LEVEL_LOW U(0x0) 117 #define GPIO_OD_LEVEL_HIGH U(0x1) 118 119 #define GPIO_MAX_CID_SUPPORTED U(3) 120 121 /* 122 * GPIO configuration description structured as single 16bit word 123 * for efficient save/restore when GPIO pin suspends or resumes. 124 * 125 * @mode: One of GPIO_MODE_* 126 * @otype: One of GPIO_OTYPE_* 127 * @ospeed: One of GPIO_OSPEED_* 128 * @pupd: One of GPIO_PUPD_* 129 * @od: One of GPIO_OD_* 130 * @af: Alternate function numerical ID between 0 and 15 131 * @nsec: Hint on expected secure state of the pin: 0 if secure, 1 otherwise 132 */ 133 struct gpio_cfg { 134 uint16_t mode: 2; 135 uint16_t otype: 1; 136 uint16_t ospeed: 2; 137 uint16_t pupd: 2; 138 uint16_t od: 1; 139 uint16_t af: 4; 140 uint16_t nsec: 1; 141 }; 142 143 /* 144 * Description of a pin and its muxing 145 * 146 * @bank: GPIO bank identifier as assigned by the platform 147 * @pin: Pin number in the GPIO bank 148 * @cfg: Pin configuration 149 */ 150 struct stm32_pinctrl { 151 uint8_t bank; 152 uint8_t pin; 153 struct gpio_cfg cfg; 154 }; 155 156 /* 157 * struct stm32_pinctrl_array - Array of pins in a pin control state 158 * @count: Number of cells in @pinctrl 159 * @pinctrl: Pin control configuration 160 */ 161 struct stm32_pinctrl_array { 162 size_t count; 163 struct stm32_pinctrl pinctrl[]; 164 }; 165 166 /** 167 * struct stm32_gpio_bank - GPIO bank instance 168 * 169 * @base: base address of the GPIO controller registers. 170 * @clock: clock identifier. 171 * @gpio_chip: GPIO chip reference for that GPIO bank 172 * @ngpios: number of GPIOs. 173 * @bank_id: Id of the bank. 174 * @lock: lock protecting the GPIO bank access. 175 * @rif_cfg: RIF configuration data 176 * @seccfgr: non-RIF bank secure configuration data 177 * @sec_support: True if bank supports pin security protection, else false 178 * @ready: True if configuration is applied, else false 179 * @is_tdcid: True if OP-TEE runs as Trusted Domain CID 180 * @link: Link in bank list 181 */ 182 struct stm32_gpio_bank { 183 vaddr_t base; 184 struct clk *clock; 185 struct gpio_chip gpio_chip; 186 unsigned int ngpios; 187 unsigned int bank_id; 188 unsigned int lock; 189 struct rif_conf_data *rif_cfg; 190 uint32_t seccfgr; 191 bool sec_support; 192 bool ready; 193 bool is_tdcid; 194 STAILQ_ENTRY(stm32_gpio_bank) link; 195 }; 196 197 /* 198 * struct stm32_gpio_pm_state - Consumed GPIO for PM purpose 199 * @gpio_pinctrl: Reference and configuration state for a consumed GPIO 200 * @level: GPIO level 201 * @link: Link in consumed GPIO list 202 */ 203 struct stm32_gpio_pm_state { 204 struct stm32_pinctrl gpio_pinctrl; 205 uint8_t level; 206 SLIST_ENTRY(stm32_gpio_pm_state) link; 207 }; 208 209 /** 210 * Compatibility information of supported banks 211 * 212 * @gpioz: True if bank is a GPIOZ bank 213 * @secure_control: Identify GPIO security bank capability. 214 * @secure_extended: Identify RIF presence. 215 */ 216 struct bank_compat { 217 bool gpioz; 218 bool secure_control; 219 bool secure_extended; 220 }; 221 222 static unsigned int gpio_lock; 223 224 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 225 STAILQ_HEAD_INITIALIZER(bank_list); 226 227 static SLIST_HEAD(, stm32_gpio_pm_state) consumed_gpios_head; 228 229 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 230 231 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 232 { 233 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 234 } 235 236 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 237 unsigned int gpio_pin) 238 { 239 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 240 enum gpio_level level = GPIO_LEVEL_HIGH; 241 unsigned int reg_offset = 0; 242 unsigned int mode = 0; 243 244 assert(gpio_pin < bank->ngpios); 245 246 if (clk_enable(bank->clock)) 247 panic(); 248 249 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 250 GPIO_MODE_MASK; 251 252 switch (mode) { 253 case GPIO_MODE_INPUT: 254 reg_offset = GPIO_IDR_OFFSET; 255 break; 256 case GPIO_MODE_OUTPUT: 257 reg_offset = GPIO_ODR_OFFSET; 258 break; 259 default: 260 panic(); 261 } 262 263 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 264 level = GPIO_LEVEL_HIGH; 265 else 266 level = GPIO_LEVEL_LOW; 267 268 clk_disable(bank->clock); 269 270 return level; 271 } 272 273 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 274 enum gpio_level level) 275 { 276 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 277 278 assert(gpio_pin < bank->ngpios); 279 280 if (clk_enable(bank->clock)) 281 panic(); 282 283 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 284 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 285 286 if (level == GPIO_LEVEL_HIGH) 287 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 288 else 289 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 290 291 clk_disable(bank->clock); 292 } 293 294 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 295 unsigned int gpio_pin) 296 { 297 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 298 uint32_t mode = 0; 299 300 assert(gpio_pin < bank->ngpios); 301 302 if (clk_enable(bank->clock)) 303 panic(); 304 305 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 306 GPIO_MODE_MASK; 307 308 clk_disable(bank->clock); 309 310 switch (mode) { 311 case GPIO_MODE_INPUT: 312 return GPIO_DIR_IN; 313 case GPIO_MODE_OUTPUT: 314 return GPIO_DIR_OUT; 315 default: 316 panic(); 317 } 318 } 319 320 static void stm32_gpio_set_direction(struct gpio_chip *chip, 321 unsigned int gpio_pin, 322 enum gpio_dir direction) 323 { 324 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 325 uint32_t exceptions = 0; 326 uint32_t mode = 0; 327 328 assert(gpio_pin < bank->ngpios); 329 330 if (direction == GPIO_DIR_IN) 331 mode = GPIO_MODE_INPUT; 332 else 333 mode = GPIO_MODE_OUTPUT; 334 335 if (clk_enable(bank->clock)) 336 panic(); 337 exceptions = cpu_spin_lock_xsave(&gpio_lock); 338 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 339 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 340 SHIFT_U32(mode, gpio_pin << 1)); 341 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 342 clk_disable(bank->clock); 343 } 344 345 /* Forward reference to the PM callback handler for consumed GPIOs */ 346 static TEE_Result consumed_gpios_pm(enum pm_op op, unsigned int pm_hint, 347 const struct pm_callback_handle *pm_hdl); 348 349 /* Forward reference to RIF semaphore release helper function */ 350 static void release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank, 351 unsigned int pin); 352 353 static void stm32_gpio_put_gpio(struct gpio_chip *chip, struct gpio *gpio) 354 { 355 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 356 struct stm32_gpio_pm_state *tstate = NULL; 357 struct stm32_gpio_pm_state *state = NULL; 358 uint32_t exceptions = 0; 359 360 assert(is_stm32_gpio_chip(chip)); 361 362 exceptions = cpu_spin_lock_xsave(&gpio_lock); 363 364 SLIST_FOREACH_SAFE(state, &consumed_gpios_head, link, tstate) { 365 if (state->gpio_pinctrl.bank == bank->bank_id && 366 state->gpio_pinctrl.pin == gpio->pin) { 367 SLIST_REMOVE(&consumed_gpios_head, state, 368 stm32_gpio_pm_state, link); 369 unregister_pm_driver_cb(consumed_gpios_pm, state); 370 release_rif_semaphore_if_acquired(bank, gpio->pin); 371 free(state); 372 free(gpio); 373 break; 374 } 375 } 376 assert(state); 377 378 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 379 } 380 381 static const struct gpio_ops stm32_gpio_ops = { 382 .get_direction = stm32_gpio_get_direction, 383 .set_direction = stm32_gpio_set_direction, 384 .get_value = stm32_gpio_get_level, 385 .set_value = stm32_gpio_set_level, 386 .put = stm32_gpio_put_gpio, 387 }; 388 389 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 390 { 391 return chip && chip->ops == &stm32_gpio_ops; 392 } 393 394 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 395 { 396 struct stm32_gpio_bank *bank = NULL; 397 398 STAILQ_FOREACH(bank, &bank_list, link) 399 if (bank_id == bank->bank_id) 400 return bank; 401 402 panic(); 403 } 404 405 #if defined(CFG_STM32_RIF) 406 static bool pin_is_accessible(struct stm32_gpio_bank *bank, unsigned int pin) 407 { 408 bool accessible = false; 409 uint32_t cidcfgr = 0; 410 411 if (!bank->rif_cfg) 412 return true; 413 414 if (clk_enable(bank->clock)) 415 panic(); 416 417 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); 418 419 if (!(cidcfgr & _CIDCFGR_CFEN)) { 420 /* Resource can be accessed when CID filtering is disabled */ 421 accessible = true; 422 } else if (stm32_rif_scid_ok(cidcfgr, GPIO_CIDCFGR_SCID_MASK, 423 RIF_CID1)) { 424 /* Resource can be accessed if CID1 is statically allowed */ 425 accessible = true; 426 } else if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) { 427 /* CID1 is allowed to request the semaphore */ 428 accessible = true; 429 } 430 431 clk_disable(bank->clock); 432 433 return accessible; 434 } 435 436 static TEE_Result acquire_rif_semaphore_if_needed(struct stm32_gpio_bank *bank, 437 unsigned int pin) 438 { 439 TEE_Result res = TEE_SUCCESS; 440 uint32_t cidcfgr = 0; 441 442 if (!bank->rif_cfg) 443 return TEE_SUCCESS; 444 445 res = clk_enable(bank->clock); 446 if (res) 447 return res; 448 449 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); 450 451 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 452 res = stm32_rif_acquire_semaphore(bank->base + GPIO_SEMCR(pin), 453 GPIO_MAX_CID_SUPPORTED); 454 455 clk_disable(bank->clock); 456 457 return res; 458 } 459 460 static uint32_t semaphore_current_cid(struct stm32_gpio_bank *bank, 461 unsigned int pin) 462 { 463 return (io_read32(bank->base + GPIO_SEMCR(pin)) >> 464 _CIDCFGR_SCID_SHIFT) & 465 GENMASK_32(GPIO_MAX_CID_SUPPORTED - 1, 0); 466 } 467 468 static void release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank, 469 unsigned int pin) 470 { 471 TEE_Result res = TEE_ERROR_GENERIC; 472 uint32_t cidcfgr = 0; 473 474 if (!bank->rif_cfg) 475 return; 476 477 res = clk_enable(bank->clock); 478 if (res) 479 panic(); 480 481 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); 482 483 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1) && 484 semaphore_current_cid(bank, pin) == RIF_CID1) { 485 res = stm32_rif_release_semaphore(bank->base + GPIO_SEMCR(pin), 486 GPIO_MAX_CID_SUPPORTED); 487 if (res) { 488 EMSG("Failed to release GPIO %c%u semaphore", 489 bank->bank_id + 'A', pin); 490 panic(); 491 } 492 } 493 494 clk_disable(bank->clock); 495 } 496 #else 497 static bool pin_is_accessible(struct stm32_gpio_bank *bank __unused, 498 unsigned int pin __unused) 499 { 500 return true; 501 } 502 503 static TEE_Result 504 acquire_rif_semaphore_if_needed(struct stm32_gpio_bank *bank __unused, 505 unsigned int pin __unused) 506 { 507 return TEE_SUCCESS; 508 } 509 510 static void 511 release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank __unused, 512 unsigned int pin __unused) 513 { 514 } 515 #endif /*CFG_STM32_RIF*/ 516 517 static bool pin_is_secure(struct stm32_gpio_bank *bank, unsigned int pin) 518 { 519 bool secure = false; 520 521 if (bank->rif_cfg || bank->sec_support) { 522 if (clk_enable(bank->clock)) 523 panic(); 524 525 secure = io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(pin); 526 527 clk_disable(bank->clock); 528 } 529 530 return secure; 531 } 532 533 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 534 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 535 { 536 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 537 538 if (clk_enable(bank->clock)) 539 panic(); 540 541 /* 542 * Save GPIO configuration bits spread over the few bank registers. 543 * 1bit fields are accessed at bit position being the pin index. 544 * 2bit fields are accessed at bit position being twice the pin index. 545 * 4bit fields are accessed at bit position being fourth the pin index 546 * but accessed from 2 32bit registers at incremental addresses. 547 */ 548 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 549 GPIO_MODE_MASK; 550 551 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 552 553 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 554 (pin << 1)) & GPIO_OSPEED_MASK; 555 556 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 557 GPIO_PUPD_PULL_MASK; 558 559 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 560 561 if (pin < GPIO_ALT_LOWER_LIMIT) 562 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 563 (pin << 2)) & GPIO_ALTERNATE_MASK; 564 else 565 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 566 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 567 GPIO_ALTERNATE_MASK; 568 569 clk_disable(bank->clock); 570 } 571 572 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 573 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 574 { 575 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 576 uint32_t exceptions = 0; 577 578 if (clk_enable(bank->clock)) 579 panic(); 580 exceptions = cpu_spin_lock_xsave(&gpio_lock); 581 582 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 583 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 584 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 585 SHIFT_U32(cfg->mode, pin << 1)); 586 587 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 588 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 589 SHIFT_U32(cfg->otype, pin)); 590 591 /* Load GPIO Output Speed confguration, 2bit value */ 592 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 593 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 594 SHIFT_U32(cfg->ospeed, pin << 1)); 595 596 /* Load GPIO pull configuration, 2bit value */ 597 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 598 SHIFT_U32(cfg->pupd, pin << 1)); 599 600 /* Load pin mux Alternate Function configuration, 4bit value */ 601 if (pin < GPIO_ALT_LOWER_LIMIT) { 602 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 603 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 604 SHIFT_U32(cfg->af, pin << 2)); 605 } else { 606 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 607 608 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 609 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 610 SHIFT_U32(cfg->af, shift)); 611 } 612 613 /* Load GPIO Output direction confuguration, 1bit */ 614 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 615 616 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 617 clk_disable(bank->clock); 618 } 619 620 /* Count pins described in the DT node and get related data if possible */ 621 static int get_pinctrl_from_fdt(const void *fdt, int node, 622 int consumer_node __maybe_unused, 623 struct stm32_pinctrl *pinctrl, size_t count) 624 { 625 struct stm32_gpio_bank *bank_ref = NULL; 626 const fdt32_t *cuint = NULL; 627 const fdt32_t *slewrate = NULL; 628 int len = 0; 629 uint32_t i = 0; 630 uint32_t speed = GPIO_OSPEED_LOW; 631 uint32_t pull = GPIO_PUPD_NO_PULL; 632 size_t found = 0; 633 bool do_panic = false; 634 635 cuint = fdt_getprop(fdt, node, "pinmux", &len); 636 if (!cuint) 637 return -FDT_ERR_NOTFOUND; 638 639 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 640 if (slewrate) 641 speed = fdt32_to_cpu(*slewrate); 642 643 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 644 pull = GPIO_PUPD_PULL_UP; 645 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 646 pull = GPIO_PUPD_PULL_DOWN; 647 648 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 649 uint32_t pincfg = 0; 650 uint32_t bank = 0; 651 uint32_t pin = 0; 652 uint32_t mode = 0; 653 uint32_t alternate = 0; 654 uint32_t odata = 0; 655 bool opendrain = false; 656 bool pin_non_secure = true; 657 658 pincfg = fdt32_to_cpu(*cuint); 659 cuint++; 660 661 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 662 663 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 664 665 mode = pincfg & DT_GPIO_MODE_MASK; 666 667 pin_non_secure = pincfg & STM32_PIN_NSEC; 668 669 switch (mode) { 670 case 0: 671 mode = GPIO_MODE_INPUT; 672 break; 673 case 1: 674 case 2: 675 case 3: 676 case 4: 677 case 5: 678 case 6: 679 case 7: 680 case 8: 681 case 9: 682 case 10: 683 case 11: 684 case 12: 685 case 13: 686 case 14: 687 case 15: 688 case 16: 689 alternate = mode - 1U; 690 mode = GPIO_MODE_ALTERNATE; 691 break; 692 case 17: 693 mode = GPIO_MODE_ANALOG; 694 break; 695 default: 696 mode = GPIO_MODE_OUTPUT; 697 break; 698 } 699 700 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 701 opendrain = true; 702 703 if (fdt_getprop(fdt, node, "output-high", NULL) && 704 mode == GPIO_MODE_INPUT) { 705 mode = GPIO_MODE_OUTPUT; 706 odata = 1; 707 } 708 709 if (fdt_getprop(fdt, node, "output-low", NULL) && 710 mode == GPIO_MODE_INPUT) { 711 mode = GPIO_MODE_OUTPUT; 712 odata = 0; 713 } 714 715 if (found < count) { 716 struct stm32_pinctrl *ref = &pinctrl[found]; 717 718 ref->bank = (uint8_t)bank; 719 ref->pin = (uint8_t)pin; 720 ref->cfg.mode = mode; 721 if (opendrain) 722 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; 723 else 724 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; 725 ref->cfg.ospeed = speed; 726 ref->cfg.pupd = pull; 727 ref->cfg.od = odata; 728 ref->cfg.af = alternate; 729 ref->cfg.nsec = pin_non_secure; 730 731 bank_ref = stm32_gpio_get_bank(bank); 732 733 if (pin >= bank_ref->ngpios) { 734 EMSG("node %s requests pin %c%u that does not exist", 735 fdt_get_name(fdt, consumer_node, NULL), 736 bank + 'A', pin); 737 do_panic = true; 738 } 739 } 740 741 found++; 742 } 743 744 if (do_panic) 745 panic(); 746 747 return (int)found; 748 } 749 750 static TEE_Result consumed_gpios_pm(enum pm_op op, 751 unsigned int pm_hint __unused, 752 const struct pm_callback_handle *pm_hdl) 753 { 754 struct stm32_gpio_pm_state *handle = pm_hdl->handle; 755 unsigned int bank_id = handle->gpio_pinctrl.bank; 756 unsigned int pin = handle->gpio_pinctrl.pin; 757 struct gpio_chip *chip = &stm32_gpio_get_bank(bank_id)->gpio_chip; 758 759 if (op == PM_OP_RESUME) { 760 set_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); 761 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) 762 stm32_gpio_set_level(chip, pin, handle->level); 763 } else { 764 get_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); 765 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) 766 handle->level = stm32_gpio_get_level(chip, pin); 767 } 768 769 return TEE_SUCCESS; 770 } 771 DECLARE_KEEP_PAGER(consumed_gpios_pm); 772 773 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 774 struct gpio **out_gpio) 775 { 776 TEE_Result res = TEE_ERROR_GENERIC; 777 const char *consumer_name __maybe_unused = NULL; 778 struct stm32_gpio_pm_state *reg_state = NULL; 779 struct stm32_gpio_pm_state *state = NULL; 780 struct stm32_gpio_bank *bank = data; 781 struct gpio *gpio = NULL; 782 unsigned int shift_1b = 0; 783 unsigned int shift_2b = 0; 784 bool gpio_secure = true; 785 uint32_t exceptions = 0; 786 uint32_t otype = 0; 787 uint32_t pupd = 0; 788 uint32_t mode = 0; 789 790 consumer_name = fdt_get_name(pargs->fdt, pargs->consumer_node, 791 NULL); 792 793 res = gpio_dt_alloc_pin(pargs, &gpio); 794 if (res) 795 return res; 796 797 if (gpio->pin >= bank->ngpios) { 798 DMSG("Invalid GPIO reference"); 799 free(gpio); 800 return TEE_ERROR_GENERIC; 801 } 802 803 if (gpio->dt_flags & GPIO_STM32_NSEC) 804 gpio_secure = false; 805 806 state = calloc(1, sizeof(*state)); 807 if (!state) { 808 free(gpio); 809 return TEE_ERROR_OUT_OF_MEMORY; 810 } 811 812 SLIST_FOREACH(reg_state, &consumed_gpios_head, link) { 813 if (reg_state->gpio_pinctrl.bank == bank->bank_id && 814 reg_state->gpio_pinctrl.pin == gpio->pin) { 815 EMSG("node %s: GPIO %c%u is used by another device", 816 consumer_name, bank->bank_id + 'A', gpio->pin); 817 free(state); 818 free(gpio); 819 return TEE_ERROR_GENERIC; 820 } 821 } 822 823 if (!pin_is_accessible(bank, gpio->pin)) { 824 EMSG("node %s requests pin on GPIO %c%u which access is denied", 825 consumer_name, bank->bank_id + 'A', gpio->pin); 826 panic(); 827 } 828 829 res = acquire_rif_semaphore_if_needed(bank, gpio->pin); 830 if (res) { 831 EMSG("Failed to acquire GPIO %c%u semaphore for node %s", 832 bank->bank_id + 'A', gpio->pin, consumer_name); 833 return res; 834 } 835 836 if (gpio_secure && !(bank->rif_cfg || bank->sec_support)) { 837 EMSG("node %s requests secure GPIO %c%u that cannot be secured", 838 consumer_name, bank->bank_id + 'A', gpio->pin); 839 panic(); 840 } 841 842 if (gpio_secure != pin_is_secure(bank, gpio->pin)) { 843 IMSG("WARNING: node %s requests %s GPIO %c%u but pin is %s. Check st,protreg in GPIO bank node %s", 844 consumer_name, gpio_secure ? "secure" : "non-secure", 845 bank->bank_id + 'A', gpio->pin, 846 pin_is_secure(bank, gpio->pin) ? "secure" : "non-secure", 847 fdt_get_name(pargs->fdt, pargs->phandle_node, NULL)); 848 if (!IS_ENABLED(CFG_INSECURE)) 849 panic(); 850 } 851 852 state->gpio_pinctrl.pin = gpio->pin; 853 state->gpio_pinctrl.bank = bank->bank_id; 854 SLIST_INSERT_HEAD(&consumed_gpios_head, state, link); 855 856 register_pm_driver_cb(consumed_gpios_pm, state, "stm32-gpio-state"); 857 858 shift_1b = gpio->pin; 859 shift_2b = SHIFT_U32(gpio->pin, 1); 860 861 if (gpio->dt_flags & GPIO_PULL_UP) 862 pupd = GPIO_PUPD_PULL_UP; 863 else if (gpio->dt_flags & GPIO_PULL_DOWN) 864 pupd = GPIO_PUPD_PULL_DOWN; 865 else 866 pupd = GPIO_PUPD_NO_PULL; 867 868 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 869 otype = GPIO_OTYPE_OPEN_DRAIN; 870 else 871 otype = GPIO_OTYPE_PUSH_PULL; 872 873 if (clk_enable(bank->clock)) 874 panic(); 875 exceptions = cpu_spin_lock_xsave(&gpio_lock); 876 877 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 878 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 879 SHIFT_U32(mode, shift_2b)); 880 881 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 882 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 883 SHIFT_U32(otype, shift_1b)); 884 885 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 886 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 887 SHIFT_U32(pupd, shift_2b)); 888 889 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 890 clk_disable(bank->clock); 891 892 gpio->chip = &bank->gpio_chip; 893 894 *out_gpio = gpio; 895 896 return TEE_SUCCESS; 897 } 898 899 /* Get bank ID from bank node property st,bank-name or panic on failure */ 900 static unsigned int dt_get_bank_id(const void *fdt, int node) 901 { 902 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 903 const fdt32_t *cuint = NULL; 904 int len = 0; 905 906 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 907 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 908 if (!cuint || (len != dt_name_len + 1)) 909 panic("Missing/wrong st,bank-name property"); 910 911 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 912 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 913 panic("Wrong st,bank-name property"); 914 915 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 916 } 917 918 /* 919 * Return whether or not the GPIO bank related to a DT node is already 920 * registered in the GPIO bank link. 921 */ 922 static bool bank_is_registered(const void *fdt, int node) 923 { 924 unsigned int bank_id = dt_get_bank_id(fdt, node); 925 struct stm32_gpio_bank *bank = NULL; 926 927 STAILQ_FOREACH(bank, &bank_list, link) 928 if (bank->bank_id == bank_id) 929 return true; 930 931 return false; 932 } 933 934 #ifdef CFG_STM32_RIF 935 static TEE_Result handle_available_semaphores(struct stm32_gpio_bank *bank, 936 uint32_t gpios_mask) 937 { 938 TEE_Result res = TEE_ERROR_GENERIC; 939 uint32_t cidcfgr = 0; 940 unsigned int i = 0; 941 942 for (i = 0 ; i < bank->ngpios; i++) { 943 if (!(BIT(i) & gpios_mask)) 944 continue; 945 946 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(i)); 947 948 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 949 continue; 950 951 if (!(io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(i))) { 952 res = stm32_rif_release_semaphore(bank->base + 953 GPIO_SEMCR(i), 954 MAX_CID_SUPPORTED); 955 if (res) { 956 EMSG("Cannot release semaphore for resource %u", 957 i); 958 return res; 959 } 960 } else { 961 res = stm32_rif_acquire_semaphore(bank->base + 962 GPIO_SEMCR(i), 963 MAX_CID_SUPPORTED); 964 if (res) { 965 EMSG("Cannot acquire semaphore for resource %u", 966 i); 967 return res; 968 } 969 } 970 } 971 972 return TEE_SUCCESS; 973 } 974 975 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank, 976 uint32_t gpios_mask) 977 { 978 TEE_Result res = TEE_ERROR_GENERIC; 979 unsigned int i = 0; 980 981 if (!bank->rif_cfg) 982 return TEE_SUCCESS; 983 984 if (clk_enable(bank->clock)) 985 panic(); 986 987 if (bank->is_tdcid) { 988 for (i = 0; i < bank->ngpios; i++) { 989 if (!(BIT(i) & gpios_mask)) 990 continue; 991 992 /* 993 * When TDCID, OP-TEE should be the one to set the CID 994 * filtering configuration. Clearing previous 995 * configuration prevents undesired events during the 996 * only legitimate configuration. 997 */ 998 io_clrbits32(bank->base + GPIO_CIDCFGR(i), 999 GPIO_CIDCFGR_CONF_MASK); 1000 } 1001 } else { 1002 res = handle_available_semaphores(bank, gpios_mask); 1003 if (res) 1004 panic(); 1005 } 1006 1007 /* Security and privilege RIF configuration */ 1008 io_mask32(bank->base + GPIO_PRIVCFGR_OFFSET, 1009 bank->rif_cfg->priv_conf[0], gpios_mask); 1010 io_mask32(bank->base + GPIO_SECR_OFFSET, 1011 bank->rif_cfg->sec_conf[0], gpios_mask); 1012 1013 if (!bank->is_tdcid) { 1014 res = TEE_SUCCESS; 1015 goto out; 1016 } 1017 1018 for (i = 0; i < bank->ngpios; i++) { 1019 if (!(BIT(i) & gpios_mask)) 1020 continue; 1021 1022 io_clrsetbits32(bank->base + GPIO_CIDCFGR(i), 1023 GPIO_CIDCFGR_CONF_MASK, 1024 bank->rif_cfg->cid_confs[i]); 1025 } 1026 1027 /* 1028 * Lock RIF configuration if configured. This cannot be undone until 1029 * next reset. 1030 */ 1031 io_setbits32(bank->base + GPIO_RCFGLOCKR_OFFSET, 1032 bank->rif_cfg->lock_conf[0]); 1033 1034 res = handle_available_semaphores(bank, gpios_mask); 1035 if (res) 1036 panic(); 1037 1038 out: 1039 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) { 1040 /* Check that RIF config are applied, panic otherwise */ 1041 if ((io_read32(bank->base + GPIO_PRIVCFGR_OFFSET) & 1042 gpios_mask) != 1043 (bank->rif_cfg->priv_conf[0] & gpios_mask)) { 1044 EMSG("GPIO bank%c priv conf is incorrect", 1045 'A' + bank->bank_id); 1046 panic(); 1047 } 1048 1049 if ((io_read32(bank->base + GPIO_SECR_OFFSET) & gpios_mask) != 1050 (bank->rif_cfg->sec_conf[0] & gpios_mask)) { 1051 EMSG("GPIO bank %c sec conf is incorrect", 1052 'A' + bank->bank_id); 1053 panic(); 1054 } 1055 } 1056 1057 clk_disable(bank->clock); 1058 1059 return res; 1060 } 1061 #else /* CFG_STM32_RIF */ 1062 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank __unused, 1063 uint32_t gpios_mask __unused) 1064 { 1065 return TEE_SUCCESS; 1066 } 1067 #endif /* CFG_STM32_RIF */ 1068 1069 /* Forward reference to stm32_gpio_set_conf_sec() defined below */ 1070 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank); 1071 1072 static TEE_Result stm32_gpio_fw_configure(struct firewall_query *firewall) 1073 { 1074 struct stm32_gpio_bank *bank = firewall->ctrl->priv; 1075 uint32_t firewall_arg = 0; 1076 uint32_t gpios_mask = 0; 1077 bool secure = true; 1078 1079 assert(bank->sec_support); 1080 1081 if (firewall->arg_count != 1) 1082 return TEE_ERROR_BAD_PARAMETERS; 1083 1084 firewall_arg = firewall->args[0]; 1085 1086 if (bank->rif_cfg) { 1087 gpios_mask = BIT(RIF_CHANNEL_ID(firewall_arg)); 1088 1089 /* We're about to change a specific GPIO config */ 1090 bank->rif_cfg->access_mask[0] |= gpios_mask; 1091 1092 /* 1093 * Update bank RIF config with firewall configuration data 1094 * and apply it. 1095 */ 1096 stm32_rif_parse_cfg(firewall_arg, bank->rif_cfg, 1097 bank->ngpios); 1098 return apply_rif_config(bank, gpios_mask); 1099 } 1100 1101 /* 1102 * Non RIF GPIO banks use a single cell as a bit mask (bits 0 to 15) 1103 * to define the a group of GPIO pins (one or several) to configure 1104 * for that bank, and GPIO_STM32_NSEC bit flag to set if these pins 1105 * are non-secure (flag set) or non-secure (flag cleared). 1106 */ 1107 gpios_mask = firewall_arg & GENMASK_32(15, 0); 1108 1109 secure = !(firewall_arg & GPIO_STM32_NSEC); 1110 1111 if (gpios_mask & ~GENMASK_32(bank->ngpios, 0)) { 1112 EMSG("Invalid bitmask %#"PRIx32" for GPIO bank %c", 1113 gpios_mask, 'A' + bank->bank_id); 1114 return TEE_ERROR_GENERIC; 1115 } 1116 1117 /* Update bank secure register configuration data and apply it */ 1118 if (secure) 1119 bank->seccfgr |= gpios_mask; 1120 else 1121 bank->seccfgr &= ~gpios_mask; 1122 1123 stm32_gpio_set_conf_sec(bank); 1124 1125 return TEE_SUCCESS; 1126 } 1127 1128 static const struct firewall_controller_ops stm32_gpio_firewall_ops = { 1129 .set_conf = stm32_gpio_fw_configure, 1130 }; 1131 1132 static void stm32_gpio_save_rif_config(struct stm32_gpio_bank *bank) 1133 { 1134 size_t i = 0; 1135 1136 for (i = 0; i < bank->ngpios; i++) 1137 bank->rif_cfg->cid_confs[i] = io_read32(bank->base + 1138 GPIO_CIDCFGR(i)); 1139 1140 bank->rif_cfg->priv_conf[0] = io_read32(bank->base + 1141 GPIO_PRIVCFGR_OFFSET); 1142 bank->rif_cfg->sec_conf[0] = io_read32(bank->base + 1143 GPIO_SECR_OFFSET); 1144 bank->rif_cfg->lock_conf[0] = io_read32(bank->base + 1145 GPIO_RCFGLOCKR_OFFSET); 1146 } 1147 1148 static void stm32_parse_gpio_rif_conf(struct stm32_gpio_bank *bank, 1149 const void *fdt, int node) 1150 { 1151 unsigned int i = 0; 1152 unsigned int nb_rif_conf = 0; 1153 int lenp = 0; 1154 const fdt32_t *cuint = NULL; 1155 1156 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 1157 if (!cuint) { 1158 DMSG("No RIF configuration available"); 1159 return; 1160 } 1161 1162 bank->rif_cfg = calloc(1, sizeof(*bank->rif_cfg)); 1163 if (!bank->rif_cfg) 1164 panic(); 1165 1166 bank->rif_cfg->sec_conf = calloc(1, sizeof(uint32_t)); 1167 if (!bank->rif_cfg->sec_conf) 1168 panic(); 1169 1170 nb_rif_conf = (unsigned int)(lenp / sizeof(uint32_t)); 1171 assert(nb_rif_conf <= bank->ngpios); 1172 1173 bank->rif_cfg->cid_confs = calloc(bank->ngpios, sizeof(uint32_t)); 1174 bank->rif_cfg->priv_conf = calloc(1, sizeof(uint32_t)); 1175 bank->rif_cfg->lock_conf = calloc(1, sizeof(uint32_t)); 1176 bank->rif_cfg->access_mask = calloc(1, sizeof(uint32_t)); 1177 if (!bank->rif_cfg->cid_confs || !bank->rif_cfg->access_mask || 1178 !bank->rif_cfg->priv_conf || !bank->rif_cfg->lock_conf) 1179 panic("Missing memory capacity for GPIOS RIF configuration"); 1180 1181 for (i = 0; i < nb_rif_conf; i++) 1182 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), bank->rif_cfg, 1183 bank->ngpios); 1184 } 1185 1186 /* Get GPIO bank information from the DT */ 1187 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 1188 const void *compat_data, 1189 int range_offset, 1190 struct stm32_gpio_bank **out_bank) 1191 { 1192 const struct bank_compat *compat = compat_data; 1193 TEE_Result res = TEE_ERROR_GENERIC; 1194 struct stm32_gpio_bank *bank = NULL; 1195 const fdt32_t *cuint = NULL; 1196 struct io_pa_va pa_va = { }; 1197 struct clk *clk = NULL; 1198 size_t blen = 0; 1199 paddr_t pa = 0; 1200 int len = 0; 1201 int i = 0; 1202 1203 assert(out_bank); 1204 1205 /* Probe deferrable devices first */ 1206 res = clk_dt_get_by_index(fdt, node, 0, &clk); 1207 if (res) 1208 return res; 1209 1210 bank = calloc(1, sizeof(*bank)); 1211 if (!bank) 1212 return TEE_ERROR_OUT_OF_MEMORY; 1213 1214 if (compat->secure_extended) { 1215 res = stm32_rifsc_check_tdcid(&bank->is_tdcid); 1216 if (res) { 1217 free(bank); 1218 return res; 1219 } 1220 } 1221 1222 /* 1223 * Do not rely *only* on the "reg" property to get the address, 1224 * but consider also the "ranges" translation property 1225 */ 1226 if (fdt_reg_info(fdt, node, &pa, &blen)) 1227 panic("missing reg or reg size property"); 1228 1229 pa_va.pa = pa + range_offset; 1230 1231 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 1232 bank->bank_id = dt_get_bank_id(fdt, node); 1233 bank->clock = clk; 1234 bank->gpio_chip.ops = &stm32_gpio_ops; 1235 bank->sec_support = compat->secure_control; 1236 1237 /* Parse gpio-ranges with its 4 parameters */ 1238 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 1239 len /= sizeof(*cuint); 1240 if (len % 4) 1241 panic("wrong gpio-ranges syntax"); 1242 1243 /* Get the last defined gpio line (offset + nb of pins) */ 1244 for (i = 0; i < len / 4; i++) { 1245 bank->ngpios = MAX(bank->ngpios, 1246 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 1247 fdt32_to_cpu(*(cuint + 3)))); 1248 cuint += 4; 1249 } 1250 1251 if (compat->secure_extended) { 1252 /* RIF configuration */ 1253 bank->base = io_pa_or_va_secure(&pa_va, blen); 1254 1255 stm32_parse_gpio_rif_conf(bank, fdt, node); 1256 } else if (bank->sec_support) { 1257 /* Secure configuration */ 1258 bank->base = io_pa_or_va_secure(&pa_va, blen); 1259 cuint = fdt_getprop(fdt, node, "st,protreg", NULL); 1260 if (cuint) 1261 bank->seccfgr = fdt32_to_cpu(*cuint); 1262 else 1263 DMSG("GPIO bank %c assigned to non-secure", 1264 bank->bank_id + 'A'); 1265 } else { 1266 bank->base = io_pa_or_va_nsec(&pa_va, blen); 1267 } 1268 1269 if (compat->gpioz) 1270 stm32mp_register_gpioz_pin_count(bank->ngpios); 1271 1272 *out_bank = bank; 1273 1274 return TEE_SUCCESS; 1275 } 1276 1277 static TEE_Result stm32_gpio_firewall_register(const void *fdt, int node, 1278 struct stm32_gpio_bank *bank) 1279 { 1280 struct firewall_controller *controller = NULL; 1281 TEE_Result res = TEE_ERROR_GENERIC; 1282 char bank_name[] = "gpio-bank-X"; 1283 char *name = NULL; 1284 1285 if (!IS_ENABLED(CFG_DRIVERS_FIREWALL) || 1286 !bank->sec_support) 1287 return TEE_SUCCESS; 1288 1289 controller = calloc(1, sizeof(*controller)); 1290 if (!controller) 1291 return TEE_ERROR_OUT_OF_MEMORY; 1292 1293 bank_name[sizeof(bank_name) - 2] = 'A' + bank->bank_id; 1294 name = strdup(bank_name); 1295 1296 controller->name = name; 1297 controller->priv = bank; 1298 controller->ops = &stm32_gpio_firewall_ops; 1299 1300 if (!controller->name) 1301 EMSG("Warning: out of memory to store bank name"); 1302 1303 res = firewall_dt_controller_register(fdt, node, controller); 1304 if (res) { 1305 free(name); 1306 free(controller); 1307 } 1308 1309 return res; 1310 } 1311 1312 /* Parse a pinctrl node to register the GPIO banks it describes */ 1313 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 1314 const void *compat_data) 1315 { 1316 TEE_Result res = TEE_SUCCESS; 1317 const fdt32_t *cuint = NULL; 1318 int range_offs = 0; 1319 int b_node = 0; 1320 int len = 0; 1321 1322 /* Read the ranges property (for regs memory translation) */ 1323 cuint = fdt_getprop(fdt, node, "ranges", &len); 1324 if (!cuint) 1325 panic("missing ranges property"); 1326 1327 len /= sizeof(*cuint); 1328 if (len == 3) 1329 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 1330 1331 fdt_for_each_subnode(b_node, fdt, node) { 1332 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 1333 if (cuint) { 1334 /* 1335 * We found a property "gpio-controller" in the node: 1336 * the node is a GPIO bank description, add it to the 1337 * bank list. 1338 */ 1339 struct stm32_gpio_bank *bank = NULL; 1340 1341 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 1342 bank_is_registered(fdt, b_node)) 1343 continue; 1344 1345 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 1346 range_offs, &bank); 1347 if (res) 1348 return res; 1349 1350 /* Registering a provider should not defer probe */ 1351 res = gpio_register_provider(fdt, b_node, 1352 stm32_gpio_get_dt, bank); 1353 if (res) 1354 panic(); 1355 1356 res = stm32_gpio_firewall_register(fdt, b_node, bank); 1357 if (res) 1358 panic(); 1359 1360 STAILQ_INSERT_TAIL(&bank_list, bank, link); 1361 } else { 1362 if (len != -FDT_ERR_NOTFOUND) 1363 panic(); 1364 } 1365 } 1366 1367 return TEE_SUCCESS; 1368 } 1369 1370 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 1371 bool secure) 1372 { 1373 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 1374 uint32_t exceptions = 0; 1375 1376 if (clk_enable(bank->clock)) 1377 panic(); 1378 exceptions = cpu_spin_lock_xsave(&gpio_lock); 1379 1380 if (secure) 1381 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 1382 else 1383 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 1384 1385 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 1386 clk_disable(bank->clock); 1387 } 1388 1389 #ifdef CFG_DRIVERS_PINCTRL 1390 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf) 1391 { 1392 struct stm32_pinctrl_array *ref = conf->priv; 1393 struct stm32_pinctrl *p = ref->pinctrl; 1394 struct stm32_gpio_bank *bank = NULL; 1395 TEE_Result res = TEE_ERROR_GENERIC; 1396 size_t pin_count = ref->count; 1397 size_t n = 0; 1398 bool error = false; 1399 1400 for (n = 0; n < pin_count; n++) { 1401 bank = stm32_gpio_get_bank(p[n].bank); 1402 1403 if (!pin_is_accessible(bank, p[n].pin)) { 1404 EMSG("Apply pinctrl for pin %c%u that cannot be accessed", 1405 p[n].bank + 'A', p[n].pin); 1406 error = true; 1407 continue; 1408 } 1409 1410 res = acquire_rif_semaphore_if_needed(bank, p[n].pin); 1411 if (res) { 1412 EMSG("Failed to acquire GPIO %c%u semaphore", 1413 bank->bank_id + 'A', p[n].pin); 1414 error = true; 1415 continue; 1416 } 1417 1418 if (p[n].cfg.nsec == !pin_is_secure(bank, p[n].pin)) 1419 continue; 1420 1421 if (IS_ENABLED(CFG_INSECURE)) { 1422 IMSG("WARNING: apply pinctrl for %ssecure pin %c%u that is %ssecure", 1423 p[n].cfg.nsec ? "non-" : "", 1424 p[n].bank + 'A', p[n].pin, 1425 pin_is_secure(bank, p[n].pin) ? "" : "non-"); 1426 } else { 1427 EMSG("Apply pinctrl for %ssecure pin %c%u that is %ssecure", 1428 p[n].cfg.nsec ? "non-" : "", 1429 p[n].bank + 'A', p[n].pin, 1430 pin_is_secure(bank, p[n].pin) ? "" : "non-"); 1431 error = true; 1432 } 1433 } 1434 1435 if (error) { 1436 for (n = 0; n < pin_count; n++) { 1437 bank = stm32_gpio_get_bank(p[n].bank); 1438 release_rif_semaphore_if_acquired(bank, p[n].pin); 1439 } 1440 1441 return TEE_ERROR_SECURITY; 1442 } 1443 1444 for (n = 0; n < pin_count; n++) 1445 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg); 1446 1447 return TEE_SUCCESS; 1448 } 1449 1450 static void stm32_pinctrl_conf_free(struct pinconf *conf) 1451 { 1452 free(conf); 1453 } 1454 1455 static const struct pinctrl_ops stm32_pinctrl_ops = { 1456 .conf_apply = stm32_pinctrl_conf_apply, 1457 .conf_free = stm32_pinctrl_conf_free, 1458 }; 1459 1460 DECLARE_KEEP_PAGER(stm32_pinctrl_ops); 1461 1462 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl, 1463 unsigned int *bank, unsigned int *pin, 1464 unsigned int *count) 1465 { 1466 size_t conf_index = 0; 1467 size_t pin_count = 0; 1468 size_t n = 0; 1469 1470 assert(count); 1471 if (!pinctrl) 1472 goto out; 1473 1474 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1475 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1476 struct stm32_pinctrl_array *ref = pinconf->priv; 1477 1478 /* Consider only the stm32_gpio pins */ 1479 if (pinconf->ops != &stm32_pinctrl_ops) 1480 continue; 1481 1482 if (bank || pin) { 1483 for (n = 0; n < ref->count; n++) { 1484 if (bank && pin_count < *count) 1485 bank[pin_count] = ref->pinctrl[n].bank; 1486 if (pin && pin_count < *count) 1487 pin[pin_count] = ref->pinctrl[n].pin; 1488 pin_count++; 1489 } 1490 } else { 1491 pin_count += ref->count; 1492 } 1493 } 1494 1495 out: 1496 *count = pin_count; 1497 } 1498 1499 void stm32_pinctrl_set_secure_cfg(struct pinctrl_state *pinctrl, bool secure) 1500 { 1501 size_t conf_index = 0; 1502 1503 if (!pinctrl) 1504 return; 1505 1506 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1507 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1508 struct stm32_pinctrl_array *ref = pinconf->priv; 1509 struct stm32_pinctrl *pc = NULL; 1510 size_t n = 0; 1511 1512 for (n = 0; n < ref->count; n++) { 1513 if (pinconf->ops != &stm32_pinctrl_ops) 1514 continue; 1515 1516 pc = ref->pinctrl + n; 1517 stm32_gpio_set_secure_cfg(pc->bank, pc->pin, secure); 1518 } 1519 } 1520 } 1521 1522 /* Allocate and return a pinctrl configuration from a DT reference */ 1523 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs, 1524 void *data __unused, 1525 struct pinconf **out_pinconf) 1526 { 1527 struct conf { 1528 struct pinconf pinconf; 1529 struct stm32_pinctrl_array array_ref; 1530 } *loc_conf = NULL; 1531 struct stm32_pinctrl *pinctrl = NULL; 1532 struct pinconf *pinconf = NULL; 1533 const void *fdt = NULL; 1534 size_t pin_count = 0; 1535 int pinctrl_node = 0; 1536 int pinmux_node = 0; 1537 int count = 0; 1538 1539 pinctrl_node = pargs->phandle_node; 1540 fdt = pargs->fdt; 1541 assert(fdt && pinctrl_node); 1542 1543 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1544 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count)) 1545 pin_count += (size_t)count / sizeof(uint32_t); 1546 else if (count != -FDT_ERR_NOTFOUND) 1547 panic(); 1548 } 1549 1550 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count); 1551 if (!loc_conf) 1552 return TEE_ERROR_OUT_OF_MEMORY; 1553 1554 pinconf = &loc_conf->pinconf; 1555 pinconf->ops = &stm32_pinctrl_ops; 1556 pinconf->priv = &loc_conf->array_ref; 1557 1558 loc_conf->array_ref.count = pin_count; 1559 pinctrl = loc_conf->array_ref.pinctrl; 1560 1561 count = 0; 1562 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1563 int found = 0; 1564 1565 found = get_pinctrl_from_fdt(fdt, pinmux_node, 1566 pargs->consumer_node, 1567 pinctrl + count, 1568 pin_count - count); 1569 if (found <= 0 && found > ((int)pin_count - count)) { 1570 /* We can't recover from an error here so let's panic */ 1571 panic(); 1572 } 1573 1574 count += found; 1575 } 1576 1577 *out_pinconf = pinconf; 1578 1579 return TEE_SUCCESS; 1580 } 1581 #endif /*CFG_DRIVERS_PINCTRL*/ 1582 1583 static void stm32_gpio_get_conf_sec(struct stm32_gpio_bank *bank) 1584 { 1585 if (bank->sec_support) { 1586 clk_enable(bank->clock); 1587 bank->seccfgr = io_read32(bank->base + GPIO_SECR_OFFSET); 1588 clk_disable(bank->clock); 1589 } 1590 } 1591 1592 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank) 1593 { 1594 if (bank->sec_support) { 1595 clk_enable(bank->clock); 1596 io_write32(bank->base + GPIO_SECR_OFFSET, bank->seccfgr); 1597 clk_disable(bank->clock); 1598 } 1599 } 1600 1601 static TEE_Result stm32_gpio_sec_config_resume(void) 1602 { 1603 TEE_Result res = TEE_ERROR_GENERIC; 1604 struct stm32_gpio_bank *bank = NULL; 1605 1606 STAILQ_FOREACH(bank, &bank_list, link) { 1607 if (bank->rif_cfg) { 1608 if (!bank->is_tdcid) 1609 continue; 1610 1611 bank->rif_cfg->access_mask[0] = GENMASK_32(bank->ngpios, 1612 0); 1613 1614 res = apply_rif_config(bank, 1615 bank->rif_cfg->access_mask[0]); 1616 if (res) { 1617 EMSG("Failed to set GPIO bank %c RIF config", 1618 'A' + bank->bank_id); 1619 return res; 1620 } 1621 } else { 1622 stm32_gpio_set_conf_sec(bank); 1623 } 1624 } 1625 1626 return TEE_SUCCESS; 1627 } 1628 1629 static TEE_Result stm32_gpio_sec_config_suspend(void) 1630 { 1631 struct stm32_gpio_bank *bank = NULL; 1632 1633 STAILQ_FOREACH(bank, &bank_list, link) { 1634 if (bank->rif_cfg) { 1635 if (bank->is_tdcid) 1636 stm32_gpio_save_rif_config(bank); 1637 } else { 1638 stm32_gpio_get_conf_sec(bank); 1639 } 1640 } 1641 1642 return TEE_SUCCESS; 1643 } 1644 1645 static TEE_Result 1646 stm32_gpio_sec_config_pm(enum pm_op op, unsigned int pm_hint, 1647 const struct pm_callback_handle *hdl __unused) 1648 { 1649 TEE_Result ret = TEE_ERROR_GENERIC; 1650 1651 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT)) 1652 return TEE_SUCCESS; 1653 1654 if (op == PM_OP_RESUME) 1655 ret = stm32_gpio_sec_config_resume(); 1656 else 1657 ret = stm32_gpio_sec_config_suspend(); 1658 1659 return ret; 1660 } 1661 DECLARE_KEEP_PAGER(stm32_gpio_sec_config_pm); 1662 1663 /* 1664 * Several pinctrl nodes can be probed. Their bank will be put in the unique 1665 * bank_list. To avoid multiple configuration set for a bank when looping 1666 * over each bank in the bank list, ready is set to true when a bank is 1667 * configured. Therefore, during other bank probes, the configuration won't 1668 * be set again. 1669 */ 1670 static TEE_Result apply_sec_cfg(void) 1671 { 1672 TEE_Result res = TEE_ERROR_GENERIC; 1673 struct stm32_gpio_bank *bank = NULL; 1674 unsigned int pin = 0; 1675 1676 STAILQ_FOREACH(bank, &bank_list, link) { 1677 if (bank->ready) 1678 continue; 1679 1680 if (bank->rif_cfg) { 1681 res = apply_rif_config(bank, 1682 bank->rif_cfg->access_mask[0]); 1683 if (res) { 1684 EMSG("Failed to set GPIO bank %c RIF config", 1685 'A' + bank->bank_id); 1686 STAILQ_REMOVE(&bank_list, bank, stm32_gpio_bank, 1687 link); 1688 free(bank); 1689 return res; 1690 } 1691 1692 /* 1693 * Semaphores for pinctrl and GPIO are taken when 1694 * these are used (pinctrl state applied, GPIO 1695 * consumed) or when an explicit firewall configuration 1696 * is requested through the firewall framework. 1697 * Therefore release here the taken semaphores. 1698 */ 1699 for (pin = 0; pin < bank->ngpios; pin++) 1700 release_rif_semaphore_if_acquired(bank, pin); 1701 1702 } else { 1703 stm32_gpio_set_conf_sec(bank); 1704 } 1705 1706 bank->ready = true; 1707 } 1708 1709 return TEE_SUCCESS; 1710 } 1711 1712 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 1713 const void *compat_data) 1714 { 1715 static bool pm_register; 1716 TEE_Result res = TEE_ERROR_GENERIC; 1717 1718 /* Register GPIO banks described in this pin control node */ 1719 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data); 1720 if (res) 1721 return res; 1722 1723 if (STAILQ_EMPTY(&bank_list)) 1724 DMSG("no gpio bank for that driver"); 1725 else if (apply_sec_cfg()) 1726 panic(); 1727 1728 if (!pm_register) { 1729 /* 1730 * Register to PM once for all probed banks to restore 1731 * their secure configuration. 1732 */ 1733 register_pm_driver_cb(stm32_gpio_sec_config_pm, NULL, 1734 "stm32-gpio-secure-config"); 1735 pm_register = true; 1736 } 1737 1738 #ifdef CFG_DRIVERS_PINCTRL 1739 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get, 1740 (void *)compat_data); 1741 if (res) 1742 panic(); 1743 #endif 1744 1745 return TEE_SUCCESS; 1746 } 1747 1748 static const struct dt_device_match stm32_pinctrl_match_table[] = { 1749 { 1750 .compatible = "st,stm32mp135-pinctrl", 1751 .compat_data = &(struct bank_compat){ 1752 .secure_control = true, 1753 .secure_extended = false, 1754 }, 1755 }, 1756 { 1757 .compatible = "st,stm32mp157-pinctrl", 1758 .compat_data = &(struct bank_compat){ 1759 .secure_control = false, 1760 .secure_extended = false, 1761 }, 1762 }, 1763 { 1764 .compatible = "st,stm32mp157-z-pinctrl", 1765 .compat_data = &(struct bank_compat){ 1766 .gpioz = true, 1767 .secure_control = true, 1768 .secure_extended = false, 1769 }, 1770 }, 1771 { 1772 .compatible = "st,stm32mp257-pinctrl", 1773 .compat_data = &(struct bank_compat){ 1774 .secure_control = true, 1775 .secure_extended = true, 1776 }, 1777 }, 1778 { 1779 .compatible = "st,stm32mp257-z-pinctrl", 1780 .compat_data = &(struct bank_compat){ 1781 .gpioz = true, 1782 .secure_control = true, 1783 .secure_extended = true, 1784 }, 1785 }, 1786 { } 1787 }; 1788 1789 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 1790 .name = "stm32_gpio-pinctrl", 1791 .type = DT_DRIVER_PINCTRL, 1792 .match_table = stm32_pinctrl_match_table, 1793 .probe = stm32_pinctrl_probe, 1794 }; 1795