1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2024, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <compiler.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/firewall.h> 13 #include <drivers/gpio.h> 14 #include <drivers/pinctrl.h> 15 #include <drivers/stm32_gpio.h> 16 #include <drivers/stm32_rif.h> 17 #include <dt-bindings/gpio/stm32mp_gpio.h> 18 #include <io.h> 19 #include <kernel/dt.h> 20 #include <kernel/boot.h> 21 #include <kernel/panic.h> 22 #include <kernel/pm.h> 23 #include <kernel/spinlock.h> 24 #include <libfdt.h> 25 #include <mm/core_memprot.h> 26 #include <stdbool.h> 27 #include <stdint.h> 28 #include <stm32_util.h> 29 #include <sys/queue.h> 30 #include <trace.h> 31 #include <util.h> 32 33 #ifndef CFG_DRIVERS_GPIO 34 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 35 #endif 36 37 #define GPIO_PIN_MAX 15 38 39 #define GPIO_MODER_OFFSET U(0x00) 40 #define GPIO_OTYPER_OFFSET U(0x04) 41 #define GPIO_OSPEEDR_OFFSET U(0x08) 42 #define GPIO_PUPDR_OFFSET U(0x0c) 43 #define GPIO_IDR_OFFSET U(0x10) 44 #define GPIO_ODR_OFFSET U(0x14) 45 #define GPIO_BSRR_OFFSET U(0x18) 46 #define GPIO_AFRL_OFFSET U(0x20) 47 #define GPIO_AFRH_OFFSET U(0x24) 48 #define GPIO_SECR_OFFSET U(0x30) 49 #define GPIO_PRIVCFGR_OFFSET U(0x34) 50 #define GPIO_RCFGLOCKR_OFFSET U(0x38) 51 #define GPIO_CIDCFGR(x) (U(0x50) + U(0x8) * (x)) 52 #define GPIO_SEMCR(x) (U(0x54) + U(0x8) * (x)) 53 54 #define GPIO_ALT_LOWER_LIMIT U(0x8) 55 56 /* 57 * CIDCFGR register bitfields 58 */ 59 #define GPIO_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16) 60 #define GPIO_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 61 #define GPIO_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | _CIDCFGR_SEMEN | \ 62 GPIO_CIDCFGR_SCID_MASK | \ 63 GPIO_CIDCFGR_SEMWL_MASK) 64 65 /* 66 * PRIVCFGR register bitfields 67 */ 68 #define GPIO_PRIVCFGR_MASK GENMASK_32(15, 0) 69 70 /* 71 * SECCFGR register bitfields 72 */ 73 #define GPIO_SECCFGR_MASK GENMASK_32(15, 0) 74 75 /* 76 * RCFGLOCKR register bitfields 77 */ 78 #define GPIO_RCFGLOCKR_MASK GENMASK_32(15, 0) 79 80 /* 81 * SEMCR register bitfields 82 */ 83 #define GPIO_SEMCR_SCID_M GENMASK_32(6, 4) 84 85 #define GPIO_MODE_MASK GENMASK_32(1, 0) 86 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 87 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 88 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 89 90 #define DT_GPIO_BANK_SHIFT U(12) 91 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 92 #define DT_GPIO_PIN_SHIFT U(8) 93 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 94 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 95 96 #define DT_GPIO_BANK_NAME0 "GPIOA" 97 98 #define GPIO_MODE_INPUT U(0x0) 99 #define GPIO_MODE_OUTPUT U(0x1) 100 #define GPIO_MODE_ALTERNATE U(0x2) 101 #define GPIO_MODE_ANALOG U(0x3) 102 103 #define GPIO_OTYPE_PUSH_PULL U(0x0) 104 #define GPIO_OTYPE_OPEN_DRAIN U(0x1) 105 106 #define GPIO_OSPEED_LOW U(0x0) 107 #define GPIO_OSPEED_MEDIUM U(0x1) 108 #define GPIO_OSPEED_HIGH U(0x2) 109 #define GPIO_OSPEED_VERY_HIGH U(0x3) 110 111 #define GPIO_PUPD_NO_PULL U(0x0) 112 #define GPIO_PUPD_PULL_UP U(0x1) 113 #define GPIO_PUPD_PULL_DOWN U(0x2) 114 115 #define GPIO_OD_LEVEL_LOW U(0x0) 116 #define GPIO_OD_LEVEL_HIGH U(0x1) 117 118 #define GPIO_MAX_CID_SUPPORTED U(3) 119 120 /* 121 * GPIO configuration description structured as single 16bit word 122 * for efficient save/restore when GPIO pin suspends or resumes. 123 * 124 * @mode: One of GPIO_MODE_* 125 * @otype: One of GPIO_OTYPE_* 126 * @ospeed: One of GPIO_OSPEED_* 127 * @pupd: One of GPIO_PUPD_* 128 * @od: One of GPIO_OD_* 129 * @af: Alternate function numerical ID between 0 and 15 130 */ 131 struct gpio_cfg { 132 uint16_t mode: 2; 133 uint16_t otype: 1; 134 uint16_t ospeed: 2; 135 uint16_t pupd: 2; 136 uint16_t od: 1; 137 uint16_t af: 4; 138 }; 139 140 /* 141 * Description of a pin and its muxing 142 * 143 * @bank: GPIO bank identifier as assigned by the platform 144 * @pin: Pin number in the GPIO bank 145 * @cfg: Pin configuration 146 */ 147 struct stm32_pinctrl { 148 uint8_t bank; 149 uint8_t pin; 150 struct gpio_cfg cfg; 151 }; 152 153 /* 154 * struct stm32_pinctrl_array - Array of pins in a pin control state 155 * @count: Number of cells in @pinctrl 156 * @pinctrl: Pin control configuration 157 */ 158 struct stm32_pinctrl_array { 159 size_t count; 160 struct stm32_pinctrl pinctrl[]; 161 }; 162 163 /** 164 * struct stm32_gpio_bank - GPIO bank instance 165 * 166 * @base: base address of the GPIO controller registers. 167 * @clock: clock identifier. 168 * @gpio_chip: GPIO chip reference for that GPIO bank 169 * @ngpios: number of GPIOs. 170 * @bank_id: Id of the bank. 171 * @lock: lock protecting the GPIO bank access. 172 * @rif_cfg: RIF configuration data 173 * @seccfgr: non-RIF bank secure configuration data 174 * @sec_support: True if bank supports pin security protection, else false 175 * @ready: True if configuration is applied, else false 176 * @is_tdcid: True if OP-TEE runs as Trusted Domain CID 177 * @link: Link in bank list 178 */ 179 struct stm32_gpio_bank { 180 vaddr_t base; 181 struct clk *clock; 182 struct gpio_chip gpio_chip; 183 unsigned int ngpios; 184 unsigned int bank_id; 185 unsigned int lock; 186 struct rif_conf_data *rif_cfg; 187 uint32_t seccfgr; 188 bool sec_support; 189 bool ready; 190 bool is_tdcid; 191 STAILQ_ENTRY(stm32_gpio_bank) link; 192 }; 193 194 /* 195 * struct stm32_gpio_pm_state - Consumed GPIO for PM purpose 196 * @gpio_pinctrl: Reference and configuration state for a consumed GPIO 197 * @level: GPIO level 198 * @link: Link in consumed GPIO list 199 */ 200 struct stm32_gpio_pm_state { 201 struct stm32_pinctrl gpio_pinctrl; 202 uint8_t level; 203 SLIST_ENTRY(stm32_gpio_pm_state) link; 204 }; 205 206 /** 207 * Compatibility information of supported banks 208 * 209 * @gpioz: True if bank is a GPIOZ bank 210 * @secure_control: Identify GPIO security bank capability. 211 * @secure_extended: Identify RIF presence. 212 */ 213 struct bank_compat { 214 bool gpioz; 215 bool secure_control; 216 bool secure_extended; 217 }; 218 219 static unsigned int gpio_lock; 220 221 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 222 STAILQ_HEAD_INITIALIZER(bank_list); 223 224 static SLIST_HEAD(, stm32_gpio_pm_state) consumed_gpios_head; 225 226 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 227 228 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 229 { 230 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 231 } 232 233 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 234 unsigned int gpio_pin) 235 { 236 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 237 enum gpio_level level = GPIO_LEVEL_HIGH; 238 unsigned int reg_offset = 0; 239 unsigned int mode = 0; 240 241 assert(gpio_pin < bank->ngpios); 242 243 if (clk_enable(bank->clock)) 244 panic(); 245 246 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 247 GPIO_MODE_MASK; 248 249 switch (mode) { 250 case GPIO_MODE_INPUT: 251 reg_offset = GPIO_IDR_OFFSET; 252 break; 253 case GPIO_MODE_OUTPUT: 254 reg_offset = GPIO_ODR_OFFSET; 255 break; 256 default: 257 panic(); 258 } 259 260 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 261 level = GPIO_LEVEL_HIGH; 262 else 263 level = GPIO_LEVEL_LOW; 264 265 clk_disable(bank->clock); 266 267 return level; 268 } 269 270 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 271 enum gpio_level level) 272 { 273 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 274 275 assert(gpio_pin < bank->ngpios); 276 277 if (clk_enable(bank->clock)) 278 panic(); 279 280 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 281 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 282 283 if (level == GPIO_LEVEL_HIGH) 284 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 285 else 286 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 287 288 clk_disable(bank->clock); 289 } 290 291 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 292 unsigned int gpio_pin) 293 { 294 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 295 uint32_t mode = 0; 296 297 assert(gpio_pin < bank->ngpios); 298 299 if (clk_enable(bank->clock)) 300 panic(); 301 302 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 303 GPIO_MODE_MASK; 304 305 clk_disable(bank->clock); 306 307 switch (mode) { 308 case GPIO_MODE_INPUT: 309 return GPIO_DIR_IN; 310 case GPIO_MODE_OUTPUT: 311 return GPIO_DIR_OUT; 312 default: 313 panic(); 314 } 315 } 316 317 static void stm32_gpio_set_direction(struct gpio_chip *chip, 318 unsigned int gpio_pin, 319 enum gpio_dir direction) 320 { 321 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 322 uint32_t exceptions = 0; 323 uint32_t mode = 0; 324 325 assert(gpio_pin < bank->ngpios); 326 327 if (direction == GPIO_DIR_IN) 328 mode = GPIO_MODE_INPUT; 329 else 330 mode = GPIO_MODE_OUTPUT; 331 332 if (clk_enable(bank->clock)) 333 panic(); 334 exceptions = cpu_spin_lock_xsave(&gpio_lock); 335 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 336 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 337 SHIFT_U32(mode, gpio_pin << 1)); 338 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 339 clk_disable(bank->clock); 340 } 341 342 /* Forward reference to the PM callback handler for consumed GPIOs */ 343 static TEE_Result consumed_gpios_pm(enum pm_op op, unsigned int pm_hint, 344 const struct pm_callback_handle *pm_hdl); 345 346 /* Forward reference to RIF semaphore release helper function */ 347 static void release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank, 348 unsigned int pin); 349 350 static void stm32_gpio_put_gpio(struct gpio_chip *chip, struct gpio *gpio) 351 { 352 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 353 struct stm32_gpio_pm_state *tstate = NULL; 354 struct stm32_gpio_pm_state *state = NULL; 355 uint32_t exceptions = 0; 356 357 assert(is_stm32_gpio_chip(chip)); 358 359 exceptions = cpu_spin_lock_xsave(&gpio_lock); 360 361 SLIST_FOREACH_SAFE(state, &consumed_gpios_head, link, tstate) { 362 if (state->gpio_pinctrl.bank == bank->bank_id && 363 state->gpio_pinctrl.pin == gpio->pin) { 364 SLIST_REMOVE(&consumed_gpios_head, state, 365 stm32_gpio_pm_state, link); 366 unregister_pm_driver_cb(consumed_gpios_pm, state); 367 release_rif_semaphore_if_acquired(bank, gpio->pin); 368 free(state); 369 free(gpio); 370 break; 371 } 372 } 373 assert(state); 374 375 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 376 } 377 378 static const struct gpio_ops stm32_gpio_ops = { 379 .get_direction = stm32_gpio_get_direction, 380 .set_direction = stm32_gpio_set_direction, 381 .get_value = stm32_gpio_get_level, 382 .set_value = stm32_gpio_set_level, 383 .put = stm32_gpio_put_gpio, 384 }; 385 386 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 387 { 388 return chip && chip->ops == &stm32_gpio_ops; 389 } 390 391 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 392 { 393 struct stm32_gpio_bank *bank = NULL; 394 395 STAILQ_FOREACH(bank, &bank_list, link) 396 if (bank_id == bank->bank_id) 397 return bank; 398 399 panic(); 400 } 401 402 #if defined(CFG_STM32_RIF) 403 static TEE_Result acquire_rif_semaphore_if_needed(struct stm32_gpio_bank *bank, 404 unsigned int pin) 405 { 406 TEE_Result res = TEE_SUCCESS; 407 uint32_t cidcfgr = 0; 408 409 if (!bank->rif_cfg) 410 return TEE_SUCCESS; 411 412 res = clk_enable(bank->clock); 413 if (res) 414 return res; 415 416 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); 417 418 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 419 res = stm32_rif_acquire_semaphore(bank->base + GPIO_SEMCR(pin), 420 GPIO_MAX_CID_SUPPORTED); 421 422 clk_disable(bank->clock); 423 424 return res; 425 } 426 427 static uint32_t semaphore_current_cid(struct stm32_gpio_bank *bank, 428 unsigned int pin) 429 { 430 return (io_read32(bank->base + GPIO_SEMCR(pin)) >> 431 _CIDCFGR_SCID_SHIFT) & 432 GENMASK_32(GPIO_MAX_CID_SUPPORTED - 1, 0); 433 } 434 435 static void release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank, 436 unsigned int pin) 437 { 438 TEE_Result res = TEE_ERROR_GENERIC; 439 uint32_t cidcfgr = 0; 440 441 if (!bank->rif_cfg) 442 return; 443 444 res = clk_enable(bank->clock); 445 if (res) 446 panic(); 447 448 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); 449 450 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1) && 451 semaphore_current_cid(bank, pin) == RIF_CID1) { 452 res = stm32_rif_release_semaphore(bank->base + GPIO_SEMCR(pin), 453 GPIO_MAX_CID_SUPPORTED); 454 if (res) { 455 EMSG("Failed to release GPIO %c%u semaphore", 456 bank->bank_id + 'A', pin); 457 panic(); 458 } 459 } 460 461 clk_disable(bank->clock); 462 } 463 #else 464 static TEE_Result 465 acquire_rif_semaphore_if_needed(struct stm32_gpio_bank *bank __unused, 466 unsigned int pin __unused) 467 { 468 return TEE_SUCCESS; 469 } 470 471 static void 472 release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank __unused, 473 unsigned int pin __unused) 474 { 475 } 476 #endif /*CFG_STM32_RIF*/ 477 478 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 479 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 480 { 481 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 482 483 if (clk_enable(bank->clock)) 484 panic(); 485 486 /* 487 * Save GPIO configuration bits spread over the few bank registers. 488 * 1bit fields are accessed at bit position being the pin index. 489 * 2bit fields are accessed at bit position being twice the pin index. 490 * 4bit fields are accessed at bit position being fourth the pin index 491 * but accessed from 2 32bit registers at incremental addresses. 492 */ 493 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 494 GPIO_MODE_MASK; 495 496 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 497 498 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 499 (pin << 1)) & GPIO_OSPEED_MASK; 500 501 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 502 GPIO_PUPD_PULL_MASK; 503 504 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 505 506 if (pin < GPIO_ALT_LOWER_LIMIT) 507 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 508 (pin << 2)) & GPIO_ALTERNATE_MASK; 509 else 510 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 511 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 512 GPIO_ALTERNATE_MASK; 513 514 clk_disable(bank->clock); 515 } 516 517 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 518 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 519 { 520 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 521 uint32_t exceptions = 0; 522 523 if (clk_enable(bank->clock)) 524 panic(); 525 exceptions = cpu_spin_lock_xsave(&gpio_lock); 526 527 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 528 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 529 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 530 SHIFT_U32(cfg->mode, pin << 1)); 531 532 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 533 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 534 SHIFT_U32(cfg->otype, pin)); 535 536 /* Load GPIO Output Speed confguration, 2bit value */ 537 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 538 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 539 SHIFT_U32(cfg->ospeed, pin << 1)); 540 541 /* Load GPIO pull configuration, 2bit value */ 542 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 543 SHIFT_U32(cfg->pupd, pin << 1)); 544 545 /* Load pin mux Alternate Function configuration, 4bit value */ 546 if (pin < GPIO_ALT_LOWER_LIMIT) { 547 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 548 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 549 SHIFT_U32(cfg->af, pin << 2)); 550 } else { 551 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 552 553 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 554 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 555 SHIFT_U32(cfg->af, shift)); 556 } 557 558 /* Load GPIO Output direction confuguration, 1bit */ 559 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 560 561 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 562 clk_disable(bank->clock); 563 } 564 565 /* Count pins described in the DT node and get related data if possible */ 566 static int get_pinctrl_from_fdt(const void *fdt, int node, 567 struct stm32_pinctrl *pinctrl, size_t count) 568 { 569 const fdt32_t *cuint = NULL; 570 const fdt32_t *slewrate = NULL; 571 int len = 0; 572 uint32_t i = 0; 573 uint32_t speed = GPIO_OSPEED_LOW; 574 uint32_t pull = GPIO_PUPD_NO_PULL; 575 size_t found = 0; 576 577 cuint = fdt_getprop(fdt, node, "pinmux", &len); 578 if (!cuint) 579 return -FDT_ERR_NOTFOUND; 580 581 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 582 if (slewrate) 583 speed = fdt32_to_cpu(*slewrate); 584 585 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 586 pull = GPIO_PUPD_PULL_UP; 587 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 588 pull = GPIO_PUPD_PULL_DOWN; 589 590 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 591 uint32_t pincfg = 0; 592 uint32_t bank = 0; 593 uint32_t pin = 0; 594 uint32_t mode = 0; 595 uint32_t alternate = 0; 596 uint32_t odata = 0; 597 bool opendrain = false; 598 599 pincfg = fdt32_to_cpu(*cuint); 600 cuint++; 601 602 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 603 604 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 605 606 mode = pincfg & DT_GPIO_MODE_MASK; 607 608 switch (mode) { 609 case 0: 610 mode = GPIO_MODE_INPUT; 611 break; 612 case 1: 613 case 2: 614 case 3: 615 case 4: 616 case 5: 617 case 6: 618 case 7: 619 case 8: 620 case 9: 621 case 10: 622 case 11: 623 case 12: 624 case 13: 625 case 14: 626 case 15: 627 case 16: 628 alternate = mode - 1U; 629 mode = GPIO_MODE_ALTERNATE; 630 break; 631 case 17: 632 mode = GPIO_MODE_ANALOG; 633 break; 634 default: 635 mode = GPIO_MODE_OUTPUT; 636 break; 637 } 638 639 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 640 opendrain = true; 641 642 if (fdt_getprop(fdt, node, "output-high", NULL) && 643 mode == GPIO_MODE_INPUT) { 644 mode = GPIO_MODE_OUTPUT; 645 odata = 1; 646 } 647 648 if (fdt_getprop(fdt, node, "output-low", NULL) && 649 mode == GPIO_MODE_INPUT) { 650 mode = GPIO_MODE_OUTPUT; 651 odata = 0; 652 } 653 654 if (found < count) { 655 struct stm32_pinctrl *ref = &pinctrl[found]; 656 657 ref->bank = (uint8_t)bank; 658 ref->pin = (uint8_t)pin; 659 ref->cfg.mode = mode; 660 if (opendrain) 661 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; 662 else 663 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; 664 ref->cfg.ospeed = speed; 665 ref->cfg.pupd = pull; 666 ref->cfg.od = odata; 667 ref->cfg.af = alternate; 668 } 669 670 found++; 671 } 672 673 return (int)found; 674 } 675 676 static TEE_Result consumed_gpios_pm(enum pm_op op, 677 unsigned int pm_hint __unused, 678 const struct pm_callback_handle *pm_hdl) 679 { 680 struct stm32_gpio_pm_state *handle = pm_hdl->handle; 681 unsigned int bank_id = handle->gpio_pinctrl.bank; 682 unsigned int pin = handle->gpio_pinctrl.pin; 683 struct gpio_chip *chip = &stm32_gpio_get_bank(bank_id)->gpio_chip; 684 685 if (op == PM_OP_RESUME) { 686 set_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); 687 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) 688 stm32_gpio_set_level(chip, pin, handle->level); 689 } else { 690 get_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); 691 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) 692 handle->level = stm32_gpio_get_level(chip, pin); 693 } 694 695 return TEE_SUCCESS; 696 } 697 DECLARE_KEEP_PAGER(consumed_gpios_pm); 698 699 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 700 struct gpio **out_gpio) 701 { 702 TEE_Result res = TEE_ERROR_GENERIC; 703 const char *consumer_name __maybe_unused = NULL; 704 struct stm32_gpio_pm_state *reg_state = NULL; 705 struct stm32_gpio_pm_state *state = NULL; 706 struct stm32_gpio_bank *bank = data; 707 struct gpio *gpio = NULL; 708 unsigned int shift_1b = 0; 709 unsigned int shift_2b = 0; 710 uint32_t exceptions = 0; 711 uint32_t otype = 0; 712 uint32_t pupd = 0; 713 uint32_t mode = 0; 714 715 consumer_name = fdt_get_name(pargs->fdt, pargs->consumer_node, 716 NULL); 717 718 res = gpio_dt_alloc_pin(pargs, &gpio); 719 if (res) 720 return res; 721 722 if (gpio->pin >= bank->ngpios) { 723 DMSG("Invalid GPIO reference"); 724 free(gpio); 725 return TEE_ERROR_GENERIC; 726 } 727 728 state = calloc(1, sizeof(*state)); 729 if (!state) { 730 free(gpio); 731 return TEE_ERROR_OUT_OF_MEMORY; 732 } 733 734 SLIST_FOREACH(reg_state, &consumed_gpios_head, link) { 735 if (reg_state->gpio_pinctrl.bank == bank->bank_id && 736 reg_state->gpio_pinctrl.pin == gpio->pin) { 737 EMSG("node %s: GPIO %c%u is used by another device", 738 fdt_get_name(pargs->fdt, pargs->consumer_node, 739 NULL), 740 bank->bank_id + 'A', gpio->pin); 741 free(state); 742 free(gpio); 743 return TEE_ERROR_GENERIC; 744 } 745 } 746 747 res = acquire_rif_semaphore_if_needed(bank, gpio->pin); 748 if (res) { 749 EMSG("Failed to acquire GPIO %c%u semaphore for node %s", 750 bank->bank_id + 'A', gpio->pin, consumer_name); 751 return res; 752 } 753 754 state->gpio_pinctrl.pin = gpio->pin; 755 state->gpio_pinctrl.bank = bank->bank_id; 756 SLIST_INSERT_HEAD(&consumed_gpios_head, state, link); 757 758 register_pm_driver_cb(consumed_gpios_pm, state, "stm32-gpio-state"); 759 760 shift_1b = gpio->pin; 761 shift_2b = SHIFT_U32(gpio->pin, 1); 762 763 if (gpio->dt_flags & GPIO_PULL_UP) 764 pupd = GPIO_PUPD_PULL_UP; 765 else if (gpio->dt_flags & GPIO_PULL_DOWN) 766 pupd = GPIO_PUPD_PULL_DOWN; 767 else 768 pupd = GPIO_PUPD_NO_PULL; 769 770 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 771 otype = GPIO_OTYPE_OPEN_DRAIN; 772 else 773 otype = GPIO_OTYPE_PUSH_PULL; 774 775 if (clk_enable(bank->clock)) 776 panic(); 777 exceptions = cpu_spin_lock_xsave(&gpio_lock); 778 779 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 780 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 781 SHIFT_U32(mode, shift_2b)); 782 783 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 784 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 785 SHIFT_U32(otype, shift_1b)); 786 787 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 788 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 789 SHIFT_U32(pupd, shift_2b)); 790 791 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 792 clk_disable(bank->clock); 793 794 gpio->chip = &bank->gpio_chip; 795 796 *out_gpio = gpio; 797 798 return TEE_SUCCESS; 799 } 800 801 /* Get bank ID from bank node property st,bank-name or panic on failure */ 802 static unsigned int dt_get_bank_id(const void *fdt, int node) 803 { 804 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 805 const fdt32_t *cuint = NULL; 806 int len = 0; 807 808 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 809 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 810 if (!cuint || (len != dt_name_len + 1)) 811 panic("Missing/wrong st,bank-name property"); 812 813 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 814 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 815 panic("Wrong st,bank-name property"); 816 817 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 818 } 819 820 /* 821 * Return whether or not the GPIO bank related to a DT node is already 822 * registered in the GPIO bank link. 823 */ 824 static bool bank_is_registered(const void *fdt, int node) 825 { 826 unsigned int bank_id = dt_get_bank_id(fdt, node); 827 struct stm32_gpio_bank *bank = NULL; 828 829 STAILQ_FOREACH(bank, &bank_list, link) 830 if (bank->bank_id == bank_id) 831 return true; 832 833 return false; 834 } 835 836 #ifdef CFG_STM32_RIF 837 static TEE_Result handle_available_semaphores(struct stm32_gpio_bank *bank, 838 uint32_t gpios_mask) 839 { 840 TEE_Result res = TEE_ERROR_GENERIC; 841 uint32_t cidcfgr = 0; 842 unsigned int i = 0; 843 844 for (i = 0 ; i < bank->ngpios; i++) { 845 if (!(BIT(i) & gpios_mask)) 846 continue; 847 848 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(i)); 849 850 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 851 continue; 852 853 if (!(io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(i))) { 854 res = stm32_rif_release_semaphore(bank->base + 855 GPIO_SEMCR(i), 856 MAX_CID_SUPPORTED); 857 if (res) { 858 EMSG("Cannot release semaphore for resource %u", 859 i); 860 return res; 861 } 862 } else { 863 res = stm32_rif_acquire_semaphore(bank->base + 864 GPIO_SEMCR(i), 865 MAX_CID_SUPPORTED); 866 if (res) { 867 EMSG("Cannot acquire semaphore for resource %u", 868 i); 869 return res; 870 } 871 } 872 } 873 874 return TEE_SUCCESS; 875 } 876 877 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank, 878 uint32_t gpios_mask) 879 { 880 TEE_Result res = TEE_ERROR_GENERIC; 881 unsigned int i = 0; 882 883 if (!bank->rif_cfg) 884 return TEE_SUCCESS; 885 886 if (clk_enable(bank->clock)) 887 panic(); 888 889 if (bank->is_tdcid) { 890 for (i = 0; i < bank->ngpios; i++) { 891 if (!(BIT(i) & gpios_mask)) 892 continue; 893 894 /* 895 * When TDCID, OP-TEE should be the one to set the CID 896 * filtering configuration. Clearing previous 897 * configuration prevents undesired events during the 898 * only legitimate configuration. 899 */ 900 io_clrbits32(bank->base + GPIO_CIDCFGR(i), 901 GPIO_CIDCFGR_CONF_MASK); 902 } 903 } else { 904 res = handle_available_semaphores(bank, gpios_mask); 905 if (res) 906 panic(); 907 } 908 909 /* Security and privilege RIF configuration */ 910 io_mask32(bank->base + GPIO_PRIVCFGR_OFFSET, 911 bank->rif_cfg->priv_conf[0], gpios_mask); 912 io_mask32(bank->base + GPIO_SECR_OFFSET, 913 bank->rif_cfg->sec_conf[0], gpios_mask); 914 915 if (!bank->is_tdcid) { 916 res = TEE_SUCCESS; 917 goto out; 918 } 919 920 for (i = 0; i < bank->ngpios; i++) { 921 if (!(BIT(i) & gpios_mask)) 922 continue; 923 924 io_clrsetbits32(bank->base + GPIO_CIDCFGR(i), 925 GPIO_CIDCFGR_CONF_MASK, 926 bank->rif_cfg->cid_confs[i]); 927 } 928 929 /* 930 * Lock RIF configuration if configured. This cannot be undone until 931 * next reset. 932 */ 933 io_setbits32(bank->base + GPIO_RCFGLOCKR_OFFSET, 934 bank->rif_cfg->lock_conf[0]); 935 936 res = handle_available_semaphores(bank, gpios_mask); 937 if (res) 938 panic(); 939 940 out: 941 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) { 942 /* Check that RIF config are applied, panic otherwise */ 943 if ((io_read32(bank->base + GPIO_PRIVCFGR_OFFSET) & 944 gpios_mask) != 945 (bank->rif_cfg->priv_conf[0] & gpios_mask)) { 946 EMSG("GPIO bank%c priv conf is incorrect", 947 'A' + bank->bank_id); 948 panic(); 949 } 950 951 if ((io_read32(bank->base + GPIO_SECR_OFFSET) & gpios_mask) != 952 (bank->rif_cfg->sec_conf[0] & gpios_mask)) { 953 EMSG("GPIO bank %c sec conf is incorrect", 954 'A' + bank->bank_id); 955 panic(); 956 } 957 } 958 959 clk_disable(bank->clock); 960 961 return res; 962 } 963 #else /* CFG_STM32_RIF */ 964 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank __unused, 965 uint32_t gpios_mask __unused) 966 { 967 return TEE_SUCCESS; 968 } 969 #endif /* CFG_STM32_RIF */ 970 971 /* Forward reference to stm32_gpio_set_conf_sec() defined below */ 972 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank); 973 974 static TEE_Result stm32_gpio_fw_configure(struct firewall_query *firewall) 975 { 976 struct stm32_gpio_bank *bank = firewall->ctrl->priv; 977 uint32_t firewall_arg = 0; 978 uint32_t gpios_mask = 0; 979 bool secure = true; 980 981 assert(bank->sec_support); 982 983 if (firewall->arg_count != 1) 984 return TEE_ERROR_BAD_PARAMETERS; 985 986 firewall_arg = firewall->args[0]; 987 988 if (bank->rif_cfg) { 989 gpios_mask = BIT(RIF_CHANNEL_ID(firewall_arg)); 990 991 /* We're about to change a specific GPIO config */ 992 bank->rif_cfg->access_mask[0] |= gpios_mask; 993 994 /* 995 * Update bank RIF config with firewall configuration data 996 * and apply it. 997 */ 998 stm32_rif_parse_cfg(firewall_arg, bank->rif_cfg, 999 bank->ngpios); 1000 return apply_rif_config(bank, gpios_mask); 1001 } 1002 1003 /* 1004 * Non RIF GPIO banks use a single cell as a bit mask (bits 0 to 15) 1005 * to define the a group of GPIO pins (one or several) to configure 1006 * for that bank, and GPIO_STM32_NSEC bit flag to set if these pins 1007 * are non-secure (flag set) or non-secure (flag cleared). 1008 */ 1009 gpios_mask = firewall_arg & GENMASK_32(15, 0); 1010 1011 secure = !(firewall_arg & GPIO_STM32_NSEC); 1012 1013 if (gpios_mask & ~GENMASK_32(bank->ngpios, 0)) { 1014 EMSG("Invalid bitmask %#"PRIx32" for GPIO bank %c", 1015 gpios_mask, 'A' + bank->bank_id); 1016 return TEE_ERROR_GENERIC; 1017 } 1018 1019 /* Update bank secure register configuration data and apply it */ 1020 if (secure) 1021 bank->seccfgr |= gpios_mask; 1022 else 1023 bank->seccfgr &= ~gpios_mask; 1024 1025 stm32_gpio_set_conf_sec(bank); 1026 1027 return TEE_SUCCESS; 1028 } 1029 1030 static const struct firewall_controller_ops stm32_gpio_firewall_ops = { 1031 .set_conf = stm32_gpio_fw_configure, 1032 }; 1033 1034 static void stm32_gpio_save_rif_config(struct stm32_gpio_bank *bank) 1035 { 1036 size_t i = 0; 1037 1038 for (i = 0; i < bank->ngpios; i++) 1039 bank->rif_cfg->cid_confs[i] = io_read32(bank->base + 1040 GPIO_CIDCFGR(i)); 1041 1042 bank->rif_cfg->priv_conf[0] = io_read32(bank->base + 1043 GPIO_PRIVCFGR_OFFSET); 1044 bank->rif_cfg->sec_conf[0] = io_read32(bank->base + 1045 GPIO_SECR_OFFSET); 1046 bank->rif_cfg->lock_conf[0] = io_read32(bank->base + 1047 GPIO_RCFGLOCKR_OFFSET); 1048 } 1049 1050 static void stm32_parse_gpio_rif_conf(struct stm32_gpio_bank *bank, 1051 const void *fdt, int node) 1052 { 1053 unsigned int i = 0; 1054 unsigned int nb_rif_conf = 0; 1055 int lenp = 0; 1056 const fdt32_t *cuint = NULL; 1057 1058 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 1059 if (!cuint) { 1060 DMSG("No RIF configuration available"); 1061 return; 1062 } 1063 1064 bank->rif_cfg = calloc(1, sizeof(*bank->rif_cfg)); 1065 if (!bank->rif_cfg) 1066 panic(); 1067 1068 bank->rif_cfg->sec_conf = calloc(1, sizeof(uint32_t)); 1069 if (!bank->rif_cfg->sec_conf) 1070 panic(); 1071 1072 nb_rif_conf = (unsigned int)(lenp / sizeof(uint32_t)); 1073 assert(nb_rif_conf <= bank->ngpios); 1074 1075 bank->rif_cfg->cid_confs = calloc(bank->ngpios, sizeof(uint32_t)); 1076 bank->rif_cfg->priv_conf = calloc(1, sizeof(uint32_t)); 1077 bank->rif_cfg->lock_conf = calloc(1, sizeof(uint32_t)); 1078 bank->rif_cfg->access_mask = calloc(1, sizeof(uint32_t)); 1079 if (!bank->rif_cfg->cid_confs || !bank->rif_cfg->access_mask || 1080 !bank->rif_cfg->priv_conf || !bank->rif_cfg->lock_conf) 1081 panic("Missing memory capacity for GPIOS RIF configuration"); 1082 1083 for (i = 0; i < nb_rif_conf; i++) 1084 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), bank->rif_cfg, 1085 bank->ngpios); 1086 } 1087 1088 /* Get GPIO bank information from the DT */ 1089 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 1090 const void *compat_data, 1091 int range_offset, 1092 struct stm32_gpio_bank **out_bank) 1093 { 1094 const struct bank_compat *compat = compat_data; 1095 TEE_Result res = TEE_ERROR_GENERIC; 1096 struct stm32_gpio_bank *bank = NULL; 1097 const fdt32_t *cuint = NULL; 1098 struct io_pa_va pa_va = { }; 1099 struct clk *clk = NULL; 1100 size_t blen = 0; 1101 paddr_t pa = 0; 1102 int len = 0; 1103 int i = 0; 1104 1105 assert(out_bank); 1106 1107 /* Probe deferrable devices first */ 1108 res = clk_dt_get_by_index(fdt, node, 0, &clk); 1109 if (res) 1110 return res; 1111 1112 bank = calloc(1, sizeof(*bank)); 1113 if (!bank) 1114 return TEE_ERROR_OUT_OF_MEMORY; 1115 1116 if (compat->secure_extended) { 1117 res = stm32_rifsc_check_tdcid(&bank->is_tdcid); 1118 if (res) { 1119 free(bank); 1120 return res; 1121 } 1122 } 1123 1124 /* 1125 * Do not rely *only* on the "reg" property to get the address, 1126 * but consider also the "ranges" translation property 1127 */ 1128 if (fdt_reg_info(fdt, node, &pa, &blen)) 1129 panic("missing reg or reg size property"); 1130 1131 pa_va.pa = pa + range_offset; 1132 1133 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 1134 bank->bank_id = dt_get_bank_id(fdt, node); 1135 bank->clock = clk; 1136 bank->gpio_chip.ops = &stm32_gpio_ops; 1137 bank->sec_support = compat->secure_control; 1138 1139 /* Parse gpio-ranges with its 4 parameters */ 1140 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 1141 len /= sizeof(*cuint); 1142 if (len % 4) 1143 panic("wrong gpio-ranges syntax"); 1144 1145 /* Get the last defined gpio line (offset + nb of pins) */ 1146 for (i = 0; i < len / 4; i++) { 1147 bank->ngpios = MAX(bank->ngpios, 1148 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 1149 fdt32_to_cpu(*(cuint + 3)))); 1150 cuint += 4; 1151 } 1152 1153 if (compat->secure_extended) { 1154 /* RIF configuration */ 1155 bank->base = io_pa_or_va_secure(&pa_va, blen); 1156 1157 stm32_parse_gpio_rif_conf(bank, fdt, node); 1158 } else if (bank->sec_support) { 1159 /* Secure configuration */ 1160 bank->base = io_pa_or_va_secure(&pa_va, blen); 1161 cuint = fdt_getprop(fdt, node, "st,protreg", NULL); 1162 if (cuint) 1163 bank->seccfgr = fdt32_to_cpu(*cuint); 1164 else 1165 DMSG("GPIO bank %c assigned to non-secure", 1166 bank->bank_id + 'A'); 1167 } else { 1168 bank->base = io_pa_or_va_nsec(&pa_va, blen); 1169 } 1170 1171 if (compat->gpioz) 1172 stm32mp_register_gpioz_pin_count(bank->ngpios); 1173 1174 *out_bank = bank; 1175 1176 return TEE_SUCCESS; 1177 } 1178 1179 static TEE_Result stm32_gpio_firewall_register(const void *fdt, int node, 1180 struct stm32_gpio_bank *bank) 1181 { 1182 struct firewall_controller *controller = NULL; 1183 TEE_Result res = TEE_ERROR_GENERIC; 1184 char bank_name[] = "gpio-bank-X"; 1185 char *name = NULL; 1186 1187 if (!IS_ENABLED(CFG_DRIVERS_FIREWALL) || 1188 !bank->sec_support) 1189 return TEE_SUCCESS; 1190 1191 controller = calloc(1, sizeof(*controller)); 1192 if (!controller) 1193 return TEE_ERROR_OUT_OF_MEMORY; 1194 1195 bank_name[sizeof(bank_name) - 2] = 'A' + bank->bank_id; 1196 name = strdup(bank_name); 1197 1198 controller->name = name; 1199 controller->priv = bank; 1200 controller->ops = &stm32_gpio_firewall_ops; 1201 1202 if (!controller->name) 1203 EMSG("Warning: out of memory to store bank name"); 1204 1205 res = firewall_dt_controller_register(fdt, node, controller); 1206 if (res) { 1207 free(name); 1208 free(controller); 1209 } 1210 1211 return res; 1212 } 1213 1214 /* Parse a pinctrl node to register the GPIO banks it describes */ 1215 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 1216 const void *compat_data) 1217 { 1218 TEE_Result res = TEE_SUCCESS; 1219 const fdt32_t *cuint = NULL; 1220 int range_offs = 0; 1221 int b_node = 0; 1222 int len = 0; 1223 1224 /* Read the ranges property (for regs memory translation) */ 1225 cuint = fdt_getprop(fdt, node, "ranges", &len); 1226 if (!cuint) 1227 panic("missing ranges property"); 1228 1229 len /= sizeof(*cuint); 1230 if (len == 3) 1231 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 1232 1233 fdt_for_each_subnode(b_node, fdt, node) { 1234 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 1235 if (cuint) { 1236 /* 1237 * We found a property "gpio-controller" in the node: 1238 * the node is a GPIO bank description, add it to the 1239 * bank list. 1240 */ 1241 struct stm32_gpio_bank *bank = NULL; 1242 1243 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 1244 bank_is_registered(fdt, b_node)) 1245 continue; 1246 1247 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 1248 range_offs, &bank); 1249 if (res) 1250 return res; 1251 1252 /* Registering a provider should not defer probe */ 1253 res = gpio_register_provider(fdt, b_node, 1254 stm32_gpio_get_dt, bank); 1255 if (res) 1256 panic(); 1257 1258 res = stm32_gpio_firewall_register(fdt, b_node, bank); 1259 if (res) 1260 panic(); 1261 1262 STAILQ_INSERT_TAIL(&bank_list, bank, link); 1263 } else { 1264 if (len != -FDT_ERR_NOTFOUND) 1265 panic(); 1266 } 1267 } 1268 1269 return TEE_SUCCESS; 1270 } 1271 1272 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 1273 bool secure) 1274 { 1275 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 1276 uint32_t exceptions = 0; 1277 1278 if (clk_enable(bank->clock)) 1279 panic(); 1280 exceptions = cpu_spin_lock_xsave(&gpio_lock); 1281 1282 if (secure) 1283 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 1284 else 1285 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 1286 1287 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 1288 clk_disable(bank->clock); 1289 } 1290 1291 #ifdef CFG_DRIVERS_PINCTRL 1292 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf) 1293 { 1294 struct stm32_pinctrl_array *ref = conf->priv; 1295 struct stm32_pinctrl *p = ref->pinctrl; 1296 struct stm32_gpio_bank *bank = NULL; 1297 TEE_Result res = TEE_ERROR_GENERIC; 1298 size_t pin_count = ref->count; 1299 size_t n = 0; 1300 bool error = false; 1301 1302 for (n = 0; n < pin_count; n++) { 1303 bank = stm32_gpio_get_bank(p[n].bank); 1304 res = acquire_rif_semaphore_if_needed(bank, p[n].pin); 1305 if (res) { 1306 EMSG("Failed to acquire GPIO %c%u semaphore", 1307 bank->bank_id + 'A', p[n].pin); 1308 error = true; 1309 } 1310 } 1311 1312 if (error) { 1313 for (n = 0; n < pin_count; n++) { 1314 bank = stm32_gpio_get_bank(p[n].bank); 1315 release_rif_semaphore_if_acquired(bank, p[n].pin); 1316 } 1317 1318 return TEE_ERROR_SECURITY; 1319 } 1320 1321 for (n = 0; n < pin_count; n++) 1322 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg); 1323 1324 return TEE_SUCCESS; 1325 } 1326 1327 static void stm32_pinctrl_conf_free(struct pinconf *conf) 1328 { 1329 free(conf); 1330 } 1331 1332 static const struct pinctrl_ops stm32_pinctrl_ops = { 1333 .conf_apply = stm32_pinctrl_conf_apply, 1334 .conf_free = stm32_pinctrl_conf_free, 1335 }; 1336 1337 DECLARE_KEEP_PAGER(stm32_pinctrl_ops); 1338 1339 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl, 1340 unsigned int *bank, unsigned int *pin, 1341 unsigned int *count) 1342 { 1343 size_t conf_index = 0; 1344 size_t pin_count = 0; 1345 size_t n = 0; 1346 1347 assert(count); 1348 if (!pinctrl) 1349 goto out; 1350 1351 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1352 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1353 struct stm32_pinctrl_array *ref = pinconf->priv; 1354 1355 /* Consider only the stm32_gpio pins */ 1356 if (pinconf->ops != &stm32_pinctrl_ops) 1357 continue; 1358 1359 if (bank || pin) { 1360 for (n = 0; n < ref->count; n++) { 1361 if (bank && pin_count < *count) 1362 bank[pin_count] = ref->pinctrl[n].bank; 1363 if (pin && pin_count < *count) 1364 pin[pin_count] = ref->pinctrl[n].pin; 1365 pin_count++; 1366 } 1367 } else { 1368 pin_count += ref->count; 1369 } 1370 } 1371 1372 out: 1373 *count = pin_count; 1374 } 1375 1376 void stm32_pinctrl_set_secure_cfg(struct pinctrl_state *pinctrl, bool secure) 1377 { 1378 size_t conf_index = 0; 1379 1380 if (!pinctrl) 1381 return; 1382 1383 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1384 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1385 struct stm32_pinctrl_array *ref = pinconf->priv; 1386 struct stm32_pinctrl *pc = NULL; 1387 size_t n = 0; 1388 1389 for (n = 0; n < ref->count; n++) { 1390 if (pinconf->ops != &stm32_pinctrl_ops) 1391 continue; 1392 1393 pc = ref->pinctrl + n; 1394 stm32_gpio_set_secure_cfg(pc->bank, pc->pin, secure); 1395 } 1396 } 1397 } 1398 1399 /* Allocate and return a pinctrl configuration from a DT reference */ 1400 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs, 1401 void *data __unused, 1402 struct pinconf **out_pinconf) 1403 { 1404 struct conf { 1405 struct pinconf pinconf; 1406 struct stm32_pinctrl_array array_ref; 1407 } *loc_conf = NULL; 1408 struct stm32_pinctrl *pinctrl = NULL; 1409 struct pinconf *pinconf = NULL; 1410 const void *fdt = NULL; 1411 size_t pin_count = 0; 1412 int pinctrl_node = 0; 1413 int pinmux_node = 0; 1414 int count = 0; 1415 1416 pinctrl_node = pargs->phandle_node; 1417 fdt = pargs->fdt; 1418 assert(fdt && pinctrl_node); 1419 1420 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1421 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count)) 1422 pin_count += (size_t)count / sizeof(uint32_t); 1423 else if (count != -FDT_ERR_NOTFOUND) 1424 panic(); 1425 } 1426 1427 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count); 1428 if (!loc_conf) 1429 return TEE_ERROR_OUT_OF_MEMORY; 1430 1431 pinconf = &loc_conf->pinconf; 1432 pinconf->ops = &stm32_pinctrl_ops; 1433 pinconf->priv = &loc_conf->array_ref; 1434 1435 loc_conf->array_ref.count = pin_count; 1436 pinctrl = loc_conf->array_ref.pinctrl; 1437 1438 count = 0; 1439 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1440 int found = 0; 1441 1442 found = get_pinctrl_from_fdt(fdt, pinmux_node, pinctrl + count, 1443 pin_count - count); 1444 if (found <= 0 && found > ((int)pin_count - count)) { 1445 /* We can't recover from an error here so let's panic */ 1446 panic(); 1447 } 1448 1449 count += found; 1450 } 1451 1452 *out_pinconf = pinconf; 1453 1454 return TEE_SUCCESS; 1455 } 1456 #endif /*CFG_DRIVERS_PINCTRL*/ 1457 1458 static void stm32_gpio_get_conf_sec(struct stm32_gpio_bank *bank) 1459 { 1460 if (bank->sec_support) { 1461 clk_enable(bank->clock); 1462 bank->seccfgr = io_read32(bank->base + GPIO_SECR_OFFSET); 1463 clk_disable(bank->clock); 1464 } 1465 } 1466 1467 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank) 1468 { 1469 if (bank->sec_support) { 1470 clk_enable(bank->clock); 1471 io_write32(bank->base + GPIO_SECR_OFFSET, bank->seccfgr); 1472 clk_disable(bank->clock); 1473 } 1474 } 1475 1476 static TEE_Result stm32_gpio_sec_config_resume(void) 1477 { 1478 TEE_Result res = TEE_ERROR_GENERIC; 1479 struct stm32_gpio_bank *bank = NULL; 1480 1481 STAILQ_FOREACH(bank, &bank_list, link) { 1482 if (bank->rif_cfg) { 1483 if (!bank->is_tdcid) 1484 continue; 1485 1486 bank->rif_cfg->access_mask[0] = GENMASK_32(bank->ngpios, 1487 0); 1488 1489 res = apply_rif_config(bank, 1490 bank->rif_cfg->access_mask[0]); 1491 if (res) { 1492 EMSG("Failed to set GPIO bank %c RIF config", 1493 'A' + bank->bank_id); 1494 return res; 1495 } 1496 } else { 1497 stm32_gpio_set_conf_sec(bank); 1498 } 1499 } 1500 1501 return TEE_SUCCESS; 1502 } 1503 1504 static TEE_Result stm32_gpio_sec_config_suspend(void) 1505 { 1506 struct stm32_gpio_bank *bank = NULL; 1507 1508 STAILQ_FOREACH(bank, &bank_list, link) { 1509 if (bank->rif_cfg) { 1510 if (bank->is_tdcid) 1511 stm32_gpio_save_rif_config(bank); 1512 } else { 1513 stm32_gpio_get_conf_sec(bank); 1514 } 1515 } 1516 1517 return TEE_SUCCESS; 1518 } 1519 1520 static TEE_Result 1521 stm32_gpio_sec_config_pm(enum pm_op op, unsigned int pm_hint, 1522 const struct pm_callback_handle *hdl __unused) 1523 { 1524 TEE_Result ret = TEE_ERROR_GENERIC; 1525 1526 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT)) 1527 return TEE_SUCCESS; 1528 1529 if (op == PM_OP_RESUME) 1530 ret = stm32_gpio_sec_config_resume(); 1531 else 1532 ret = stm32_gpio_sec_config_suspend(); 1533 1534 return ret; 1535 } 1536 DECLARE_KEEP_PAGER(stm32_gpio_sec_config_pm); 1537 1538 /* 1539 * Several pinctrl nodes can be probed. Their bank will be put in the unique 1540 * bank_list. To avoid multiple configuration set for a bank when looping 1541 * over each bank in the bank list, ready is set to true when a bank is 1542 * configured. Therefore, during other bank probes, the configuration won't 1543 * be set again. 1544 */ 1545 static TEE_Result apply_sec_cfg(void) 1546 { 1547 TEE_Result res = TEE_ERROR_GENERIC; 1548 struct stm32_gpio_bank *bank = NULL; 1549 unsigned int pin = 0; 1550 1551 STAILQ_FOREACH(bank, &bank_list, link) { 1552 if (bank->ready) 1553 continue; 1554 1555 if (bank->rif_cfg) { 1556 res = apply_rif_config(bank, 1557 bank->rif_cfg->access_mask[0]); 1558 if (res) { 1559 EMSG("Failed to set GPIO bank %c RIF config", 1560 'A' + bank->bank_id); 1561 STAILQ_REMOVE(&bank_list, bank, stm32_gpio_bank, 1562 link); 1563 free(bank); 1564 return res; 1565 } 1566 1567 /* 1568 * Semaphores for pinctrl and GPIO are taken when 1569 * these are used (pinctrl state applied, GPIO 1570 * consumed) or when an explicit firewall configuration 1571 * is requested through the firewall framework. 1572 * Therefore release here the taken semaphores. 1573 */ 1574 for (pin = 0; pin < bank->ngpios; pin++) 1575 release_rif_semaphore_if_acquired(bank, pin); 1576 1577 } else { 1578 stm32_gpio_set_conf_sec(bank); 1579 } 1580 1581 bank->ready = true; 1582 } 1583 1584 return TEE_SUCCESS; 1585 } 1586 1587 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 1588 const void *compat_data) 1589 { 1590 static bool pm_register; 1591 TEE_Result res = TEE_ERROR_GENERIC; 1592 1593 /* Register GPIO banks described in this pin control node */ 1594 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data); 1595 if (res) 1596 return res; 1597 1598 if (STAILQ_EMPTY(&bank_list)) 1599 DMSG("no gpio bank for that driver"); 1600 else if (apply_sec_cfg()) 1601 panic(); 1602 1603 if (!pm_register) { 1604 /* 1605 * Register to PM once for all probed banks to restore 1606 * their secure configuration. 1607 */ 1608 register_pm_driver_cb(stm32_gpio_sec_config_pm, NULL, 1609 "stm32-gpio-secure-config"); 1610 pm_register = true; 1611 } 1612 1613 #ifdef CFG_DRIVERS_PINCTRL 1614 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get, 1615 (void *)compat_data); 1616 if (res) 1617 panic(); 1618 #endif 1619 1620 return TEE_SUCCESS; 1621 } 1622 1623 static const struct dt_device_match stm32_pinctrl_match_table[] = { 1624 { 1625 .compatible = "st,stm32mp135-pinctrl", 1626 .compat_data = &(struct bank_compat){ 1627 .secure_control = true, 1628 .secure_extended = false, 1629 }, 1630 }, 1631 { 1632 .compatible = "st,stm32mp157-pinctrl", 1633 .compat_data = &(struct bank_compat){ 1634 .secure_control = false, 1635 .secure_extended = false, 1636 }, 1637 }, 1638 { 1639 .compatible = "st,stm32mp157-z-pinctrl", 1640 .compat_data = &(struct bank_compat){ 1641 .gpioz = true, 1642 .secure_control = true, 1643 .secure_extended = false, 1644 }, 1645 }, 1646 { 1647 .compatible = "st,stm32mp257-pinctrl", 1648 .compat_data = &(struct bank_compat){ 1649 .secure_control = true, 1650 .secure_extended = true, 1651 }, 1652 }, 1653 { 1654 .compatible = "st,stm32mp257-z-pinctrl", 1655 .compat_data = &(struct bank_compat){ 1656 .gpioz = true, 1657 .secure_control = true, 1658 .secure_extended = true, 1659 }, 1660 }, 1661 { } 1662 }; 1663 1664 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 1665 .name = "stm32_gpio-pinctrl", 1666 .type = DT_DRIVER_PINCTRL, 1667 .match_table = stm32_pinctrl_match_table, 1668 .probe = stm32_pinctrl_probe, 1669 }; 1670