1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2024, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <compiler.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/firewall.h> 13 #include <drivers/gpio.h> 14 #include <drivers/pinctrl.h> 15 #include <drivers/stm32_gpio.h> 16 #include <drivers/stm32_rif.h> 17 #include <dt-bindings/gpio/stm32mp_gpio.h> 18 #include <io.h> 19 #include <kernel/dt.h> 20 #include <kernel/boot.h> 21 #include <kernel/panic.h> 22 #include <kernel/pm.h> 23 #include <kernel/spinlock.h> 24 #include <libfdt.h> 25 #include <mm/core_memprot.h> 26 #include <stdbool.h> 27 #include <stdint.h> 28 #include <stm32_util.h> 29 #include <sys/queue.h> 30 #include <trace.h> 31 #include <util.h> 32 33 #ifndef CFG_DRIVERS_GPIO 34 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 35 #endif 36 37 #define GPIO_PIN_MAX 15 38 39 #define GPIO_MODER_OFFSET U(0x00) 40 #define GPIO_OTYPER_OFFSET U(0x04) 41 #define GPIO_OSPEEDR_OFFSET U(0x08) 42 #define GPIO_PUPDR_OFFSET U(0x0c) 43 #define GPIO_IDR_OFFSET U(0x10) 44 #define GPIO_ODR_OFFSET U(0x14) 45 #define GPIO_BSRR_OFFSET U(0x18) 46 #define GPIO_AFRL_OFFSET U(0x20) 47 #define GPIO_AFRH_OFFSET U(0x24) 48 #define GPIO_SECR_OFFSET U(0x30) 49 #define GPIO_PRIVCFGR_OFFSET U(0x34) 50 #define GPIO_RCFGLOCKR_OFFSET U(0x38) 51 #define GPIO_CIDCFGR(x) (U(0x50) + U(0x8) * (x)) 52 #define GPIO_SEMCR(x) (U(0x54) + U(0x8) * (x)) 53 54 #define GPIO_ALT_LOWER_LIMIT U(0x8) 55 56 /* 57 * CIDCFGR register bitfields 58 */ 59 #define GPIO_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16) 60 #define GPIO_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 61 #define GPIO_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | _CIDCFGR_SEMEN | \ 62 GPIO_CIDCFGR_SCID_MASK | \ 63 GPIO_CIDCFGR_SEMWL_MASK) 64 65 /* 66 * PRIVCFGR register bitfields 67 */ 68 #define GPIO_PRIVCFGR_MASK GENMASK_32(15, 0) 69 70 /* 71 * SECCFGR register bitfields 72 */ 73 #define GPIO_SECCFGR_MASK GENMASK_32(15, 0) 74 75 /* 76 * RCFGLOCKR register bitfields 77 */ 78 #define GPIO_RCFGLOCKR_MASK GENMASK_32(15, 0) 79 80 /* 81 * SEMCR register bitfields 82 */ 83 #define GPIO_SEMCR_SCID_M GENMASK_32(6, 4) 84 85 #define GPIO_MODE_MASK GENMASK_32(1, 0) 86 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 87 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 88 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 89 90 #define DT_GPIO_BANK_SHIFT U(12) 91 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 92 #define DT_GPIO_PIN_SHIFT U(8) 93 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 94 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 95 96 #define DT_GPIO_BANK_NAME0 "GPIOA" 97 98 #define GPIO_MODE_INPUT U(0x0) 99 #define GPIO_MODE_OUTPUT U(0x1) 100 #define GPIO_MODE_ALTERNATE U(0x2) 101 #define GPIO_MODE_ANALOG U(0x3) 102 103 #define GPIO_OTYPE_PUSH_PULL U(0x0) 104 #define GPIO_OTYPE_OPEN_DRAIN U(0x1) 105 106 #define GPIO_OSPEED_LOW U(0x0) 107 #define GPIO_OSPEED_MEDIUM U(0x1) 108 #define GPIO_OSPEED_HIGH U(0x2) 109 #define GPIO_OSPEED_VERY_HIGH U(0x3) 110 111 #define GPIO_PUPD_NO_PULL U(0x0) 112 #define GPIO_PUPD_PULL_UP U(0x1) 113 #define GPIO_PUPD_PULL_DOWN U(0x2) 114 115 #define GPIO_OD_LEVEL_LOW U(0x0) 116 #define GPIO_OD_LEVEL_HIGH U(0x1) 117 118 #define GPIO_MAX_CID_SUPPORTED U(3) 119 120 /* 121 * GPIO configuration description structured as single 16bit word 122 * for efficient save/restore when GPIO pin suspends or resumes. 123 * 124 * @mode: One of GPIO_MODE_* 125 * @otype: One of GPIO_OTYPE_* 126 * @ospeed: One of GPIO_OSPEED_* 127 * @pupd: One of GPIO_PUPD_* 128 * @od: One of GPIO_OD_* 129 * @af: Alternate function numerical ID between 0 and 15 130 */ 131 struct gpio_cfg { 132 uint16_t mode: 2; 133 uint16_t otype: 1; 134 uint16_t ospeed: 2; 135 uint16_t pupd: 2; 136 uint16_t od: 1; 137 uint16_t af: 4; 138 }; 139 140 /* 141 * Description of a pin and its muxing 142 * 143 * @bank: GPIO bank identifier as assigned by the platform 144 * @pin: Pin number in the GPIO bank 145 * @cfg: Pin configuration 146 */ 147 struct stm32_pinctrl { 148 uint8_t bank; 149 uint8_t pin; 150 struct gpio_cfg cfg; 151 }; 152 153 /* 154 * struct stm32_pinctrl_array - Array of pins in a pin control state 155 * @count: Number of cells in @pinctrl 156 * @pinctrl: Pin control configuration 157 */ 158 struct stm32_pinctrl_array { 159 size_t count; 160 struct stm32_pinctrl pinctrl[]; 161 }; 162 163 /** 164 * struct stm32_gpio_bank - GPIO bank instance 165 * 166 * @base: base address of the GPIO controller registers. 167 * @clock: clock identifier. 168 * @gpio_chip: GPIO chip reference for that GPIO bank 169 * @ngpios: number of GPIOs. 170 * @bank_id: Id of the bank. 171 * @lock: lock protecting the GPIO bank access. 172 * @rif_cfg: RIF configuration data 173 * @seccfgr: non-RIF bank secure configuration data 174 * @sec_support: True if bank supports pin security protection, else false 175 * @ready: True if configuration is applied, else false 176 * @is_tdcid: True if OP-TEE runs as Trusted Domain CID 177 * @link: Link in bank list 178 */ 179 struct stm32_gpio_bank { 180 vaddr_t base; 181 struct clk *clock; 182 struct gpio_chip gpio_chip; 183 unsigned int ngpios; 184 unsigned int bank_id; 185 unsigned int lock; 186 struct rif_conf_data *rif_cfg; 187 uint32_t seccfgr; 188 bool sec_support; 189 bool ready; 190 bool is_tdcid; 191 STAILQ_ENTRY(stm32_gpio_bank) link; 192 }; 193 194 /* 195 * struct stm32_gpio_pm_state - Consumed GPIO for PM purpose 196 * @gpio_pinctrl: Reference and configuration state for a consumed GPIO 197 * @level: GPIO level 198 * @link: Link in consumed GPIO list 199 */ 200 struct stm32_gpio_pm_state { 201 struct stm32_pinctrl gpio_pinctrl; 202 uint8_t level; 203 SLIST_ENTRY(stm32_gpio_pm_state) link; 204 }; 205 206 /** 207 * Compatibility information of supported banks 208 * 209 * @gpioz: True if bank is a GPIOZ bank 210 * @secure_control: Identify GPIO security bank capability. 211 * @secure_extended: Identify RIF presence. 212 */ 213 struct bank_compat { 214 bool gpioz; 215 bool secure_control; 216 bool secure_extended; 217 }; 218 219 static unsigned int gpio_lock; 220 221 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 222 STAILQ_HEAD_INITIALIZER(bank_list); 223 224 static SLIST_HEAD(, stm32_gpio_pm_state) consumed_gpios_head; 225 226 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 227 228 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 229 { 230 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 231 } 232 233 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 234 unsigned int gpio_pin) 235 { 236 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 237 enum gpio_level level = GPIO_LEVEL_HIGH; 238 unsigned int reg_offset = 0; 239 unsigned int mode = 0; 240 241 assert(gpio_pin < bank->ngpios); 242 243 if (clk_enable(bank->clock)) 244 panic(); 245 246 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 247 GPIO_MODE_MASK; 248 249 switch (mode) { 250 case GPIO_MODE_INPUT: 251 reg_offset = GPIO_IDR_OFFSET; 252 break; 253 case GPIO_MODE_OUTPUT: 254 reg_offset = GPIO_ODR_OFFSET; 255 break; 256 default: 257 panic(); 258 } 259 260 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 261 level = GPIO_LEVEL_HIGH; 262 else 263 level = GPIO_LEVEL_LOW; 264 265 clk_disable(bank->clock); 266 267 return level; 268 } 269 270 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 271 enum gpio_level level) 272 { 273 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 274 275 assert(gpio_pin < bank->ngpios); 276 277 if (clk_enable(bank->clock)) 278 panic(); 279 280 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 281 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 282 283 if (level == GPIO_LEVEL_HIGH) 284 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 285 else 286 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 287 288 clk_disable(bank->clock); 289 } 290 291 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 292 unsigned int gpio_pin) 293 { 294 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 295 uint32_t mode = 0; 296 297 assert(gpio_pin < bank->ngpios); 298 299 if (clk_enable(bank->clock)) 300 panic(); 301 302 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 303 GPIO_MODE_MASK; 304 305 clk_disable(bank->clock); 306 307 switch (mode) { 308 case GPIO_MODE_INPUT: 309 return GPIO_DIR_IN; 310 case GPIO_MODE_OUTPUT: 311 return GPIO_DIR_OUT; 312 default: 313 panic(); 314 } 315 } 316 317 static void stm32_gpio_set_direction(struct gpio_chip *chip, 318 unsigned int gpio_pin, 319 enum gpio_dir direction) 320 { 321 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 322 uint32_t exceptions = 0; 323 uint32_t mode = 0; 324 325 assert(gpio_pin < bank->ngpios); 326 327 if (direction == GPIO_DIR_IN) 328 mode = GPIO_MODE_INPUT; 329 else 330 mode = GPIO_MODE_OUTPUT; 331 332 if (clk_enable(bank->clock)) 333 panic(); 334 exceptions = cpu_spin_lock_xsave(&gpio_lock); 335 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 336 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 337 SHIFT_U32(mode, gpio_pin << 1)); 338 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 339 clk_disable(bank->clock); 340 } 341 342 /* Forward reference to the PM callback handler for consumed GPIOs */ 343 static TEE_Result consumed_gpios_pm(enum pm_op op, unsigned int pm_hint, 344 const struct pm_callback_handle *pm_hdl); 345 346 static void stm32_gpio_put_gpio(struct gpio_chip *chip, struct gpio *gpio) 347 { 348 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 349 struct stm32_gpio_pm_state *tstate = NULL; 350 struct stm32_gpio_pm_state *state = NULL; 351 uint32_t exceptions = 0; 352 353 assert(is_stm32_gpio_chip(chip)); 354 355 exceptions = cpu_spin_lock_xsave(&gpio_lock); 356 357 SLIST_FOREACH_SAFE(state, &consumed_gpios_head, link, tstate) { 358 if (state->gpio_pinctrl.bank == bank->bank_id && 359 state->gpio_pinctrl.pin == gpio->pin) { 360 SLIST_REMOVE(&consumed_gpios_head, state, 361 stm32_gpio_pm_state, link); 362 unregister_pm_driver_cb(consumed_gpios_pm, state); 363 free(state); 364 free(gpio); 365 break; 366 } 367 } 368 assert(state); 369 370 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 371 } 372 373 static const struct gpio_ops stm32_gpio_ops = { 374 .get_direction = stm32_gpio_get_direction, 375 .set_direction = stm32_gpio_set_direction, 376 .get_value = stm32_gpio_get_level, 377 .set_value = stm32_gpio_set_level, 378 .put = stm32_gpio_put_gpio, 379 }; 380 381 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 382 { 383 return chip && chip->ops == &stm32_gpio_ops; 384 } 385 386 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 387 { 388 struct stm32_gpio_bank *bank = NULL; 389 390 STAILQ_FOREACH(bank, &bank_list, link) 391 if (bank_id == bank->bank_id) 392 return bank; 393 394 panic(); 395 } 396 397 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 398 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 399 { 400 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 401 402 if (clk_enable(bank->clock)) 403 panic(); 404 405 /* 406 * Save GPIO configuration bits spread over the few bank registers. 407 * 1bit fields are accessed at bit position being the pin index. 408 * 2bit fields are accessed at bit position being twice the pin index. 409 * 4bit fields are accessed at bit position being fourth the pin index 410 * but accessed from 2 32bit registers at incremental addresses. 411 */ 412 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 413 GPIO_MODE_MASK; 414 415 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 416 417 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 418 (pin << 1)) & GPIO_OSPEED_MASK; 419 420 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 421 GPIO_PUPD_PULL_MASK; 422 423 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 424 425 if (pin < GPIO_ALT_LOWER_LIMIT) 426 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 427 (pin << 2)) & GPIO_ALTERNATE_MASK; 428 else 429 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 430 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 431 GPIO_ALTERNATE_MASK; 432 433 clk_disable(bank->clock); 434 } 435 436 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 437 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 438 { 439 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 440 uint32_t exceptions = 0; 441 442 if (clk_enable(bank->clock)) 443 panic(); 444 exceptions = cpu_spin_lock_xsave(&gpio_lock); 445 446 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 447 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 448 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 449 SHIFT_U32(cfg->mode, pin << 1)); 450 451 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 452 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 453 SHIFT_U32(cfg->otype, pin)); 454 455 /* Load GPIO Output Speed confguration, 2bit value */ 456 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 457 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 458 SHIFT_U32(cfg->ospeed, pin << 1)); 459 460 /* Load GPIO pull configuration, 2bit value */ 461 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 462 SHIFT_U32(cfg->pupd, pin << 1)); 463 464 /* Load pin mux Alternate Function configuration, 4bit value */ 465 if (pin < GPIO_ALT_LOWER_LIMIT) { 466 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 467 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 468 SHIFT_U32(cfg->af, pin << 2)); 469 } else { 470 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 471 472 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 473 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 474 SHIFT_U32(cfg->af, shift)); 475 } 476 477 /* Load GPIO Output direction confuguration, 1bit */ 478 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 479 480 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 481 clk_disable(bank->clock); 482 } 483 484 /* Count pins described in the DT node and get related data if possible */ 485 static int get_pinctrl_from_fdt(const void *fdt, int node, 486 struct stm32_pinctrl *pinctrl, size_t count) 487 { 488 const fdt32_t *cuint = NULL; 489 const fdt32_t *slewrate = NULL; 490 int len = 0; 491 uint32_t i = 0; 492 uint32_t speed = GPIO_OSPEED_LOW; 493 uint32_t pull = GPIO_PUPD_NO_PULL; 494 size_t found = 0; 495 496 cuint = fdt_getprop(fdt, node, "pinmux", &len); 497 if (!cuint) 498 return -FDT_ERR_NOTFOUND; 499 500 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 501 if (slewrate) 502 speed = fdt32_to_cpu(*slewrate); 503 504 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 505 pull = GPIO_PUPD_PULL_UP; 506 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 507 pull = GPIO_PUPD_PULL_DOWN; 508 509 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 510 uint32_t pincfg = 0; 511 uint32_t bank = 0; 512 uint32_t pin = 0; 513 uint32_t mode = 0; 514 uint32_t alternate = 0; 515 uint32_t odata = 0; 516 bool opendrain = false; 517 518 pincfg = fdt32_to_cpu(*cuint); 519 cuint++; 520 521 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 522 523 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 524 525 mode = pincfg & DT_GPIO_MODE_MASK; 526 527 switch (mode) { 528 case 0: 529 mode = GPIO_MODE_INPUT; 530 break; 531 case 1: 532 case 2: 533 case 3: 534 case 4: 535 case 5: 536 case 6: 537 case 7: 538 case 8: 539 case 9: 540 case 10: 541 case 11: 542 case 12: 543 case 13: 544 case 14: 545 case 15: 546 case 16: 547 alternate = mode - 1U; 548 mode = GPIO_MODE_ALTERNATE; 549 break; 550 case 17: 551 mode = GPIO_MODE_ANALOG; 552 break; 553 default: 554 mode = GPIO_MODE_OUTPUT; 555 break; 556 } 557 558 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 559 opendrain = true; 560 561 if (fdt_getprop(fdt, node, "output-high", NULL) && 562 mode == GPIO_MODE_INPUT) { 563 mode = GPIO_MODE_OUTPUT; 564 odata = 1; 565 } 566 567 if (fdt_getprop(fdt, node, "output-low", NULL) && 568 mode == GPIO_MODE_INPUT) { 569 mode = GPIO_MODE_OUTPUT; 570 odata = 0; 571 } 572 573 if (found < count) { 574 struct stm32_pinctrl *ref = &pinctrl[found]; 575 576 ref->bank = (uint8_t)bank; 577 ref->pin = (uint8_t)pin; 578 ref->cfg.mode = mode; 579 if (opendrain) 580 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; 581 else 582 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; 583 ref->cfg.ospeed = speed; 584 ref->cfg.pupd = pull; 585 ref->cfg.od = odata; 586 ref->cfg.af = alternate; 587 } 588 589 found++; 590 } 591 592 return (int)found; 593 } 594 595 static TEE_Result consumed_gpios_pm(enum pm_op op, 596 unsigned int pm_hint __unused, 597 const struct pm_callback_handle *pm_hdl) 598 { 599 struct stm32_gpio_pm_state *handle = pm_hdl->handle; 600 unsigned int bank_id = handle->gpio_pinctrl.bank; 601 unsigned int pin = handle->gpio_pinctrl.pin; 602 struct gpio_chip *chip = &stm32_gpio_get_bank(bank_id)->gpio_chip; 603 604 if (op == PM_OP_RESUME) { 605 set_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); 606 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) 607 stm32_gpio_set_level(chip, pin, handle->level); 608 } else { 609 get_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); 610 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) 611 handle->level = stm32_gpio_get_level(chip, pin); 612 } 613 614 return TEE_SUCCESS; 615 } 616 DECLARE_KEEP_PAGER(consumed_gpios_pm); 617 618 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 619 struct gpio **out_gpio) 620 { 621 TEE_Result res = TEE_ERROR_GENERIC; 622 struct stm32_gpio_pm_state *reg_state = NULL; 623 struct stm32_gpio_pm_state *state = NULL; 624 struct stm32_gpio_bank *bank = data; 625 struct gpio *gpio = NULL; 626 unsigned int shift_1b = 0; 627 unsigned int shift_2b = 0; 628 uint32_t exceptions = 0; 629 uint32_t otype = 0; 630 uint32_t pupd = 0; 631 uint32_t mode = 0; 632 633 res = gpio_dt_alloc_pin(pargs, &gpio); 634 if (res) 635 return res; 636 637 if (gpio->pin >= bank->ngpios) { 638 DMSG("Invalid GPIO reference"); 639 free(gpio); 640 return TEE_ERROR_GENERIC; 641 } 642 643 state = calloc(1, sizeof(*state)); 644 if (!state) { 645 free(gpio); 646 return TEE_ERROR_OUT_OF_MEMORY; 647 } 648 649 SLIST_FOREACH(reg_state, &consumed_gpios_head, link) { 650 if (reg_state->gpio_pinctrl.bank == bank->bank_id && 651 reg_state->gpio_pinctrl.pin == gpio->pin) { 652 EMSG("node %s: GPIO %c%u is used by another device", 653 fdt_get_name(pargs->fdt, pargs->consumer_node, 654 NULL), 655 bank->bank_id + 'A', gpio->pin); 656 free(state); 657 free(gpio); 658 return TEE_ERROR_GENERIC; 659 } 660 } 661 662 state->gpio_pinctrl.pin = gpio->pin; 663 state->gpio_pinctrl.bank = bank->bank_id; 664 SLIST_INSERT_HEAD(&consumed_gpios_head, state, link); 665 666 register_pm_driver_cb(consumed_gpios_pm, state, "stm32-gpio-state"); 667 668 shift_1b = gpio->pin; 669 shift_2b = SHIFT_U32(gpio->pin, 1); 670 671 if (gpio->dt_flags & GPIO_PULL_UP) 672 pupd = GPIO_PUPD_PULL_UP; 673 else if (gpio->dt_flags & GPIO_PULL_DOWN) 674 pupd = GPIO_PUPD_PULL_DOWN; 675 else 676 pupd = GPIO_PUPD_NO_PULL; 677 678 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 679 otype = GPIO_OTYPE_OPEN_DRAIN; 680 else 681 otype = GPIO_OTYPE_PUSH_PULL; 682 683 if (clk_enable(bank->clock)) 684 panic(); 685 exceptions = cpu_spin_lock_xsave(&gpio_lock); 686 687 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 688 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 689 SHIFT_U32(mode, shift_2b)); 690 691 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 692 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 693 SHIFT_U32(otype, shift_1b)); 694 695 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 696 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 697 SHIFT_U32(pupd, shift_2b)); 698 699 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 700 clk_disable(bank->clock); 701 702 gpio->chip = &bank->gpio_chip; 703 704 *out_gpio = gpio; 705 706 return TEE_SUCCESS; 707 } 708 709 /* Get bank ID from bank node property st,bank-name or panic on failure */ 710 static unsigned int dt_get_bank_id(const void *fdt, int node) 711 { 712 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 713 const fdt32_t *cuint = NULL; 714 int len = 0; 715 716 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 717 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 718 if (!cuint || (len != dt_name_len + 1)) 719 panic("Missing/wrong st,bank-name property"); 720 721 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 722 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 723 panic("Wrong st,bank-name property"); 724 725 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 726 } 727 728 /* 729 * Return whether or not the GPIO bank related to a DT node is already 730 * registered in the GPIO bank link. 731 */ 732 static bool bank_is_registered(const void *fdt, int node) 733 { 734 unsigned int bank_id = dt_get_bank_id(fdt, node); 735 struct stm32_gpio_bank *bank = NULL; 736 737 STAILQ_FOREACH(bank, &bank_list, link) 738 if (bank->bank_id == bank_id) 739 return true; 740 741 return false; 742 } 743 744 #ifdef CFG_STM32_RIF 745 static TEE_Result handle_available_semaphores(struct stm32_gpio_bank *bank, 746 uint32_t gpios_mask) 747 { 748 TEE_Result res = TEE_ERROR_GENERIC; 749 uint32_t cidcfgr = 0; 750 unsigned int i = 0; 751 752 for (i = 0 ; i < bank->ngpios; i++) { 753 if (!(BIT(i) & gpios_mask)) 754 continue; 755 756 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(i)); 757 758 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 759 continue; 760 761 if (!(io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(i))) { 762 res = stm32_rif_release_semaphore(bank->base + 763 GPIO_SEMCR(i), 764 MAX_CID_SUPPORTED); 765 if (res) { 766 EMSG("Cannot release semaphore for resource %u", 767 i); 768 return res; 769 } 770 } else { 771 res = stm32_rif_acquire_semaphore(bank->base + 772 GPIO_SEMCR(i), 773 MAX_CID_SUPPORTED); 774 if (res) { 775 EMSG("Cannot acquire semaphore for resource %u", 776 i); 777 return res; 778 } 779 } 780 } 781 782 return TEE_SUCCESS; 783 } 784 785 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank, 786 uint32_t gpios_mask) 787 { 788 TEE_Result res = TEE_ERROR_GENERIC; 789 unsigned int i = 0; 790 791 if (!bank->rif_cfg) 792 return TEE_SUCCESS; 793 794 if (clk_enable(bank->clock)) 795 panic(); 796 797 if (bank->is_tdcid) { 798 for (i = 0; i < bank->ngpios; i++) { 799 if (!(BIT(i) & gpios_mask)) 800 continue; 801 802 /* 803 * When TDCID, OP-TEE should be the one to set the CID 804 * filtering configuration. Clearing previous 805 * configuration prevents undesired events during the 806 * only legitimate configuration. 807 */ 808 io_clrbits32(bank->base + GPIO_CIDCFGR(i), 809 GPIO_CIDCFGR_CONF_MASK); 810 } 811 } else { 812 res = handle_available_semaphores(bank, gpios_mask); 813 if (res) 814 panic(); 815 } 816 817 /* Security and privilege RIF configuration */ 818 io_mask32(bank->base + GPIO_PRIVCFGR_OFFSET, 819 bank->rif_cfg->priv_conf[0], gpios_mask); 820 io_mask32(bank->base + GPIO_SECR_OFFSET, 821 bank->rif_cfg->sec_conf[0], gpios_mask); 822 823 if (!bank->is_tdcid) { 824 res = TEE_SUCCESS; 825 goto out; 826 } 827 828 for (i = 0; i < bank->ngpios; i++) { 829 if (!(BIT(i) & gpios_mask)) 830 continue; 831 832 io_clrsetbits32(bank->base + GPIO_CIDCFGR(i), 833 GPIO_CIDCFGR_CONF_MASK, 834 bank->rif_cfg->cid_confs[i]); 835 } 836 837 /* 838 * Lock RIF configuration if configured. This cannot be undone until 839 * next reset. 840 */ 841 io_setbits32(bank->base + GPIO_RCFGLOCKR_OFFSET, 842 bank->rif_cfg->lock_conf[0]); 843 844 res = handle_available_semaphores(bank, gpios_mask); 845 if (res) 846 panic(); 847 848 out: 849 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) { 850 /* Check that RIF config are applied, panic otherwise */ 851 if ((io_read32(bank->base + GPIO_PRIVCFGR_OFFSET) & 852 gpios_mask) != 853 (bank->rif_cfg->priv_conf[0] & gpios_mask)) { 854 EMSG("GPIO bank%c priv conf is incorrect", 855 'A' + bank->bank_id); 856 panic(); 857 } 858 859 if ((io_read32(bank->base + GPIO_SECR_OFFSET) & gpios_mask) != 860 (bank->rif_cfg->sec_conf[0] & gpios_mask)) { 861 EMSG("GPIO bank %c sec conf is incorrect", 862 'A' + bank->bank_id); 863 panic(); 864 } 865 } 866 867 clk_disable(bank->clock); 868 869 return res; 870 } 871 #else /* CFG_STM32_RIF */ 872 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank __unused, 873 uint32_t gpios_mask __unused) 874 { 875 return TEE_SUCCESS; 876 } 877 #endif /* CFG_STM32_RIF */ 878 879 /* Forward reference to stm32_gpio_set_conf_sec() defined below */ 880 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank); 881 882 static TEE_Result stm32_gpio_fw_configure(struct firewall_query *firewall) 883 { 884 struct stm32_gpio_bank *bank = firewall->ctrl->priv; 885 uint32_t firewall_arg = 0; 886 uint32_t gpios_mask = 0; 887 bool secure = true; 888 889 assert(bank->sec_support); 890 891 if (firewall->arg_count != 1) 892 return TEE_ERROR_BAD_PARAMETERS; 893 894 firewall_arg = firewall->args[0]; 895 896 if (bank->rif_cfg) { 897 gpios_mask = BIT(RIF_CHANNEL_ID(firewall_arg)); 898 899 /* We're about to change a specific GPIO config */ 900 bank->rif_cfg->access_mask[0] |= gpios_mask; 901 902 /* 903 * Update bank RIF config with firewall configuration data 904 * and apply it. 905 */ 906 stm32_rif_parse_cfg(firewall_arg, bank->rif_cfg, 907 bank->ngpios); 908 return apply_rif_config(bank, gpios_mask); 909 } 910 911 /* 912 * Non RIF GPIO banks use a single cell as a bit mask (bits 0 to 15) 913 * to define the a group of GPIO pins (one or several) to configure 914 * for that bank, and GPIO_STM32_NSEC bit flag to set if these pins 915 * are non-secure (flag set) or non-secure (flag cleared). 916 */ 917 gpios_mask = firewall_arg & GENMASK_32(15, 0); 918 919 secure = !(firewall_arg & GPIO_STM32_NSEC); 920 921 if (gpios_mask & ~GENMASK_32(bank->ngpios, 0)) { 922 EMSG("Invalid bitmask %#"PRIx32" for GPIO bank %c", 923 gpios_mask, 'A' + bank->bank_id); 924 return TEE_ERROR_GENERIC; 925 } 926 927 /* Update bank secure register configuration data and apply it */ 928 if (secure) 929 bank->seccfgr |= gpios_mask; 930 else 931 bank->seccfgr &= ~gpios_mask; 932 933 stm32_gpio_set_conf_sec(bank); 934 935 return TEE_SUCCESS; 936 } 937 938 static const struct firewall_controller_ops stm32_gpio_firewall_ops = { 939 .set_conf = stm32_gpio_fw_configure, 940 }; 941 942 static void stm32_gpio_save_rif_config(struct stm32_gpio_bank *bank) 943 { 944 size_t i = 0; 945 946 for (i = 0; i < bank->ngpios; i++) 947 bank->rif_cfg->cid_confs[i] = io_read32(bank->base + 948 GPIO_CIDCFGR(i)); 949 950 bank->rif_cfg->priv_conf[0] = io_read32(bank->base + 951 GPIO_PRIVCFGR_OFFSET); 952 bank->rif_cfg->sec_conf[0] = io_read32(bank->base + 953 GPIO_SECR_OFFSET); 954 bank->rif_cfg->lock_conf[0] = io_read32(bank->base + 955 GPIO_RCFGLOCKR_OFFSET); 956 } 957 958 static void stm32_parse_gpio_rif_conf(struct stm32_gpio_bank *bank, 959 const void *fdt, int node) 960 { 961 unsigned int i = 0; 962 unsigned int nb_rif_conf = 0; 963 int lenp = 0; 964 const fdt32_t *cuint = NULL; 965 966 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 967 if (!cuint) { 968 DMSG("No RIF configuration available"); 969 return; 970 } 971 972 bank->rif_cfg = calloc(1, sizeof(*bank->rif_cfg)); 973 if (!bank->rif_cfg) 974 panic(); 975 976 bank->rif_cfg->sec_conf = calloc(1, sizeof(uint32_t)); 977 if (!bank->rif_cfg->sec_conf) 978 panic(); 979 980 nb_rif_conf = (unsigned int)(lenp / sizeof(uint32_t)); 981 assert(nb_rif_conf <= bank->ngpios); 982 983 bank->rif_cfg->cid_confs = calloc(bank->ngpios, sizeof(uint32_t)); 984 bank->rif_cfg->priv_conf = calloc(1, sizeof(uint32_t)); 985 bank->rif_cfg->lock_conf = calloc(1, sizeof(uint32_t)); 986 bank->rif_cfg->access_mask = calloc(1, sizeof(uint32_t)); 987 if (!bank->rif_cfg->cid_confs || !bank->rif_cfg->access_mask || 988 !bank->rif_cfg->priv_conf || !bank->rif_cfg->lock_conf) 989 panic("Missing memory capacity for GPIOS RIF configuration"); 990 991 for (i = 0; i < nb_rif_conf; i++) 992 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), bank->rif_cfg, 993 bank->ngpios); 994 } 995 996 /* Get GPIO bank information from the DT */ 997 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 998 const void *compat_data, 999 int range_offset, 1000 struct stm32_gpio_bank **out_bank) 1001 { 1002 const struct bank_compat *compat = compat_data; 1003 TEE_Result res = TEE_ERROR_GENERIC; 1004 struct stm32_gpio_bank *bank = NULL; 1005 const fdt32_t *cuint = NULL; 1006 struct io_pa_va pa_va = { }; 1007 struct clk *clk = NULL; 1008 size_t blen = 0; 1009 paddr_t pa = 0; 1010 int len = 0; 1011 int i = 0; 1012 1013 assert(out_bank); 1014 1015 /* Probe deferrable devices first */ 1016 res = clk_dt_get_by_index(fdt, node, 0, &clk); 1017 if (res) 1018 return res; 1019 1020 bank = calloc(1, sizeof(*bank)); 1021 if (!bank) 1022 return TEE_ERROR_OUT_OF_MEMORY; 1023 1024 if (compat->secure_extended) { 1025 res = stm32_rifsc_check_tdcid(&bank->is_tdcid); 1026 if (res) { 1027 free(bank); 1028 return res; 1029 } 1030 } 1031 1032 /* 1033 * Do not rely *only* on the "reg" property to get the address, 1034 * but consider also the "ranges" translation property 1035 */ 1036 if (fdt_reg_info(fdt, node, &pa, &blen)) 1037 panic("missing reg or reg size property"); 1038 1039 pa_va.pa = pa + range_offset; 1040 1041 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 1042 bank->bank_id = dt_get_bank_id(fdt, node); 1043 bank->clock = clk; 1044 bank->gpio_chip.ops = &stm32_gpio_ops; 1045 bank->sec_support = compat->secure_control; 1046 1047 /* Parse gpio-ranges with its 4 parameters */ 1048 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 1049 len /= sizeof(*cuint); 1050 if (len % 4) 1051 panic("wrong gpio-ranges syntax"); 1052 1053 /* Get the last defined gpio line (offset + nb of pins) */ 1054 for (i = 0; i < len / 4; i++) { 1055 bank->ngpios = MAX(bank->ngpios, 1056 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 1057 fdt32_to_cpu(*(cuint + 3)))); 1058 cuint += 4; 1059 } 1060 1061 if (compat->secure_extended) { 1062 /* RIF configuration */ 1063 bank->base = io_pa_or_va_secure(&pa_va, blen); 1064 1065 stm32_parse_gpio_rif_conf(bank, fdt, node); 1066 } else if (bank->sec_support) { 1067 /* Secure configuration */ 1068 bank->base = io_pa_or_va_secure(&pa_va, blen); 1069 cuint = fdt_getprop(fdt, node, "st,protreg", NULL); 1070 if (cuint) 1071 bank->seccfgr = fdt32_to_cpu(*cuint); 1072 else 1073 DMSG("GPIO bank %c assigned to non-secure", 1074 bank->bank_id + 'A'); 1075 } else { 1076 bank->base = io_pa_or_va_nsec(&pa_va, blen); 1077 } 1078 1079 if (compat->gpioz) 1080 stm32mp_register_gpioz_pin_count(bank->ngpios); 1081 1082 *out_bank = bank; 1083 1084 return TEE_SUCCESS; 1085 } 1086 1087 static TEE_Result stm32_gpio_firewall_register(const void *fdt, int node, 1088 struct stm32_gpio_bank *bank) 1089 { 1090 struct firewall_controller *controller = NULL; 1091 TEE_Result res = TEE_ERROR_GENERIC; 1092 char bank_name[] = "gpio-bank-X"; 1093 char *name = NULL; 1094 1095 if (!IS_ENABLED(CFG_DRIVERS_FIREWALL) || 1096 !bank->sec_support) 1097 return TEE_SUCCESS; 1098 1099 controller = calloc(1, sizeof(*controller)); 1100 if (!controller) 1101 return TEE_ERROR_OUT_OF_MEMORY; 1102 1103 bank_name[sizeof(bank_name) - 2] = 'A' + bank->bank_id; 1104 name = strdup(bank_name); 1105 1106 controller->name = name; 1107 controller->priv = bank; 1108 controller->ops = &stm32_gpio_firewall_ops; 1109 1110 if (!controller->name) 1111 EMSG("Warning: out of memory to store bank name"); 1112 1113 res = firewall_dt_controller_register(fdt, node, controller); 1114 if (res) { 1115 free(name); 1116 free(controller); 1117 } 1118 1119 return res; 1120 } 1121 1122 /* Parse a pinctrl node to register the GPIO banks it describes */ 1123 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 1124 const void *compat_data) 1125 { 1126 TEE_Result res = TEE_SUCCESS; 1127 const fdt32_t *cuint = NULL; 1128 int range_offs = 0; 1129 int b_node = 0; 1130 int len = 0; 1131 1132 /* Read the ranges property (for regs memory translation) */ 1133 cuint = fdt_getprop(fdt, node, "ranges", &len); 1134 if (!cuint) 1135 panic("missing ranges property"); 1136 1137 len /= sizeof(*cuint); 1138 if (len == 3) 1139 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 1140 1141 fdt_for_each_subnode(b_node, fdt, node) { 1142 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 1143 if (cuint) { 1144 /* 1145 * We found a property "gpio-controller" in the node: 1146 * the node is a GPIO bank description, add it to the 1147 * bank list. 1148 */ 1149 struct stm32_gpio_bank *bank = NULL; 1150 1151 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 1152 bank_is_registered(fdt, b_node)) 1153 continue; 1154 1155 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 1156 range_offs, &bank); 1157 if (res) 1158 return res; 1159 1160 /* Registering a provider should not defer probe */ 1161 res = gpio_register_provider(fdt, b_node, 1162 stm32_gpio_get_dt, bank); 1163 if (res) 1164 panic(); 1165 1166 res = stm32_gpio_firewall_register(fdt, b_node, bank); 1167 if (res) 1168 panic(); 1169 1170 STAILQ_INSERT_TAIL(&bank_list, bank, link); 1171 } else { 1172 if (len != -FDT_ERR_NOTFOUND) 1173 panic(); 1174 } 1175 } 1176 1177 return TEE_SUCCESS; 1178 } 1179 1180 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 1181 bool secure) 1182 { 1183 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 1184 uint32_t exceptions = 0; 1185 1186 if (clk_enable(bank->clock)) 1187 panic(); 1188 exceptions = cpu_spin_lock_xsave(&gpio_lock); 1189 1190 if (secure) 1191 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 1192 else 1193 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 1194 1195 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 1196 clk_disable(bank->clock); 1197 } 1198 1199 #ifdef CFG_DRIVERS_PINCTRL 1200 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf) 1201 { 1202 struct stm32_pinctrl_array *ref = conf->priv; 1203 struct stm32_pinctrl *p = ref->pinctrl; 1204 size_t pin_count = ref->count; 1205 size_t n = 0; 1206 1207 for (n = 0; n < pin_count; n++) 1208 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg); 1209 1210 return TEE_SUCCESS; 1211 } 1212 1213 static void stm32_pinctrl_conf_free(struct pinconf *conf) 1214 { 1215 free(conf); 1216 } 1217 1218 static const struct pinctrl_ops stm32_pinctrl_ops = { 1219 .conf_apply = stm32_pinctrl_conf_apply, 1220 .conf_free = stm32_pinctrl_conf_free, 1221 }; 1222 1223 DECLARE_KEEP_PAGER(stm32_pinctrl_ops); 1224 1225 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl, 1226 unsigned int *bank, unsigned int *pin, 1227 unsigned int *count) 1228 { 1229 size_t conf_index = 0; 1230 size_t pin_count = 0; 1231 size_t n = 0; 1232 1233 assert(count); 1234 if (!pinctrl) 1235 goto out; 1236 1237 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1238 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1239 struct stm32_pinctrl_array *ref = pinconf->priv; 1240 1241 /* Consider only the stm32_gpio pins */ 1242 if (pinconf->ops != &stm32_pinctrl_ops) 1243 continue; 1244 1245 if (bank || pin) { 1246 for (n = 0; n < ref->count; n++) { 1247 if (bank && pin_count < *count) 1248 bank[pin_count] = ref->pinctrl[n].bank; 1249 if (pin && pin_count < *count) 1250 pin[pin_count] = ref->pinctrl[n].pin; 1251 pin_count++; 1252 } 1253 } else { 1254 pin_count += ref->count; 1255 } 1256 } 1257 1258 out: 1259 *count = pin_count; 1260 } 1261 1262 void stm32_pinctrl_set_secure_cfg(struct pinctrl_state *pinctrl, bool secure) 1263 { 1264 size_t conf_index = 0; 1265 1266 if (!pinctrl) 1267 return; 1268 1269 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1270 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1271 struct stm32_pinctrl_array *ref = pinconf->priv; 1272 struct stm32_pinctrl *pc = NULL; 1273 size_t n = 0; 1274 1275 for (n = 0; n < ref->count; n++) { 1276 if (pinconf->ops != &stm32_pinctrl_ops) 1277 continue; 1278 1279 pc = ref->pinctrl + n; 1280 stm32_gpio_set_secure_cfg(pc->bank, pc->pin, secure); 1281 } 1282 } 1283 } 1284 1285 /* Allocate and return a pinctrl configuration from a DT reference */ 1286 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs, 1287 void *data __unused, 1288 struct pinconf **out_pinconf) 1289 { 1290 struct conf { 1291 struct pinconf pinconf; 1292 struct stm32_pinctrl_array array_ref; 1293 } *loc_conf = NULL; 1294 struct stm32_pinctrl *pinctrl = NULL; 1295 struct pinconf *pinconf = NULL; 1296 const void *fdt = NULL; 1297 size_t pin_count = 0; 1298 int pinctrl_node = 0; 1299 int pinmux_node = 0; 1300 int count = 0; 1301 1302 pinctrl_node = pargs->phandle_node; 1303 fdt = pargs->fdt; 1304 assert(fdt && pinctrl_node); 1305 1306 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1307 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count)) 1308 pin_count += (size_t)count / sizeof(uint32_t); 1309 else if (count != -FDT_ERR_NOTFOUND) 1310 panic(); 1311 } 1312 1313 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count); 1314 if (!loc_conf) 1315 return TEE_ERROR_OUT_OF_MEMORY; 1316 1317 pinconf = &loc_conf->pinconf; 1318 pinconf->ops = &stm32_pinctrl_ops; 1319 pinconf->priv = &loc_conf->array_ref; 1320 1321 loc_conf->array_ref.count = pin_count; 1322 pinctrl = loc_conf->array_ref.pinctrl; 1323 1324 count = 0; 1325 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1326 int found = 0; 1327 1328 found = get_pinctrl_from_fdt(fdt, pinmux_node, pinctrl + count, 1329 pin_count - count); 1330 if (found <= 0 && found > ((int)pin_count - count)) { 1331 /* We can't recover from an error here so let's panic */ 1332 panic(); 1333 } 1334 1335 count += found; 1336 } 1337 1338 *out_pinconf = pinconf; 1339 1340 return TEE_SUCCESS; 1341 } 1342 #endif /*CFG_DRIVERS_PINCTRL*/ 1343 1344 static void stm32_gpio_get_conf_sec(struct stm32_gpio_bank *bank) 1345 { 1346 if (bank->sec_support) { 1347 clk_enable(bank->clock); 1348 bank->seccfgr = io_read32(bank->base + GPIO_SECR_OFFSET); 1349 clk_disable(bank->clock); 1350 } 1351 } 1352 1353 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank) 1354 { 1355 if (bank->sec_support) { 1356 clk_enable(bank->clock); 1357 io_write32(bank->base + GPIO_SECR_OFFSET, bank->seccfgr); 1358 clk_disable(bank->clock); 1359 } 1360 } 1361 1362 static TEE_Result stm32_gpio_sec_config_resume(void) 1363 { 1364 TEE_Result res = TEE_ERROR_GENERIC; 1365 struct stm32_gpio_bank *bank = NULL; 1366 1367 STAILQ_FOREACH(bank, &bank_list, link) { 1368 if (bank->rif_cfg) { 1369 if (!bank->is_tdcid) 1370 continue; 1371 1372 bank->rif_cfg->access_mask[0] = GENMASK_32(bank->ngpios, 1373 0); 1374 1375 res = apply_rif_config(bank, 1376 bank->rif_cfg->access_mask[0]); 1377 if (res) { 1378 EMSG("Failed to set GPIO bank %c RIF config", 1379 'A' + bank->bank_id); 1380 return res; 1381 } 1382 } else { 1383 stm32_gpio_set_conf_sec(bank); 1384 } 1385 } 1386 1387 return TEE_SUCCESS; 1388 } 1389 1390 static TEE_Result stm32_gpio_sec_config_suspend(void) 1391 { 1392 struct stm32_gpio_bank *bank = NULL; 1393 1394 STAILQ_FOREACH(bank, &bank_list, link) { 1395 if (bank->rif_cfg) { 1396 if (bank->is_tdcid) 1397 stm32_gpio_save_rif_config(bank); 1398 } else { 1399 stm32_gpio_get_conf_sec(bank); 1400 } 1401 } 1402 1403 return TEE_SUCCESS; 1404 } 1405 1406 static TEE_Result 1407 stm32_gpio_sec_config_pm(enum pm_op op, unsigned int pm_hint, 1408 const struct pm_callback_handle *hdl __unused) 1409 { 1410 TEE_Result ret = TEE_ERROR_GENERIC; 1411 1412 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT)) 1413 return TEE_SUCCESS; 1414 1415 if (op == PM_OP_RESUME) 1416 ret = stm32_gpio_sec_config_resume(); 1417 else 1418 ret = stm32_gpio_sec_config_suspend(); 1419 1420 return ret; 1421 } 1422 DECLARE_KEEP_PAGER(stm32_gpio_sec_config_pm); 1423 1424 /* 1425 * Several pinctrl nodes can be probed. Their bank will be put in the unique 1426 * bank_list. To avoid multiple configuration set for a bank when looping 1427 * over each bank in the bank list, ready is set to true when a bank is 1428 * configured. Therefore, during other bank probes, the configuration won't 1429 * be set again. 1430 */ 1431 static TEE_Result apply_sec_cfg(void) 1432 { 1433 TEE_Result res = TEE_ERROR_GENERIC; 1434 struct stm32_gpio_bank *bank = NULL; 1435 1436 STAILQ_FOREACH(bank, &bank_list, link) { 1437 if (bank->ready) 1438 continue; 1439 1440 if (bank->rif_cfg) { 1441 res = apply_rif_config(bank, 1442 bank->rif_cfg->access_mask[0]); 1443 if (res) { 1444 EMSG("Failed to set GPIO bank %c RIF config", 1445 'A' + bank->bank_id); 1446 STAILQ_REMOVE(&bank_list, bank, stm32_gpio_bank, 1447 link); 1448 free(bank); 1449 return res; 1450 } 1451 } else { 1452 stm32_gpio_set_conf_sec(bank); 1453 } 1454 1455 bank->ready = true; 1456 } 1457 1458 return TEE_SUCCESS; 1459 } 1460 1461 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 1462 const void *compat_data) 1463 { 1464 static bool pm_register; 1465 TEE_Result res = TEE_ERROR_GENERIC; 1466 1467 /* Register GPIO banks described in this pin control node */ 1468 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data); 1469 if (res) 1470 return res; 1471 1472 if (STAILQ_EMPTY(&bank_list)) 1473 DMSG("no gpio bank for that driver"); 1474 else if (apply_sec_cfg()) 1475 panic(); 1476 1477 if (!pm_register) { 1478 /* 1479 * Register to PM once for all probed banks to restore 1480 * their secure configuration. 1481 */ 1482 register_pm_driver_cb(stm32_gpio_sec_config_pm, NULL, 1483 "stm32-gpio-secure-config"); 1484 pm_register = true; 1485 } 1486 1487 #ifdef CFG_DRIVERS_PINCTRL 1488 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get, 1489 (void *)compat_data); 1490 if (res) 1491 panic(); 1492 #endif 1493 1494 return TEE_SUCCESS; 1495 } 1496 1497 static const struct dt_device_match stm32_pinctrl_match_table[] = { 1498 { 1499 .compatible = "st,stm32mp135-pinctrl", 1500 .compat_data = &(struct bank_compat){ 1501 .secure_control = true, 1502 .secure_extended = false, 1503 }, 1504 }, 1505 { 1506 .compatible = "st,stm32mp157-pinctrl", 1507 .compat_data = &(struct bank_compat){ 1508 .secure_control = false, 1509 .secure_extended = false, 1510 }, 1511 }, 1512 { 1513 .compatible = "st,stm32mp157-z-pinctrl", 1514 .compat_data = &(struct bank_compat){ 1515 .gpioz = true, 1516 .secure_control = true, 1517 .secure_extended = false, 1518 }, 1519 }, 1520 { 1521 .compatible = "st,stm32mp257-pinctrl", 1522 .compat_data = &(struct bank_compat){ 1523 .secure_control = true, 1524 .secure_extended = true, 1525 }, 1526 }, 1527 { 1528 .compatible = "st,stm32mp257-z-pinctrl", 1529 .compat_data = &(struct bank_compat){ 1530 .gpioz = true, 1531 .secure_control = true, 1532 .secure_extended = true, 1533 }, 1534 }, 1535 { } 1536 }; 1537 1538 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 1539 .name = "stm32_gpio-pinctrl", 1540 .type = DT_DRIVER_PINCTRL, 1541 .match_table = stm32_pinctrl_match_table, 1542 .probe = stm32_pinctrl_probe, 1543 }; 1544