1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2024, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <compiler.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/firewall.h> 13 #include <drivers/gpio.h> 14 #include <drivers/pinctrl.h> 15 #include <drivers/stm32_gpio.h> 16 #include <drivers/stm32_rif.h> 17 #include <dt-bindings/gpio/stm32mp_gpio.h> 18 #include <io.h> 19 #include <kernel/dt.h> 20 #include <kernel/boot.h> 21 #include <kernel/panic.h> 22 #include <kernel/pm.h> 23 #include <kernel/spinlock.h> 24 #include <libfdt.h> 25 #include <mm/core_memprot.h> 26 #include <stdbool.h> 27 #include <stdint.h> 28 #include <stm32_util.h> 29 #include <sys/queue.h> 30 #include <trace.h> 31 #include <util.h> 32 33 #ifndef CFG_DRIVERS_GPIO 34 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 35 #endif 36 37 #define GPIO_PIN_MAX 15 38 39 #define GPIO_MODER_OFFSET U(0x00) 40 #define GPIO_OTYPER_OFFSET U(0x04) 41 #define GPIO_OSPEEDR_OFFSET U(0x08) 42 #define GPIO_PUPDR_OFFSET U(0x0c) 43 #define GPIO_IDR_OFFSET U(0x10) 44 #define GPIO_ODR_OFFSET U(0x14) 45 #define GPIO_BSRR_OFFSET U(0x18) 46 #define GPIO_AFRL_OFFSET U(0x20) 47 #define GPIO_AFRH_OFFSET U(0x24) 48 #define GPIO_SECR_OFFSET U(0x30) 49 #define GPIO_PRIVCFGR_OFFSET U(0x34) 50 #define GPIO_RCFGLOCKR_OFFSET U(0x38) 51 #define GPIO_CIDCFGR(x) (U(0x50) + U(0x8) * (x)) 52 #define GPIO_SEMCR(x) (U(0x54) + U(0x8) * (x)) 53 54 #define GPIO_ALT_LOWER_LIMIT U(0x8) 55 56 /* 57 * CIDCFGR register bitfields 58 */ 59 #define GPIO_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16) 60 #define GPIO_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 61 #define GPIO_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | _CIDCFGR_SEMEN | \ 62 GPIO_CIDCFGR_SCID_MASK | \ 63 GPIO_CIDCFGR_SEMWL_MASK) 64 65 /* 66 * PRIVCFGR register bitfields 67 */ 68 #define GPIO_PRIVCFGR_MASK GENMASK_32(15, 0) 69 70 /* 71 * SECCFGR register bitfields 72 */ 73 #define GPIO_SECCFGR_MASK GENMASK_32(15, 0) 74 75 /* 76 * RCFGLOCKR register bitfields 77 */ 78 #define GPIO_RCFGLOCKR_MASK GENMASK_32(15, 0) 79 80 /* 81 * SEMCR register bitfields 82 */ 83 #define GPIO_SEMCR_SCID_M GENMASK_32(6, 4) 84 85 #define GPIO_MODE_MASK GENMASK_32(1, 0) 86 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 87 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 88 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 89 90 #define DT_GPIO_BANK_SHIFT U(12) 91 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 92 #define DT_GPIO_PIN_SHIFT U(8) 93 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 94 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 95 96 #define DT_GPIO_BANK_NAME0 "GPIOA" 97 98 #define GPIO_MODE_INPUT U(0x0) 99 #define GPIO_MODE_OUTPUT U(0x1) 100 #define GPIO_MODE_ALTERNATE U(0x2) 101 #define GPIO_MODE_ANALOG U(0x3) 102 103 #define GPIO_OTYPE_PUSH_PULL U(0x0) 104 #define GPIO_OTYPE_OPEN_DRAIN U(0x1) 105 106 #define GPIO_OSPEED_LOW U(0x0) 107 #define GPIO_OSPEED_MEDIUM U(0x1) 108 #define GPIO_OSPEED_HIGH U(0x2) 109 #define GPIO_OSPEED_VERY_HIGH U(0x3) 110 111 #define GPIO_PUPD_NO_PULL U(0x0) 112 #define GPIO_PUPD_PULL_UP U(0x1) 113 #define GPIO_PUPD_PULL_DOWN U(0x2) 114 115 #define GPIO_OD_LEVEL_LOW U(0x0) 116 #define GPIO_OD_LEVEL_HIGH U(0x1) 117 118 #define GPIO_MAX_CID_SUPPORTED U(3) 119 120 /* 121 * GPIO configuration description structured as single 16bit word 122 * for efficient save/restore when GPIO pin suspends or resumes. 123 * 124 * @mode: One of GPIO_MODE_* 125 * @otype: One of GPIO_OTYPE_* 126 * @ospeed: One of GPIO_OSPEED_* 127 * @pupd: One of GPIO_PUPD_* 128 * @od: One of GPIO_OD_* 129 * @af: Alternate function numerical ID between 0 and 15 130 */ 131 struct gpio_cfg { 132 uint16_t mode: 2; 133 uint16_t otype: 1; 134 uint16_t ospeed: 2; 135 uint16_t pupd: 2; 136 uint16_t od: 1; 137 uint16_t af: 4; 138 }; 139 140 /* 141 * Description of a pin and its muxing 142 * 143 * @bank: GPIO bank identifier as assigned by the platform 144 * @pin: Pin number in the GPIO bank 145 * @cfg: Pin configuration 146 */ 147 struct stm32_pinctrl { 148 uint8_t bank; 149 uint8_t pin; 150 struct gpio_cfg cfg; 151 }; 152 153 /* 154 * struct stm32_pinctrl_array - Array of pins in a pin control state 155 * @count: Number of cells in @pinctrl 156 * @pinctrl: Pin control configuration 157 */ 158 struct stm32_pinctrl_array { 159 size_t count; 160 struct stm32_pinctrl pinctrl[]; 161 }; 162 163 /** 164 * struct stm32_gpio_bank - GPIO bank instance 165 * 166 * @base: base address of the GPIO controller registers. 167 * @clock: clock identifier. 168 * @gpio_chip: GPIO chip reference for that GPIO bank 169 * @ngpios: number of GPIOs. 170 * @bank_id: Id of the bank. 171 * @lock: lock protecting the GPIO bank access. 172 * @rif_cfg: RIF configuration data 173 * @seccfgr: non-RIF bank secure configuration data 174 * @sec_support: True if bank supports pin security protection, else false 175 * @ready: True if configuration is applied, else false 176 * @is_tdcid: True if OP-TEE runs as Trusted Domain CID 177 * @link: Link in bank list 178 */ 179 struct stm32_gpio_bank { 180 vaddr_t base; 181 struct clk *clock; 182 struct gpio_chip gpio_chip; 183 unsigned int ngpios; 184 unsigned int bank_id; 185 unsigned int lock; 186 struct rif_conf_data *rif_cfg; 187 uint32_t seccfgr; 188 bool sec_support; 189 bool ready; 190 bool is_tdcid; 191 STAILQ_ENTRY(stm32_gpio_bank) link; 192 }; 193 194 /* 195 * struct stm32_gpio_pm_state - Consumed GPIO for PM purpose 196 * @gpio_pinctrl: Reference and configuration state for a consumed GPIO 197 * @level: GPIO level 198 * @link: Link in consumed GPIO list 199 */ 200 struct stm32_gpio_pm_state { 201 struct stm32_pinctrl gpio_pinctrl; 202 uint8_t level; 203 SLIST_ENTRY(stm32_gpio_pm_state) link; 204 }; 205 206 /** 207 * Compatibility information of supported banks 208 * 209 * @gpioz: True if bank is a GPIOZ bank 210 * @secure_control: Identify GPIO security bank capability. 211 * @secure_extended: Identify RIF presence. 212 */ 213 struct bank_compat { 214 bool gpioz; 215 bool secure_control; 216 bool secure_extended; 217 }; 218 219 static unsigned int gpio_lock; 220 221 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 222 STAILQ_HEAD_INITIALIZER(bank_list); 223 224 static SLIST_HEAD(, stm32_gpio_pm_state) consumed_gpios_head; 225 226 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 227 228 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 229 { 230 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 231 } 232 233 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 234 unsigned int gpio_pin) 235 { 236 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 237 enum gpio_level level = GPIO_LEVEL_HIGH; 238 unsigned int reg_offset = 0; 239 unsigned int mode = 0; 240 241 assert(gpio_pin < bank->ngpios); 242 243 if (clk_enable(bank->clock)) 244 panic(); 245 246 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 247 GPIO_MODE_MASK; 248 249 switch (mode) { 250 case GPIO_MODE_INPUT: 251 reg_offset = GPIO_IDR_OFFSET; 252 break; 253 case GPIO_MODE_OUTPUT: 254 reg_offset = GPIO_ODR_OFFSET; 255 break; 256 default: 257 panic(); 258 } 259 260 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 261 level = GPIO_LEVEL_HIGH; 262 else 263 level = GPIO_LEVEL_LOW; 264 265 clk_disable(bank->clock); 266 267 return level; 268 } 269 270 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 271 enum gpio_level level) 272 { 273 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 274 275 assert(gpio_pin < bank->ngpios); 276 277 if (clk_enable(bank->clock)) 278 panic(); 279 280 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 281 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 282 283 if (level == GPIO_LEVEL_HIGH) 284 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 285 else 286 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 287 288 clk_disable(bank->clock); 289 } 290 291 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 292 unsigned int gpio_pin) 293 { 294 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 295 uint32_t mode = 0; 296 297 assert(gpio_pin < bank->ngpios); 298 299 if (clk_enable(bank->clock)) 300 panic(); 301 302 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 303 GPIO_MODE_MASK; 304 305 clk_disable(bank->clock); 306 307 switch (mode) { 308 case GPIO_MODE_INPUT: 309 return GPIO_DIR_IN; 310 case GPIO_MODE_OUTPUT: 311 return GPIO_DIR_OUT; 312 default: 313 panic(); 314 } 315 } 316 317 static void stm32_gpio_set_direction(struct gpio_chip *chip, 318 unsigned int gpio_pin, 319 enum gpio_dir direction) 320 { 321 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 322 uint32_t exceptions = 0; 323 uint32_t mode = 0; 324 325 assert(gpio_pin < bank->ngpios); 326 327 if (direction == GPIO_DIR_IN) 328 mode = GPIO_MODE_INPUT; 329 else 330 mode = GPIO_MODE_OUTPUT; 331 332 if (clk_enable(bank->clock)) 333 panic(); 334 exceptions = cpu_spin_lock_xsave(&gpio_lock); 335 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 336 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 337 SHIFT_U32(mode, gpio_pin << 1)); 338 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 339 clk_disable(bank->clock); 340 } 341 342 /* Forward reference to the PM callback handler for consumed GPIOs */ 343 static TEE_Result consumed_gpios_pm(enum pm_op op, unsigned int pm_hint, 344 const struct pm_callback_handle *pm_hdl); 345 346 /* Forward reference to RIF semaphore release helper function */ 347 static void release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank, 348 unsigned int pin); 349 350 static void stm32_gpio_put_gpio(struct gpio_chip *chip, struct gpio *gpio) 351 { 352 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 353 struct stm32_gpio_pm_state *tstate = NULL; 354 struct stm32_gpio_pm_state *state = NULL; 355 uint32_t exceptions = 0; 356 357 assert(is_stm32_gpio_chip(chip)); 358 359 exceptions = cpu_spin_lock_xsave(&gpio_lock); 360 361 SLIST_FOREACH_SAFE(state, &consumed_gpios_head, link, tstate) { 362 if (state->gpio_pinctrl.bank == bank->bank_id && 363 state->gpio_pinctrl.pin == gpio->pin) { 364 SLIST_REMOVE(&consumed_gpios_head, state, 365 stm32_gpio_pm_state, link); 366 unregister_pm_driver_cb(consumed_gpios_pm, state); 367 release_rif_semaphore_if_acquired(bank, gpio->pin); 368 free(state); 369 free(gpio); 370 break; 371 } 372 } 373 assert(state); 374 375 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 376 } 377 378 static const struct gpio_ops stm32_gpio_ops = { 379 .get_direction = stm32_gpio_get_direction, 380 .set_direction = stm32_gpio_set_direction, 381 .get_value = stm32_gpio_get_level, 382 .set_value = stm32_gpio_set_level, 383 .put = stm32_gpio_put_gpio, 384 }; 385 386 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 387 { 388 return chip && chip->ops == &stm32_gpio_ops; 389 } 390 391 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 392 { 393 struct stm32_gpio_bank *bank = NULL; 394 395 STAILQ_FOREACH(bank, &bank_list, link) 396 if (bank_id == bank->bank_id) 397 return bank; 398 399 panic(); 400 } 401 402 #if defined(CFG_STM32_RIF) 403 static bool pin_is_accessible(struct stm32_gpio_bank *bank, unsigned int pin) 404 { 405 bool accessible = false; 406 uint32_t cidcfgr = 0; 407 408 if (!bank->rif_cfg) 409 return true; 410 411 if (clk_enable(bank->clock)) 412 panic(); 413 414 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); 415 416 if (!(cidcfgr & _CIDCFGR_CFEN)) { 417 /* Resource can be accessed when CID filtering is disabled */ 418 accessible = true; 419 } else if (stm32_rif_scid_ok(cidcfgr, GPIO_CIDCFGR_SCID_MASK, 420 RIF_CID1)) { 421 /* Resource can be accessed if CID1 is statically allowed */ 422 accessible = true; 423 } else if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) { 424 /* CID1 is allowed to request the semaphore */ 425 accessible = true; 426 } 427 428 clk_disable(bank->clock); 429 430 return accessible; 431 } 432 433 static TEE_Result acquire_rif_semaphore_if_needed(struct stm32_gpio_bank *bank, 434 unsigned int pin) 435 { 436 TEE_Result res = TEE_SUCCESS; 437 uint32_t cidcfgr = 0; 438 439 if (!bank->rif_cfg) 440 return TEE_SUCCESS; 441 442 res = clk_enable(bank->clock); 443 if (res) 444 return res; 445 446 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); 447 448 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 449 res = stm32_rif_acquire_semaphore(bank->base + GPIO_SEMCR(pin), 450 GPIO_MAX_CID_SUPPORTED); 451 452 clk_disable(bank->clock); 453 454 return res; 455 } 456 457 static uint32_t semaphore_current_cid(struct stm32_gpio_bank *bank, 458 unsigned int pin) 459 { 460 return (io_read32(bank->base + GPIO_SEMCR(pin)) >> 461 _CIDCFGR_SCID_SHIFT) & 462 GENMASK_32(GPIO_MAX_CID_SUPPORTED - 1, 0); 463 } 464 465 static void release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank, 466 unsigned int pin) 467 { 468 TEE_Result res = TEE_ERROR_GENERIC; 469 uint32_t cidcfgr = 0; 470 471 if (!bank->rif_cfg) 472 return; 473 474 res = clk_enable(bank->clock); 475 if (res) 476 panic(); 477 478 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); 479 480 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1) && 481 semaphore_current_cid(bank, pin) == RIF_CID1) { 482 res = stm32_rif_release_semaphore(bank->base + GPIO_SEMCR(pin), 483 GPIO_MAX_CID_SUPPORTED); 484 if (res) { 485 EMSG("Failed to release GPIO %c%u semaphore", 486 bank->bank_id + 'A', pin); 487 panic(); 488 } 489 } 490 491 clk_disable(bank->clock); 492 } 493 #else 494 static bool pin_is_accessible(struct stm32_gpio_bank *bank __unused, 495 unsigned int pin __unused) 496 { 497 return true; 498 } 499 500 static TEE_Result 501 acquire_rif_semaphore_if_needed(struct stm32_gpio_bank *bank __unused, 502 unsigned int pin __unused) 503 { 504 return TEE_SUCCESS; 505 } 506 507 static void 508 release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank __unused, 509 unsigned int pin __unused) 510 { 511 } 512 #endif /*CFG_STM32_RIF*/ 513 514 static bool pin_is_secure(struct stm32_gpio_bank *bank, unsigned int pin) 515 { 516 bool secure = false; 517 518 if (bank->rif_cfg || bank->sec_support) { 519 if (clk_enable(bank->clock)) 520 panic(); 521 522 secure = io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(pin); 523 524 clk_disable(bank->clock); 525 } 526 527 return secure; 528 } 529 530 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 531 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 532 { 533 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 534 535 if (clk_enable(bank->clock)) 536 panic(); 537 538 /* 539 * Save GPIO configuration bits spread over the few bank registers. 540 * 1bit fields are accessed at bit position being the pin index. 541 * 2bit fields are accessed at bit position being twice the pin index. 542 * 4bit fields are accessed at bit position being fourth the pin index 543 * but accessed from 2 32bit registers at incremental addresses. 544 */ 545 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 546 GPIO_MODE_MASK; 547 548 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 549 550 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 551 (pin << 1)) & GPIO_OSPEED_MASK; 552 553 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 554 GPIO_PUPD_PULL_MASK; 555 556 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 557 558 if (pin < GPIO_ALT_LOWER_LIMIT) 559 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 560 (pin << 2)) & GPIO_ALTERNATE_MASK; 561 else 562 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 563 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 564 GPIO_ALTERNATE_MASK; 565 566 clk_disable(bank->clock); 567 } 568 569 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 570 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 571 { 572 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 573 uint32_t exceptions = 0; 574 575 if (clk_enable(bank->clock)) 576 panic(); 577 exceptions = cpu_spin_lock_xsave(&gpio_lock); 578 579 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 580 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 581 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 582 SHIFT_U32(cfg->mode, pin << 1)); 583 584 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 585 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 586 SHIFT_U32(cfg->otype, pin)); 587 588 /* Load GPIO Output Speed confguration, 2bit value */ 589 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 590 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 591 SHIFT_U32(cfg->ospeed, pin << 1)); 592 593 /* Load GPIO pull configuration, 2bit value */ 594 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 595 SHIFT_U32(cfg->pupd, pin << 1)); 596 597 /* Load pin mux Alternate Function configuration, 4bit value */ 598 if (pin < GPIO_ALT_LOWER_LIMIT) { 599 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 600 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 601 SHIFT_U32(cfg->af, pin << 2)); 602 } else { 603 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 604 605 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 606 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 607 SHIFT_U32(cfg->af, shift)); 608 } 609 610 /* Load GPIO Output direction confuguration, 1bit */ 611 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 612 613 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 614 clk_disable(bank->clock); 615 } 616 617 /* Count pins described in the DT node and get related data if possible */ 618 static int get_pinctrl_from_fdt(const void *fdt, int node, 619 struct stm32_pinctrl *pinctrl, size_t count) 620 { 621 const fdt32_t *cuint = NULL; 622 const fdt32_t *slewrate = NULL; 623 int len = 0; 624 uint32_t i = 0; 625 uint32_t speed = GPIO_OSPEED_LOW; 626 uint32_t pull = GPIO_PUPD_NO_PULL; 627 size_t found = 0; 628 629 cuint = fdt_getprop(fdt, node, "pinmux", &len); 630 if (!cuint) 631 return -FDT_ERR_NOTFOUND; 632 633 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 634 if (slewrate) 635 speed = fdt32_to_cpu(*slewrate); 636 637 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 638 pull = GPIO_PUPD_PULL_UP; 639 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 640 pull = GPIO_PUPD_PULL_DOWN; 641 642 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 643 uint32_t pincfg = 0; 644 uint32_t bank = 0; 645 uint32_t pin = 0; 646 uint32_t mode = 0; 647 uint32_t alternate = 0; 648 uint32_t odata = 0; 649 bool opendrain = false; 650 651 pincfg = fdt32_to_cpu(*cuint); 652 cuint++; 653 654 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 655 656 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 657 658 mode = pincfg & DT_GPIO_MODE_MASK; 659 660 switch (mode) { 661 case 0: 662 mode = GPIO_MODE_INPUT; 663 break; 664 case 1: 665 case 2: 666 case 3: 667 case 4: 668 case 5: 669 case 6: 670 case 7: 671 case 8: 672 case 9: 673 case 10: 674 case 11: 675 case 12: 676 case 13: 677 case 14: 678 case 15: 679 case 16: 680 alternate = mode - 1U; 681 mode = GPIO_MODE_ALTERNATE; 682 break; 683 case 17: 684 mode = GPIO_MODE_ANALOG; 685 break; 686 default: 687 mode = GPIO_MODE_OUTPUT; 688 break; 689 } 690 691 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 692 opendrain = true; 693 694 if (fdt_getprop(fdt, node, "output-high", NULL) && 695 mode == GPIO_MODE_INPUT) { 696 mode = GPIO_MODE_OUTPUT; 697 odata = 1; 698 } 699 700 if (fdt_getprop(fdt, node, "output-low", NULL) && 701 mode == GPIO_MODE_INPUT) { 702 mode = GPIO_MODE_OUTPUT; 703 odata = 0; 704 } 705 706 if (found < count) { 707 struct stm32_pinctrl *ref = &pinctrl[found]; 708 709 ref->bank = (uint8_t)bank; 710 ref->pin = (uint8_t)pin; 711 ref->cfg.mode = mode; 712 if (opendrain) 713 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; 714 else 715 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; 716 ref->cfg.ospeed = speed; 717 ref->cfg.pupd = pull; 718 ref->cfg.od = odata; 719 ref->cfg.af = alternate; 720 } 721 722 found++; 723 } 724 725 return (int)found; 726 } 727 728 static TEE_Result consumed_gpios_pm(enum pm_op op, 729 unsigned int pm_hint __unused, 730 const struct pm_callback_handle *pm_hdl) 731 { 732 struct stm32_gpio_pm_state *handle = pm_hdl->handle; 733 unsigned int bank_id = handle->gpio_pinctrl.bank; 734 unsigned int pin = handle->gpio_pinctrl.pin; 735 struct gpio_chip *chip = &stm32_gpio_get_bank(bank_id)->gpio_chip; 736 737 if (op == PM_OP_RESUME) { 738 set_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); 739 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) 740 stm32_gpio_set_level(chip, pin, handle->level); 741 } else { 742 get_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); 743 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) 744 handle->level = stm32_gpio_get_level(chip, pin); 745 } 746 747 return TEE_SUCCESS; 748 } 749 DECLARE_KEEP_PAGER(consumed_gpios_pm); 750 751 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 752 struct gpio **out_gpio) 753 { 754 TEE_Result res = TEE_ERROR_GENERIC; 755 const char *consumer_name __maybe_unused = NULL; 756 struct stm32_gpio_pm_state *reg_state = NULL; 757 struct stm32_gpio_pm_state *state = NULL; 758 struct stm32_gpio_bank *bank = data; 759 struct gpio *gpio = NULL; 760 unsigned int shift_1b = 0; 761 unsigned int shift_2b = 0; 762 bool gpio_secure = true; 763 uint32_t exceptions = 0; 764 uint32_t otype = 0; 765 uint32_t pupd = 0; 766 uint32_t mode = 0; 767 768 consumer_name = fdt_get_name(pargs->fdt, pargs->consumer_node, 769 NULL); 770 771 res = gpio_dt_alloc_pin(pargs, &gpio); 772 if (res) 773 return res; 774 775 if (gpio->pin >= bank->ngpios) { 776 DMSG("Invalid GPIO reference"); 777 free(gpio); 778 return TEE_ERROR_GENERIC; 779 } 780 781 if (gpio->dt_flags & GPIO_STM32_NSEC) 782 gpio_secure = false; 783 784 state = calloc(1, sizeof(*state)); 785 if (!state) { 786 free(gpio); 787 return TEE_ERROR_OUT_OF_MEMORY; 788 } 789 790 SLIST_FOREACH(reg_state, &consumed_gpios_head, link) { 791 if (reg_state->gpio_pinctrl.bank == bank->bank_id && 792 reg_state->gpio_pinctrl.pin == gpio->pin) { 793 EMSG("node %s: GPIO %c%u is used by another device", 794 consumer_name, bank->bank_id + 'A', gpio->pin); 795 free(state); 796 free(gpio); 797 return TEE_ERROR_GENERIC; 798 } 799 } 800 801 if (!pin_is_accessible(bank, gpio->pin)) { 802 EMSG("node %s requests pin on GPIO %c%u which access is denied", 803 consumer_name, bank->bank_id + 'A', gpio->pin); 804 panic(); 805 } 806 807 res = acquire_rif_semaphore_if_needed(bank, gpio->pin); 808 if (res) { 809 EMSG("Failed to acquire GPIO %c%u semaphore for node %s", 810 bank->bank_id + 'A', gpio->pin, consumer_name); 811 return res; 812 } 813 814 if (gpio_secure && !(bank->rif_cfg || bank->sec_support)) { 815 EMSG("node %s requests secure GPIO %c%u that cannot be secured", 816 consumer_name, bank->bank_id + 'A', gpio->pin); 817 panic(); 818 } 819 820 if (gpio_secure != pin_is_secure(bank, gpio->pin)) { 821 IMSG("WARNING: node %s requests %s GPIO %c%u but pin is %s. Check st,protreg in GPIO bank node %s", 822 consumer_name, gpio_secure ? "secure" : "non-secure", 823 bank->bank_id + 'A', gpio->pin, 824 pin_is_secure(bank, gpio->pin) ? "secure" : "non-secure", 825 fdt_get_name(pargs->fdt, pargs->phandle_node, NULL)); 826 if (!IS_ENABLED(CFG_INSECURE)) 827 panic(); 828 } 829 830 state->gpio_pinctrl.pin = gpio->pin; 831 state->gpio_pinctrl.bank = bank->bank_id; 832 SLIST_INSERT_HEAD(&consumed_gpios_head, state, link); 833 834 register_pm_driver_cb(consumed_gpios_pm, state, "stm32-gpio-state"); 835 836 shift_1b = gpio->pin; 837 shift_2b = SHIFT_U32(gpio->pin, 1); 838 839 if (gpio->dt_flags & GPIO_PULL_UP) 840 pupd = GPIO_PUPD_PULL_UP; 841 else if (gpio->dt_flags & GPIO_PULL_DOWN) 842 pupd = GPIO_PUPD_PULL_DOWN; 843 else 844 pupd = GPIO_PUPD_NO_PULL; 845 846 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 847 otype = GPIO_OTYPE_OPEN_DRAIN; 848 else 849 otype = GPIO_OTYPE_PUSH_PULL; 850 851 if (clk_enable(bank->clock)) 852 panic(); 853 exceptions = cpu_spin_lock_xsave(&gpio_lock); 854 855 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 856 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 857 SHIFT_U32(mode, shift_2b)); 858 859 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 860 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 861 SHIFT_U32(otype, shift_1b)); 862 863 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 864 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 865 SHIFT_U32(pupd, shift_2b)); 866 867 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 868 clk_disable(bank->clock); 869 870 gpio->chip = &bank->gpio_chip; 871 872 *out_gpio = gpio; 873 874 return TEE_SUCCESS; 875 } 876 877 /* Get bank ID from bank node property st,bank-name or panic on failure */ 878 static unsigned int dt_get_bank_id(const void *fdt, int node) 879 { 880 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 881 const fdt32_t *cuint = NULL; 882 int len = 0; 883 884 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 885 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 886 if (!cuint || (len != dt_name_len + 1)) 887 panic("Missing/wrong st,bank-name property"); 888 889 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 890 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 891 panic("Wrong st,bank-name property"); 892 893 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 894 } 895 896 /* 897 * Return whether or not the GPIO bank related to a DT node is already 898 * registered in the GPIO bank link. 899 */ 900 static bool bank_is_registered(const void *fdt, int node) 901 { 902 unsigned int bank_id = dt_get_bank_id(fdt, node); 903 struct stm32_gpio_bank *bank = NULL; 904 905 STAILQ_FOREACH(bank, &bank_list, link) 906 if (bank->bank_id == bank_id) 907 return true; 908 909 return false; 910 } 911 912 #ifdef CFG_STM32_RIF 913 static TEE_Result handle_available_semaphores(struct stm32_gpio_bank *bank, 914 uint32_t gpios_mask) 915 { 916 TEE_Result res = TEE_ERROR_GENERIC; 917 uint32_t cidcfgr = 0; 918 unsigned int i = 0; 919 920 for (i = 0 ; i < bank->ngpios; i++) { 921 if (!(BIT(i) & gpios_mask)) 922 continue; 923 924 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(i)); 925 926 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 927 continue; 928 929 if (!(io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(i))) { 930 res = stm32_rif_release_semaphore(bank->base + 931 GPIO_SEMCR(i), 932 MAX_CID_SUPPORTED); 933 if (res) { 934 EMSG("Cannot release semaphore for resource %u", 935 i); 936 return res; 937 } 938 } else { 939 res = stm32_rif_acquire_semaphore(bank->base + 940 GPIO_SEMCR(i), 941 MAX_CID_SUPPORTED); 942 if (res) { 943 EMSG("Cannot acquire semaphore for resource %u", 944 i); 945 return res; 946 } 947 } 948 } 949 950 return TEE_SUCCESS; 951 } 952 953 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank, 954 uint32_t gpios_mask) 955 { 956 TEE_Result res = TEE_ERROR_GENERIC; 957 unsigned int i = 0; 958 959 if (!bank->rif_cfg) 960 return TEE_SUCCESS; 961 962 if (clk_enable(bank->clock)) 963 panic(); 964 965 if (bank->is_tdcid) { 966 for (i = 0; i < bank->ngpios; i++) { 967 if (!(BIT(i) & gpios_mask)) 968 continue; 969 970 /* 971 * When TDCID, OP-TEE should be the one to set the CID 972 * filtering configuration. Clearing previous 973 * configuration prevents undesired events during the 974 * only legitimate configuration. 975 */ 976 io_clrbits32(bank->base + GPIO_CIDCFGR(i), 977 GPIO_CIDCFGR_CONF_MASK); 978 } 979 } else { 980 res = handle_available_semaphores(bank, gpios_mask); 981 if (res) 982 panic(); 983 } 984 985 /* Security and privilege RIF configuration */ 986 io_mask32(bank->base + GPIO_PRIVCFGR_OFFSET, 987 bank->rif_cfg->priv_conf[0], gpios_mask); 988 io_mask32(bank->base + GPIO_SECR_OFFSET, 989 bank->rif_cfg->sec_conf[0], gpios_mask); 990 991 if (!bank->is_tdcid) { 992 res = TEE_SUCCESS; 993 goto out; 994 } 995 996 for (i = 0; i < bank->ngpios; i++) { 997 if (!(BIT(i) & gpios_mask)) 998 continue; 999 1000 io_clrsetbits32(bank->base + GPIO_CIDCFGR(i), 1001 GPIO_CIDCFGR_CONF_MASK, 1002 bank->rif_cfg->cid_confs[i]); 1003 } 1004 1005 /* 1006 * Lock RIF configuration if configured. This cannot be undone until 1007 * next reset. 1008 */ 1009 io_setbits32(bank->base + GPIO_RCFGLOCKR_OFFSET, 1010 bank->rif_cfg->lock_conf[0]); 1011 1012 res = handle_available_semaphores(bank, gpios_mask); 1013 if (res) 1014 panic(); 1015 1016 out: 1017 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) { 1018 /* Check that RIF config are applied, panic otherwise */ 1019 if ((io_read32(bank->base + GPIO_PRIVCFGR_OFFSET) & 1020 gpios_mask) != 1021 (bank->rif_cfg->priv_conf[0] & gpios_mask)) { 1022 EMSG("GPIO bank%c priv conf is incorrect", 1023 'A' + bank->bank_id); 1024 panic(); 1025 } 1026 1027 if ((io_read32(bank->base + GPIO_SECR_OFFSET) & gpios_mask) != 1028 (bank->rif_cfg->sec_conf[0] & gpios_mask)) { 1029 EMSG("GPIO bank %c sec conf is incorrect", 1030 'A' + bank->bank_id); 1031 panic(); 1032 } 1033 } 1034 1035 clk_disable(bank->clock); 1036 1037 return res; 1038 } 1039 #else /* CFG_STM32_RIF */ 1040 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank __unused, 1041 uint32_t gpios_mask __unused) 1042 { 1043 return TEE_SUCCESS; 1044 } 1045 #endif /* CFG_STM32_RIF */ 1046 1047 /* Forward reference to stm32_gpio_set_conf_sec() defined below */ 1048 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank); 1049 1050 static TEE_Result stm32_gpio_fw_configure(struct firewall_query *firewall) 1051 { 1052 struct stm32_gpio_bank *bank = firewall->ctrl->priv; 1053 uint32_t firewall_arg = 0; 1054 uint32_t gpios_mask = 0; 1055 bool secure = true; 1056 1057 assert(bank->sec_support); 1058 1059 if (firewall->arg_count != 1) 1060 return TEE_ERROR_BAD_PARAMETERS; 1061 1062 firewall_arg = firewall->args[0]; 1063 1064 if (bank->rif_cfg) { 1065 gpios_mask = BIT(RIF_CHANNEL_ID(firewall_arg)); 1066 1067 /* We're about to change a specific GPIO config */ 1068 bank->rif_cfg->access_mask[0] |= gpios_mask; 1069 1070 /* 1071 * Update bank RIF config with firewall configuration data 1072 * and apply it. 1073 */ 1074 stm32_rif_parse_cfg(firewall_arg, bank->rif_cfg, 1075 bank->ngpios); 1076 return apply_rif_config(bank, gpios_mask); 1077 } 1078 1079 /* 1080 * Non RIF GPIO banks use a single cell as a bit mask (bits 0 to 15) 1081 * to define the a group of GPIO pins (one or several) to configure 1082 * for that bank, and GPIO_STM32_NSEC bit flag to set if these pins 1083 * are non-secure (flag set) or non-secure (flag cleared). 1084 */ 1085 gpios_mask = firewall_arg & GENMASK_32(15, 0); 1086 1087 secure = !(firewall_arg & GPIO_STM32_NSEC); 1088 1089 if (gpios_mask & ~GENMASK_32(bank->ngpios, 0)) { 1090 EMSG("Invalid bitmask %#"PRIx32" for GPIO bank %c", 1091 gpios_mask, 'A' + bank->bank_id); 1092 return TEE_ERROR_GENERIC; 1093 } 1094 1095 /* Update bank secure register configuration data and apply it */ 1096 if (secure) 1097 bank->seccfgr |= gpios_mask; 1098 else 1099 bank->seccfgr &= ~gpios_mask; 1100 1101 stm32_gpio_set_conf_sec(bank); 1102 1103 return TEE_SUCCESS; 1104 } 1105 1106 static const struct firewall_controller_ops stm32_gpio_firewall_ops = { 1107 .set_conf = stm32_gpio_fw_configure, 1108 }; 1109 1110 static void stm32_gpio_save_rif_config(struct stm32_gpio_bank *bank) 1111 { 1112 size_t i = 0; 1113 1114 for (i = 0; i < bank->ngpios; i++) 1115 bank->rif_cfg->cid_confs[i] = io_read32(bank->base + 1116 GPIO_CIDCFGR(i)); 1117 1118 bank->rif_cfg->priv_conf[0] = io_read32(bank->base + 1119 GPIO_PRIVCFGR_OFFSET); 1120 bank->rif_cfg->sec_conf[0] = io_read32(bank->base + 1121 GPIO_SECR_OFFSET); 1122 bank->rif_cfg->lock_conf[0] = io_read32(bank->base + 1123 GPIO_RCFGLOCKR_OFFSET); 1124 } 1125 1126 static void stm32_parse_gpio_rif_conf(struct stm32_gpio_bank *bank, 1127 const void *fdt, int node) 1128 { 1129 unsigned int i = 0; 1130 unsigned int nb_rif_conf = 0; 1131 int lenp = 0; 1132 const fdt32_t *cuint = NULL; 1133 1134 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 1135 if (!cuint) { 1136 DMSG("No RIF configuration available"); 1137 return; 1138 } 1139 1140 bank->rif_cfg = calloc(1, sizeof(*bank->rif_cfg)); 1141 if (!bank->rif_cfg) 1142 panic(); 1143 1144 bank->rif_cfg->sec_conf = calloc(1, sizeof(uint32_t)); 1145 if (!bank->rif_cfg->sec_conf) 1146 panic(); 1147 1148 nb_rif_conf = (unsigned int)(lenp / sizeof(uint32_t)); 1149 assert(nb_rif_conf <= bank->ngpios); 1150 1151 bank->rif_cfg->cid_confs = calloc(bank->ngpios, sizeof(uint32_t)); 1152 bank->rif_cfg->priv_conf = calloc(1, sizeof(uint32_t)); 1153 bank->rif_cfg->lock_conf = calloc(1, sizeof(uint32_t)); 1154 bank->rif_cfg->access_mask = calloc(1, sizeof(uint32_t)); 1155 if (!bank->rif_cfg->cid_confs || !bank->rif_cfg->access_mask || 1156 !bank->rif_cfg->priv_conf || !bank->rif_cfg->lock_conf) 1157 panic("Missing memory capacity for GPIOS RIF configuration"); 1158 1159 for (i = 0; i < nb_rif_conf; i++) 1160 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), bank->rif_cfg, 1161 bank->ngpios); 1162 } 1163 1164 /* Get GPIO bank information from the DT */ 1165 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 1166 const void *compat_data, 1167 int range_offset, 1168 struct stm32_gpio_bank **out_bank) 1169 { 1170 const struct bank_compat *compat = compat_data; 1171 TEE_Result res = TEE_ERROR_GENERIC; 1172 struct stm32_gpio_bank *bank = NULL; 1173 const fdt32_t *cuint = NULL; 1174 struct io_pa_va pa_va = { }; 1175 struct clk *clk = NULL; 1176 size_t blen = 0; 1177 paddr_t pa = 0; 1178 int len = 0; 1179 int i = 0; 1180 1181 assert(out_bank); 1182 1183 /* Probe deferrable devices first */ 1184 res = clk_dt_get_by_index(fdt, node, 0, &clk); 1185 if (res) 1186 return res; 1187 1188 bank = calloc(1, sizeof(*bank)); 1189 if (!bank) 1190 return TEE_ERROR_OUT_OF_MEMORY; 1191 1192 if (compat->secure_extended) { 1193 res = stm32_rifsc_check_tdcid(&bank->is_tdcid); 1194 if (res) { 1195 free(bank); 1196 return res; 1197 } 1198 } 1199 1200 /* 1201 * Do not rely *only* on the "reg" property to get the address, 1202 * but consider also the "ranges" translation property 1203 */ 1204 if (fdt_reg_info(fdt, node, &pa, &blen)) 1205 panic("missing reg or reg size property"); 1206 1207 pa_va.pa = pa + range_offset; 1208 1209 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 1210 bank->bank_id = dt_get_bank_id(fdt, node); 1211 bank->clock = clk; 1212 bank->gpio_chip.ops = &stm32_gpio_ops; 1213 bank->sec_support = compat->secure_control; 1214 1215 /* Parse gpio-ranges with its 4 parameters */ 1216 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 1217 len /= sizeof(*cuint); 1218 if (len % 4) 1219 panic("wrong gpio-ranges syntax"); 1220 1221 /* Get the last defined gpio line (offset + nb of pins) */ 1222 for (i = 0; i < len / 4; i++) { 1223 bank->ngpios = MAX(bank->ngpios, 1224 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 1225 fdt32_to_cpu(*(cuint + 3)))); 1226 cuint += 4; 1227 } 1228 1229 if (compat->secure_extended) { 1230 /* RIF configuration */ 1231 bank->base = io_pa_or_va_secure(&pa_va, blen); 1232 1233 stm32_parse_gpio_rif_conf(bank, fdt, node); 1234 } else if (bank->sec_support) { 1235 /* Secure configuration */ 1236 bank->base = io_pa_or_va_secure(&pa_va, blen); 1237 cuint = fdt_getprop(fdt, node, "st,protreg", NULL); 1238 if (cuint) 1239 bank->seccfgr = fdt32_to_cpu(*cuint); 1240 else 1241 DMSG("GPIO bank %c assigned to non-secure", 1242 bank->bank_id + 'A'); 1243 } else { 1244 bank->base = io_pa_or_va_nsec(&pa_va, blen); 1245 } 1246 1247 if (compat->gpioz) 1248 stm32mp_register_gpioz_pin_count(bank->ngpios); 1249 1250 *out_bank = bank; 1251 1252 return TEE_SUCCESS; 1253 } 1254 1255 static TEE_Result stm32_gpio_firewall_register(const void *fdt, int node, 1256 struct stm32_gpio_bank *bank) 1257 { 1258 struct firewall_controller *controller = NULL; 1259 TEE_Result res = TEE_ERROR_GENERIC; 1260 char bank_name[] = "gpio-bank-X"; 1261 char *name = NULL; 1262 1263 if (!IS_ENABLED(CFG_DRIVERS_FIREWALL) || 1264 !bank->sec_support) 1265 return TEE_SUCCESS; 1266 1267 controller = calloc(1, sizeof(*controller)); 1268 if (!controller) 1269 return TEE_ERROR_OUT_OF_MEMORY; 1270 1271 bank_name[sizeof(bank_name) - 2] = 'A' + bank->bank_id; 1272 name = strdup(bank_name); 1273 1274 controller->name = name; 1275 controller->priv = bank; 1276 controller->ops = &stm32_gpio_firewall_ops; 1277 1278 if (!controller->name) 1279 EMSG("Warning: out of memory to store bank name"); 1280 1281 res = firewall_dt_controller_register(fdt, node, controller); 1282 if (res) { 1283 free(name); 1284 free(controller); 1285 } 1286 1287 return res; 1288 } 1289 1290 /* Parse a pinctrl node to register the GPIO banks it describes */ 1291 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 1292 const void *compat_data) 1293 { 1294 TEE_Result res = TEE_SUCCESS; 1295 const fdt32_t *cuint = NULL; 1296 int range_offs = 0; 1297 int b_node = 0; 1298 int len = 0; 1299 1300 /* Read the ranges property (for regs memory translation) */ 1301 cuint = fdt_getprop(fdt, node, "ranges", &len); 1302 if (!cuint) 1303 panic("missing ranges property"); 1304 1305 len /= sizeof(*cuint); 1306 if (len == 3) 1307 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 1308 1309 fdt_for_each_subnode(b_node, fdt, node) { 1310 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 1311 if (cuint) { 1312 /* 1313 * We found a property "gpio-controller" in the node: 1314 * the node is a GPIO bank description, add it to the 1315 * bank list. 1316 */ 1317 struct stm32_gpio_bank *bank = NULL; 1318 1319 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 1320 bank_is_registered(fdt, b_node)) 1321 continue; 1322 1323 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 1324 range_offs, &bank); 1325 if (res) 1326 return res; 1327 1328 /* Registering a provider should not defer probe */ 1329 res = gpio_register_provider(fdt, b_node, 1330 stm32_gpio_get_dt, bank); 1331 if (res) 1332 panic(); 1333 1334 res = stm32_gpio_firewall_register(fdt, b_node, bank); 1335 if (res) 1336 panic(); 1337 1338 STAILQ_INSERT_TAIL(&bank_list, bank, link); 1339 } else { 1340 if (len != -FDT_ERR_NOTFOUND) 1341 panic(); 1342 } 1343 } 1344 1345 return TEE_SUCCESS; 1346 } 1347 1348 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 1349 bool secure) 1350 { 1351 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 1352 uint32_t exceptions = 0; 1353 1354 if (clk_enable(bank->clock)) 1355 panic(); 1356 exceptions = cpu_spin_lock_xsave(&gpio_lock); 1357 1358 if (secure) 1359 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 1360 else 1361 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 1362 1363 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 1364 clk_disable(bank->clock); 1365 } 1366 1367 #ifdef CFG_DRIVERS_PINCTRL 1368 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf) 1369 { 1370 struct stm32_pinctrl_array *ref = conf->priv; 1371 struct stm32_pinctrl *p = ref->pinctrl; 1372 struct stm32_gpio_bank *bank = NULL; 1373 TEE_Result res = TEE_ERROR_GENERIC; 1374 size_t pin_count = ref->count; 1375 size_t n = 0; 1376 bool error = false; 1377 1378 for (n = 0; n < pin_count; n++) { 1379 bank = stm32_gpio_get_bank(p[n].bank); 1380 res = acquire_rif_semaphore_if_needed(bank, p[n].pin); 1381 if (res) { 1382 EMSG("Failed to acquire GPIO %c%u semaphore", 1383 bank->bank_id + 'A', p[n].pin); 1384 error = true; 1385 } 1386 } 1387 1388 if (error) { 1389 for (n = 0; n < pin_count; n++) { 1390 bank = stm32_gpio_get_bank(p[n].bank); 1391 release_rif_semaphore_if_acquired(bank, p[n].pin); 1392 } 1393 1394 return TEE_ERROR_SECURITY; 1395 } 1396 1397 for (n = 0; n < pin_count; n++) 1398 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg); 1399 1400 return TEE_SUCCESS; 1401 } 1402 1403 static void stm32_pinctrl_conf_free(struct pinconf *conf) 1404 { 1405 free(conf); 1406 } 1407 1408 static const struct pinctrl_ops stm32_pinctrl_ops = { 1409 .conf_apply = stm32_pinctrl_conf_apply, 1410 .conf_free = stm32_pinctrl_conf_free, 1411 }; 1412 1413 DECLARE_KEEP_PAGER(stm32_pinctrl_ops); 1414 1415 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl, 1416 unsigned int *bank, unsigned int *pin, 1417 unsigned int *count) 1418 { 1419 size_t conf_index = 0; 1420 size_t pin_count = 0; 1421 size_t n = 0; 1422 1423 assert(count); 1424 if (!pinctrl) 1425 goto out; 1426 1427 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1428 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1429 struct stm32_pinctrl_array *ref = pinconf->priv; 1430 1431 /* Consider only the stm32_gpio pins */ 1432 if (pinconf->ops != &stm32_pinctrl_ops) 1433 continue; 1434 1435 if (bank || pin) { 1436 for (n = 0; n < ref->count; n++) { 1437 if (bank && pin_count < *count) 1438 bank[pin_count] = ref->pinctrl[n].bank; 1439 if (pin && pin_count < *count) 1440 pin[pin_count] = ref->pinctrl[n].pin; 1441 pin_count++; 1442 } 1443 } else { 1444 pin_count += ref->count; 1445 } 1446 } 1447 1448 out: 1449 *count = pin_count; 1450 } 1451 1452 void stm32_pinctrl_set_secure_cfg(struct pinctrl_state *pinctrl, bool secure) 1453 { 1454 size_t conf_index = 0; 1455 1456 if (!pinctrl) 1457 return; 1458 1459 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1460 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1461 struct stm32_pinctrl_array *ref = pinconf->priv; 1462 struct stm32_pinctrl *pc = NULL; 1463 size_t n = 0; 1464 1465 for (n = 0; n < ref->count; n++) { 1466 if (pinconf->ops != &stm32_pinctrl_ops) 1467 continue; 1468 1469 pc = ref->pinctrl + n; 1470 stm32_gpio_set_secure_cfg(pc->bank, pc->pin, secure); 1471 } 1472 } 1473 } 1474 1475 /* Allocate and return a pinctrl configuration from a DT reference */ 1476 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs, 1477 void *data __unused, 1478 struct pinconf **out_pinconf) 1479 { 1480 struct conf { 1481 struct pinconf pinconf; 1482 struct stm32_pinctrl_array array_ref; 1483 } *loc_conf = NULL; 1484 struct stm32_pinctrl *pinctrl = NULL; 1485 struct pinconf *pinconf = NULL; 1486 const void *fdt = NULL; 1487 size_t pin_count = 0; 1488 int pinctrl_node = 0; 1489 int pinmux_node = 0; 1490 int count = 0; 1491 1492 pinctrl_node = pargs->phandle_node; 1493 fdt = pargs->fdt; 1494 assert(fdt && pinctrl_node); 1495 1496 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1497 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count)) 1498 pin_count += (size_t)count / sizeof(uint32_t); 1499 else if (count != -FDT_ERR_NOTFOUND) 1500 panic(); 1501 } 1502 1503 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count); 1504 if (!loc_conf) 1505 return TEE_ERROR_OUT_OF_MEMORY; 1506 1507 pinconf = &loc_conf->pinconf; 1508 pinconf->ops = &stm32_pinctrl_ops; 1509 pinconf->priv = &loc_conf->array_ref; 1510 1511 loc_conf->array_ref.count = pin_count; 1512 pinctrl = loc_conf->array_ref.pinctrl; 1513 1514 count = 0; 1515 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1516 int found = 0; 1517 1518 found = get_pinctrl_from_fdt(fdt, pinmux_node, pinctrl + count, 1519 pin_count - count); 1520 if (found <= 0 && found > ((int)pin_count - count)) { 1521 /* We can't recover from an error here so let's panic */ 1522 panic(); 1523 } 1524 1525 count += found; 1526 } 1527 1528 *out_pinconf = pinconf; 1529 1530 return TEE_SUCCESS; 1531 } 1532 #endif /*CFG_DRIVERS_PINCTRL*/ 1533 1534 static void stm32_gpio_get_conf_sec(struct stm32_gpio_bank *bank) 1535 { 1536 if (bank->sec_support) { 1537 clk_enable(bank->clock); 1538 bank->seccfgr = io_read32(bank->base + GPIO_SECR_OFFSET); 1539 clk_disable(bank->clock); 1540 } 1541 } 1542 1543 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank) 1544 { 1545 if (bank->sec_support) { 1546 clk_enable(bank->clock); 1547 io_write32(bank->base + GPIO_SECR_OFFSET, bank->seccfgr); 1548 clk_disable(bank->clock); 1549 } 1550 } 1551 1552 static TEE_Result stm32_gpio_sec_config_resume(void) 1553 { 1554 TEE_Result res = TEE_ERROR_GENERIC; 1555 struct stm32_gpio_bank *bank = NULL; 1556 1557 STAILQ_FOREACH(bank, &bank_list, link) { 1558 if (bank->rif_cfg) { 1559 if (!bank->is_tdcid) 1560 continue; 1561 1562 bank->rif_cfg->access_mask[0] = GENMASK_32(bank->ngpios, 1563 0); 1564 1565 res = apply_rif_config(bank, 1566 bank->rif_cfg->access_mask[0]); 1567 if (res) { 1568 EMSG("Failed to set GPIO bank %c RIF config", 1569 'A' + bank->bank_id); 1570 return res; 1571 } 1572 } else { 1573 stm32_gpio_set_conf_sec(bank); 1574 } 1575 } 1576 1577 return TEE_SUCCESS; 1578 } 1579 1580 static TEE_Result stm32_gpio_sec_config_suspend(void) 1581 { 1582 struct stm32_gpio_bank *bank = NULL; 1583 1584 STAILQ_FOREACH(bank, &bank_list, link) { 1585 if (bank->rif_cfg) { 1586 if (bank->is_tdcid) 1587 stm32_gpio_save_rif_config(bank); 1588 } else { 1589 stm32_gpio_get_conf_sec(bank); 1590 } 1591 } 1592 1593 return TEE_SUCCESS; 1594 } 1595 1596 static TEE_Result 1597 stm32_gpio_sec_config_pm(enum pm_op op, unsigned int pm_hint, 1598 const struct pm_callback_handle *hdl __unused) 1599 { 1600 TEE_Result ret = TEE_ERROR_GENERIC; 1601 1602 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT)) 1603 return TEE_SUCCESS; 1604 1605 if (op == PM_OP_RESUME) 1606 ret = stm32_gpio_sec_config_resume(); 1607 else 1608 ret = stm32_gpio_sec_config_suspend(); 1609 1610 return ret; 1611 } 1612 DECLARE_KEEP_PAGER(stm32_gpio_sec_config_pm); 1613 1614 /* 1615 * Several pinctrl nodes can be probed. Their bank will be put in the unique 1616 * bank_list. To avoid multiple configuration set for a bank when looping 1617 * over each bank in the bank list, ready is set to true when a bank is 1618 * configured. Therefore, during other bank probes, the configuration won't 1619 * be set again. 1620 */ 1621 static TEE_Result apply_sec_cfg(void) 1622 { 1623 TEE_Result res = TEE_ERROR_GENERIC; 1624 struct stm32_gpio_bank *bank = NULL; 1625 unsigned int pin = 0; 1626 1627 STAILQ_FOREACH(bank, &bank_list, link) { 1628 if (bank->ready) 1629 continue; 1630 1631 if (bank->rif_cfg) { 1632 res = apply_rif_config(bank, 1633 bank->rif_cfg->access_mask[0]); 1634 if (res) { 1635 EMSG("Failed to set GPIO bank %c RIF config", 1636 'A' + bank->bank_id); 1637 STAILQ_REMOVE(&bank_list, bank, stm32_gpio_bank, 1638 link); 1639 free(bank); 1640 return res; 1641 } 1642 1643 /* 1644 * Semaphores for pinctrl and GPIO are taken when 1645 * these are used (pinctrl state applied, GPIO 1646 * consumed) or when an explicit firewall configuration 1647 * is requested through the firewall framework. 1648 * Therefore release here the taken semaphores. 1649 */ 1650 for (pin = 0; pin < bank->ngpios; pin++) 1651 release_rif_semaphore_if_acquired(bank, pin); 1652 1653 } else { 1654 stm32_gpio_set_conf_sec(bank); 1655 } 1656 1657 bank->ready = true; 1658 } 1659 1660 return TEE_SUCCESS; 1661 } 1662 1663 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 1664 const void *compat_data) 1665 { 1666 static bool pm_register; 1667 TEE_Result res = TEE_ERROR_GENERIC; 1668 1669 /* Register GPIO banks described in this pin control node */ 1670 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data); 1671 if (res) 1672 return res; 1673 1674 if (STAILQ_EMPTY(&bank_list)) 1675 DMSG("no gpio bank for that driver"); 1676 else if (apply_sec_cfg()) 1677 panic(); 1678 1679 if (!pm_register) { 1680 /* 1681 * Register to PM once for all probed banks to restore 1682 * their secure configuration. 1683 */ 1684 register_pm_driver_cb(stm32_gpio_sec_config_pm, NULL, 1685 "stm32-gpio-secure-config"); 1686 pm_register = true; 1687 } 1688 1689 #ifdef CFG_DRIVERS_PINCTRL 1690 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get, 1691 (void *)compat_data); 1692 if (res) 1693 panic(); 1694 #endif 1695 1696 return TEE_SUCCESS; 1697 } 1698 1699 static const struct dt_device_match stm32_pinctrl_match_table[] = { 1700 { 1701 .compatible = "st,stm32mp135-pinctrl", 1702 .compat_data = &(struct bank_compat){ 1703 .secure_control = true, 1704 .secure_extended = false, 1705 }, 1706 }, 1707 { 1708 .compatible = "st,stm32mp157-pinctrl", 1709 .compat_data = &(struct bank_compat){ 1710 .secure_control = false, 1711 .secure_extended = false, 1712 }, 1713 }, 1714 { 1715 .compatible = "st,stm32mp157-z-pinctrl", 1716 .compat_data = &(struct bank_compat){ 1717 .gpioz = true, 1718 .secure_control = true, 1719 .secure_extended = false, 1720 }, 1721 }, 1722 { 1723 .compatible = "st,stm32mp257-pinctrl", 1724 .compat_data = &(struct bank_compat){ 1725 .secure_control = true, 1726 .secure_extended = true, 1727 }, 1728 }, 1729 { 1730 .compatible = "st,stm32mp257-z-pinctrl", 1731 .compat_data = &(struct bank_compat){ 1732 .gpioz = true, 1733 .secure_control = true, 1734 .secure_extended = true, 1735 }, 1736 }, 1737 { } 1738 }; 1739 1740 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 1741 .name = "stm32_gpio-pinctrl", 1742 .type = DT_DRIVER_PINCTRL, 1743 .match_table = stm32_pinctrl_match_table, 1744 .probe = stm32_pinctrl_probe, 1745 }; 1746