History log of /optee_os/core/ (Results 4201 – 4225 of 6498)
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642a0c6819-Jun-2019 Jens Wiklander <jens.wiklander@linaro.org>

core: remove unused TEE_MATTR_LOCKED

Removes the now unused TEE_MATTR_LOCKED macro.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.

core: remove unused TEE_MATTR_LOCKED

Removes the now unused TEE_MATTR_LOCKED macro.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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570f0d7119-Jun-2019 Jens Wiklander <jens.wiklander@linaro.org>

core: remove obsolete TEE_MMU_UMAP_* defines

Removes the now obsolete TEE_MMU_UMAP_* defines.

Fixes: 211417d3a487 ("core: more flexible ta mapping")
Reviewed-by: Jerome Forissier <jerome.forissier@

core: remove obsolete TEE_MMU_UMAP_* defines

Removes the now obsolete TEE_MMU_UMAP_* defines.

Fixes: 211417d3a487 ("core: more flexible ta mapping")
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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8fee193f19-Jul-2019 Clement Faure <clement.faure@nxp.com>

core: imx: add mx6sxsabresd platform flavor

Add mx6sxsabresd platform flavor to mx6sx.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

c1f744f519-Jul-2019 Clement Faure <clement.faure@nxp.com>

core: imx: add mx6solo platform flavors

Add mx6solosabresd and mx6solosabreauto platform flavors to mx6s.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.co

core: imx: add mx6solo platform flavors

Add mx6solosabresd and mx6solosabreauto platform flavors to mx6s.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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26abeed519-Jul-2019 Clement Faure <clement.faure@nxp.com>

core: imx: add mx6qsabreauto platform flavor

Add mx6qsabreauto platform flavor to mx6q.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

e5ad33ed19-Jul-2019 Clement Faure <clement.faure@nxp.com>

core: imx: add mx6dlsabreauto platform flavor

Add mx6dlsabreauto platform flavor to mx6dl.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

0c2f806619-Jul-2019 Clement Faure <clement.faure@nxp.com>

core: imx: add mx6ul9x9evk platform flavor

Add mx6ul9x9evk platform flavor to mx6ul.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

f9cf3c5619-Jul-2019 Clement Faure <clement.faure@nxp.com>

core: imx: add imx6qp board support

Add imx6qp board support.
Add two imx6qp platform flavors:
* imx6qpsabresd
* imx6qpsabreauto

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by:

core: imx: add imx6qp board support

Add imx6qp board support.
Add two imx6qp platform flavors:
* imx6qpsabresd
* imx6qpsabreauto

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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6230dd0f18-Mar-2019 Silvano di Ninno <silvano.dininno@nxp.com>

core: imx: update PL310 settings

Move PL310 settings for mx6q, 6dl, 6solo to a dedicated file in plat-imx
config folder.
Update PL310 settings.

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.

core: imx: update PL310 settings

Move PL310 settings for mx6q, 6dl, 6solo to a dedicated file in plat-imx
config folder.
Update PL310 settings.

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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2aa5524604-Jul-2019 Silvano di Ninno <silvano.dininno@nxp.com>

core: imx: move plat_cpu_reset_late() function

Remove platform specific imx6 file.
Move plat_cpu_reset_late() function to main file.

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Review

core: imx: move plat_cpu_reset_late() function

Remove platform specific imx6 file.
Move plat_cpu_reset_late() function to main file.

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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fa857e4b14-Nov-2017 Cedric Neveux <cedric.neveux@nxp.com>

core: imx: add SCU module

Move SCU initialization to a separate file. Update it as a driver
module.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

16e7324014-Nov-2017 Cedric Neveux <cedric.neveux@nxp.com>

core: imx: add CSU module

Centralize CSU settings in one file. Update it as a driver module.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

0db0dc0e23-Jul-2019 Clement Faure <clement.faure@nxp.com>

core: imx: disable CAAM for imx6ull

The imx6ull does not feature the CAAM.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

b847af9704-Jul-2019 Silvano di Ninno <silvano.dininno@nxp.com>

core: imx: update CAAM initialization

Change CAAM initialization to a driver model.
Add CAAM base address check.
Move imx_caam.c to drivers folder.

Signed-off-by: Silvano di Ninno <silvano.dininno@

core: imx: update CAAM initialization

Change CAAM initialization to a driver model.
Add CAAM base address check.
Move imx_caam.c to drivers folder.

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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d0d82b5210-Jul-2019 Fangsuo Wu <fangsuowu@asrmicro.com>

core: mmu: Update TCR_EL1 register when new physical address added

Suppose in init stage all physical memory registered is in 0-4G,
the IPS bits (bit34-32) is set 0. Later a physical address 0x10000

core: mmu: Update TCR_EL1 register when new physical address added

Suppose in init stage all physical memory registered is in 0-4G,
the IPS bits (bit34-32) is set 0. Later a physical address 0x100000000
is dynamically mapping with core_mmu_add_mapping, since 0x100000000
is higher than 4G, the IPS bits of TCR_EL1 register should be updated
to 0x1. Otherwise the below panic occurs:

E/TC:00 check_pa_matches_va:1805 va 0x82a00000 maps 0x100000000, expect 0x0

As currently TCR_EL1 register is only set in init stage, this patch
also updates the register in core_mmu_add_mapping.

Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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667b10f624-Jul-2019 Fangsuo Wu <fangsuowu@asrmicro.com>

tee_ree_fs: create dirfile only when it's not found

Currently there's no check of return value of tee_fs_dirfile_open,
it's reasonable to do this when dir file truely doesn't exist.
However, if tee_

tee_ree_fs: create dirfile only when it's not found

Currently there's no check of return value of tee_fs_dirfile_open,
it's reasonable to do this when dir file truely doesn't exist.
However, if tee_fs_dirfile_open fails with other reason, calling
tee_fs_dirfile_open(true..) will overlap the old dir file, thus
file access in the future will fail.

Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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969e405b09-Jul-2019 Jerome Forissier <jerome.forissier@linaro.org>

core: remove useless .section directives

A few assembler files contain ".section .text.<something>" but these
sections do not appear to be used anywhere. In addition, the functions
defined in the fi

core: remove useless .section directives

A few assembler files contain ".section .text.<something>" but these
sections do not appear to be used anywhere. In addition, the functions
defined in the files are always put in their own section anyway,
(.text.<function_name>), because of the -ffunction-sections flag.
Therefore, let's remove the useless directives.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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16e2153c05-Apr-2019 Jerome Forissier <jerome.forissier@linaro.org>

core: arm64: update register accessor macros to support Clang

Clang complains about ASM operand width:

core/arch/arm/include/arm64.h:295:1: warning: value size does not match register size specifi

core: arm64: update register accessor macros to support Clang

Clang complains about ASM operand width:

core/arch/arm/include/arm64.h:295:1: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths]
DEFINE_U32_REG_READWRITE_FUNCS(cpacr_el1)
^
core/arch/arm/include/arm64.h:278:3: note: expanded from macro 'DEFINE_U32_REG_READWRITE_FUNCS'
DEFINE_U32_REG_READ_FUNC(reg) \
^
core/arch/arm/include/arm64.h:272:3: note: expanded from macro 'DEFINE_U32_REG_READ_FUNC'
DEFINE_REG_READ_FUNC_(reg, uint32_t, reg)
^
core/arch/arm/include/arm64.h:261:42: note: expanded from macro 'DEFINE_REG_READ_FUNC_'
asm volatile("mrs %0, " #asmreg : "=r" (val)); \
^
core/arch/arm/include/arm64.h:295:1: note: use constraint modifier "w"
core/arch/arm/include/arm64.h:278:3: note: expanded from macro 'DEFINE_U32_REG_READWRITE_FUNCS'
DEFINE_U32_REG_READ_FUNC(reg) \
^
core/arch/arm/include/arm64.h:272:3: note: expanded from macro 'DEFINE_U32_REG_READ_FUNC'
DEFINE_REG_READ_FUNC_(reg, uint32_t, reg)
^
core/arch/arm/include/arm64.h:261:20: note: expanded from macro 'DEFINE_REG_READ_FUNC_'
asm volatile("mrs %0, " #asmreg : "=r" (val)); \
^

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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46daafa928-Mar-2019 Jerome Forissier <jerome.forissier@linaro.org>

Move .weak directive after the symbol definition

Clang ignores the .weak directive if it appears before the symbol is
defined. Fix the few places where it happens.

Signed-off-by: Jerome Forissier <

Move .weak directive after the symbol definition

Clang ignores the .weak directive if it appears before the symbol is
defined. Fix the few places where it happens.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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9de8272e25-Mar-2019 Jerome Forissier <jerome.forissier@linaro.org>

Remove deprecated ldm/stm instructions

Some uses of SP, PC and LR in the register list of Load/Store Multiple
instructions is forbidden (Thumb) or deprecated (ARM) as per the ARM
ARM DDI 0406 C.d. F

Remove deprecated ldm/stm instructions

Some uses of SP, PC and LR in the register list of Load/Store Multiple
instructions is forbidden (Thumb) or deprecated (ARM) as per the ARM
ARM DDI 0406 C.d. For the LDM instructions, SP should not be in the
list, and the list should not contain both PC and LR. See sections:

[A8.8.58] LDM/LDMIA/LDMFD (Thumb)
[A8.8.59] LDM/LDMIA/LDMFD (ARM)
[A8.8.60] LDMDA/LDMFA
[A8.8.61] LDMDB/LDMEA
[A8.8.62] LDMIB/LDMED

For the STM instructions, neither SP nor PC should be in the list. See
sections:

[A8.8.200] STM (STMIA, STMEA)
[A8.8.201] STMDA (STMED)
[A8.8.202] STMDB (STMFD)
[A8.8.203] STMIB (STMFA)

Clang warns on the deprecated constructs. Use ldr/str instead.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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9b177d3315-Jul-2019 Volodymyr Babchuk <volodymyr_babchuk@epam.com>

core_mmu: fix "outside of array bounds" warning

Newest versions of GCC (v9.1.0 at least) are unhappy about subtraction
from array pointer:

core/arch/arm/mm/core_mmu.c: In function 'core_init_mmu_ma

core_mmu: fix "outside of array bounds" warning

Newest versions of GCC (v9.1.0 at least) are unhappy about subtraction
from array pointer:

core/arch/arm/mm/core_mmu.c: In function 'core_init_mmu_map':
core/arch/arm/mm/core_mmu.c:523:30: warning: array subscript -1 is outside array bounds of 'const struct core_mmu_phys_mem[]' [-Warray-bounds]
523 | for (mem = start; mem < end - 1; mem++) {
| ~~~~^~~
In file included from core/include/initcall.h:9,
from core/arch/arm/include/kernel/generic_boot.h:8,
from core/arch/arm/mm/core_mmu.c:11:
core/include/scattered_array.h:100:29: note: while referencing '__scattered_array_end'
100 | static const element_type __scattered_array_end[0] __unused \
| ^~~~~~~~~~~~~~~~~~~~~

This is valid warning, as such pointer arithmetic produces undefined
behavior according to paragraph 5.6.5.8 of C99 standard. On other hand
the standard allows pointers that point past the last element of
array, so expression "mem + 1" is valid.

Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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62dd517811-Apr-2019 Jerome Forissier <jerome.forissier@linaro.org>

core_self_tests.c: build with -fno-builtin

The memory tests in core_self_tests.c call the malloc()/calloc() API
without doing anything meaningful with the output. It turns out that a
clever compiler

core_self_tests.c: build with -fno-builtin

The memory tests in core_self_tests.c call the malloc()/calloc() API
without doing anything meaningful with the output. It turns out that a
clever compiler (read: Clang) will detect this and aggressively
optimize the code, to the point that a call to calloc() is removed
entirely. Here is a reduced test case for the record:

$ cat test.c
#include <stdlib.h>

int main(int argc, char *argv[])
{
return calloc(1000000, 1) ? 1 : 0;
}
$ clang --target=arm-linux-gnueabihf -Os -c test.c
$ llvm-objdump -d test.o

test.o: file format ELF32-arm-little

Disassembly of section .text:
0000000000000000 main:
0: 01 00 a0 e3 mov r0, #1
4: 1e ff 2f e1 bx lr

No call to calloc() in the generated code! As strange as it may seem,
this is reportedly a valid behavior for the compiler [1].

This optimization is obviously not wanted for the test that tries to
check that allocation of a very large buffer fails in OP-TEE.

This commit adds the -fno-builtins flag to the compiler command for that
particular source file, thus preventing the optimization and making the
test pass.

Link: [1] https://bugs.llvm.org/show_bug.cgi?id=37304
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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e739500903-Apr-2019 Jerome Forissier <jerome.forissier@linaro.org>

core: cast parameter to (void *) when using %p in EMSG()

Fixes the following Clang warning:

core/arch/arm/kernel/generic_boot.c:395:12: warning: format specifies type 'void *' but the argument

core: cast parameter to (void *) when using %p in EMSG()

Fixes the following Clang warning:

core/arch/arm/kernel/generic_boot.c:395:12: warning: format specifies type 'void *' but the argument
has type 'const uint8_t *' (aka 'const unsigned char *') [-Wformat-pedantic]
n, page, res);
^~~~

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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b53bf2aa28-Mar-2019 Jerome Forissier <jerome.forissier@linaro.org>

core: arm: thread.c: increase stack_tmp size from 1.5 to to 2KiB

We get a dead canary error when booting QEMU with OP-TEE compiled with
Clang. Increase stack size a bit to fix the issue.

Signed-off

core: arm: thread.c: increase stack_tmp size from 1.5 to to 2KiB

We get a dead canary error when booting QEMU with OP-TEE compiled with
Clang. Increase stack size a bit to fix the issue.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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078f739e27-Mar-2019 Jerome Forissier <jerome.forissier@linaro.org>

core: link.mk: generate empty tee-pageable.bin when pager is disabled

When CFG_WITH_PAGER != y, there is no need to call $(OBJCOPY) to
generate tee-pageable.bin, since we know it will be empty. Use

core: link.mk: generate empty tee-pageable.bin when pager is disabled

When CFG_WITH_PAGER != y, there is no need to call $(OBJCOPY) to
generate tee-pageable.bin, since we know it will be empty. Use 'touch'
instead.

This fixes an error with Clang, caused by the fact that llvm-objcopy
cannot generate an empty file:

llvm-objcopy: error: failed to open out/arm-plat-vexpress/core/tee-pageable.bin: Invalid argument.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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