1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2019 NXP 5 * 6 * Peng Fan <peng.fan@nxp.com> 7 */ 8 9 #include <console.h> 10 #include <io.h> 11 #include <imx.h> 12 #include <mm/core_mmu.h> 13 #include <mm/core_memprot.h> 14 #include <platform_config.h> 15 16 static uint32_t imx_digproc(void) 17 { 18 static uint32_t reg; 19 vaddr_t anatop_addr; 20 21 if (!reg) { 22 anatop_addr = core_mmu_get_va(ANATOP_BASE, MEM_AREA_IO_SEC); 23 24 /* TODO: Handle SL here */ 25 #ifdef CFG_MX7 26 reg = io_read32(anatop_addr + OFFSET_DIGPROG_IMX7D); 27 #else 28 reg = io_read32(anatop_addr + OFFSET_DIGPROG); 29 #endif 30 } 31 32 return reg; 33 } 34 35 static uint32_t imx_soc_rev_major(void) 36 { 37 return ((imx_digproc() & 0xff00) >> 8) + 1; 38 } 39 40 uint32_t imx_soc_type(void) 41 { 42 return (imx_digproc() >> 16) & 0xff; 43 } 44 45 bool soc_is_imx6sx(void) 46 { 47 return imx_soc_type() == SOC_MX6SX; 48 } 49 50 bool soc_is_imx6ul(void) 51 { 52 return imx_soc_type() == SOC_MX6UL; 53 } 54 55 bool soc_is_imx6ull(void) 56 { 57 return imx_soc_type() == SOC_MX6ULL; 58 } 59 60 bool soc_is_imx6sdl(void) 61 { 62 return imx_soc_type() == SOC_MX6DL; 63 } 64 65 bool soc_is_imx6dq(void) 66 { 67 return (imx_soc_type() == SOC_MX6Q) && (imx_soc_rev_major() == 1); 68 } 69 70 bool soc_is_imx6dqp(void) 71 { 72 return (imx_soc_type() == SOC_MX6Q) && (imx_soc_rev_major() == 2); 73 } 74 75 bool soc_is_imx6(void) 76 { 77 return ((imx_soc_type() == SOC_MX6SX) || 78 (imx_soc_type() == SOC_MX6UL) || 79 (imx_soc_type() == SOC_MX6ULL) || 80 (imx_soc_type() == SOC_MX6DL) || 81 (imx_soc_type() == SOC_MX6Q)); 82 } 83 84 bool soc_is_imx7ds(void) 85 { 86 return imx_soc_type() == SOC_MX7D; 87 } 88 89 uint32_t imx_get_src_gpr(int cpu) 90 { 91 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC); 92 93 if (soc_is_imx7ds()) 94 return io_read32(va + SRC_GPR1_MX7 + cpu * 8 + 4); 95 else 96 return io_read32(va + SRC_GPR1 + cpu * 8 + 4); 97 } 98 99 void imx_set_src_gpr(int cpu, uint32_t val) 100 { 101 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC); 102 103 if (soc_is_imx7ds()) 104 io_write32(va + SRC_GPR1_MX7 + cpu * 8 + 4, val); 105 else 106 io_write32(va + SRC_GPR1 + cpu * 8 + 4, val); 107 } 108