1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * Copyright 2019 NXP 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm.h> 32 #include <console.h> 33 #include <drivers/gic.h> 34 #include <drivers/imx_uart.h> 35 #include <io.h> 36 #include <imx.h> 37 #include <kernel/generic_boot.h> 38 #include <kernel/misc.h> 39 #include <kernel/panic.h> 40 #include <kernel/pm_stubs.h> 41 #include <mm/core_mmu.h> 42 #include <mm/core_memprot.h> 43 #include <platform_config.h> 44 #include <stdint.h> 45 #include <sm/optee_smc.h> 46 #include <tee/entry_fast.h> 47 #include <tee/entry_std.h> 48 49 50 static void main_fiq(void); 51 static struct gic_data gic_data; 52 53 static const struct thread_handlers handlers = { 54 .std_smc = tee_entry_std, 55 .fast_smc = tee_entry_fast, 56 .nintr = main_fiq, 57 #if defined(CFG_WITH_ARM_TRUSTED_FW) 58 .cpu_on = cpu_on_handler, 59 .cpu_off = pm_do_nothing, 60 .cpu_suspend = pm_do_nothing, 61 .cpu_resume = pm_do_nothing, 62 .system_off = pm_do_nothing, 63 .system_reset = pm_do_nothing, 64 #else 65 .cpu_on = pm_panic, 66 .cpu_off = pm_panic, 67 .cpu_suspend = pm_panic, 68 .cpu_resume = pm_panic, 69 .system_off = pm_panic, 70 .system_reset = pm_panic, 71 #endif 72 }; 73 74 static struct imx_uart_data console_data; 75 76 #ifdef CONSOLE_UART_BASE 77 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 78 CORE_MMU_PGDIR_SIZE); 79 #endif 80 #ifdef GIC_BASE 81 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 82 #endif 83 #ifdef ANATOP_BASE 84 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_PGDIR_SIZE); 85 #endif 86 #ifdef GICD_BASE 87 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, 0x10000); 88 #endif 89 #ifdef AIPS1_BASE 90 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS1_BASE, 91 ROUNDUP(AIPS1_SIZE, CORE_MMU_PGDIR_SIZE)); 92 #endif 93 #ifdef AIPS2_BASE 94 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS2_BASE, 95 ROUNDUP(AIPS2_SIZE, CORE_MMU_PGDIR_SIZE)); 96 #endif 97 #ifdef AIPS3_BASE 98 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS3_BASE, 99 ROUNDUP(AIPS3_SIZE, CORE_MMU_PGDIR_SIZE)); 100 #endif 101 #ifdef IRAM_BASE 102 register_phys_mem(MEM_AREA_TEE_COHERENT, 103 ROUNDDOWN(IRAM_BASE, CORE_MMU_PGDIR_SIZE), 104 CORE_MMU_PGDIR_SIZE); 105 #endif 106 #ifdef IRAM_S_BASE 107 register_phys_mem(MEM_AREA_TEE_COHERENT, 108 ROUNDDOWN(IRAM_S_BASE, CORE_MMU_PGDIR_SIZE), 109 CORE_MMU_PGDIR_SIZE); 110 #endif 111 112 #if defined(CFG_PL310) 113 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 114 ROUNDDOWN(PL310_BASE, CORE_MMU_PGDIR_SIZE), 115 CORE_MMU_PGDIR_SIZE); 116 #endif 117 118 const struct thread_handlers *generic_boot_get_handlers(void) 119 { 120 return &handlers; 121 } 122 123 static void main_fiq(void) 124 { 125 gic_it_handle(&gic_data); 126 } 127 128 void console_init(void) 129 { 130 imx_uart_init(&console_data, CONSOLE_UART_BASE); 131 register_serial_console(&console_data.chip); 132 } 133 134 void main_init_gic(void) 135 { 136 #ifdef CFG_ARM_GICV3 137 vaddr_t gicd_base; 138 139 gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC); 140 141 if (!gicd_base) 142 panic(); 143 144 /* Initialize GIC */ 145 gic_init(&gic_data, 0, gicd_base); 146 itr_init(&gic_data.chip); 147 #else 148 vaddr_t gicc_base; 149 vaddr_t gicd_base; 150 151 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC); 152 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC); 153 154 if (!gicc_base || !gicd_base) 155 panic(); 156 157 /* Initialize GIC */ 158 gic_init(&gic_data, gicc_base, gicd_base); 159 itr_init(&gic_data.chip); 160 #endif 161 } 162 163 #if CFG_TEE_CORE_NB_CORE > 1 164 void main_secondary_init_gic(void) 165 { 166 gic_cpu_init(&gic_data); 167 } 168 #endif 169 170 #if defined(CFG_BOOT_SYNC_CPU) 171 static void psci_boot_allcpus(void) 172 { 173 vaddr_t src_base = core_mmu_get_va(SRC_BASE, MEM_AREA_TEE_COHERENT); 174 uint32_t pa = virt_to_phys((void *)TEE_TEXT_VA_START); 175 176 /* set secondary entry address and release core */ 177 io_write32(src_base + SRC_GPR1 + 8, pa); 178 io_write32(src_base + SRC_GPR1 + 16, pa); 179 io_write32(src_base + SRC_GPR1 + 24, pa); 180 181 io_write32(src_base + SRC_SCR, BM_SRC_SCR_CPU_ENABLE_ALL); 182 } 183 #endif 184 185 void plat_cpu_reset_late(void) 186 { 187 if (!get_core_pos()) { 188 /* primary core */ 189 #if defined(CFG_BOOT_SYNC_CPU) 190 psci_boot_allcpus() 191 #endif 192 imx_configure_tzasc(); 193 } 194 } 195