| c11218eb | 28-Apr-2023 |
Clement Faure <clement.faure@nxp.com> |
pta: stats: fix compilation incompatible pointer warning
To reproduce the issue: $ make PLATFORM=imx-mx8mmevk CFG_WITH_STATS=y CFG_TA_STATS=y
core/pta/stats.c: In function ‘get_user_ta_stats’: core
pta: stats: fix compilation incompatible pointer warning
To reproduce the issue: $ make PLATFORM=imx-mx8mmevk CFG_WITH_STATS=y CFG_TA_STATS=y
core/pta/stats.c: In function ‘get_user_ta_stats’: core/pta/stats.c:169:37: warning: passing argument 2 of ‘tee_ta_instance_stats’ from incompatible pointer type [-Wincompatible-pointer-types] 169 | &p[0].memref.size); | ^~~~~~~~~~~~~~~~~ | | | size_t * {aka long unsigned int *} In file included from core/include/kernel/pseudo_ta.h:10, from core/pta/stats.c:8: core/include/kernel/tee_ta_manager.h:171:56: note: expected ‘uint32_t *’ {aka ‘unsigned int *’} but argument is of type ‘size_t *’ {aka ‘long unsigned int *’} 171 | TEE_Result tee_ta_instance_stats(void *buff, uint32_t *buff_size); | ~~~~~~~~~~^~~~~~~~~ core/pta/stats.c: At top level: cc1: note: unrecognized command-line option ‘-Wno-c2x-extensions’ may have been intended to silence earlier diagnostics
Fixes: 7509620b8b95 ("GP131: Update TEE_Param") Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 426790bd | 13-Feb-2023 |
Jeffrey Kardatzke <jkardatzke@google.com> |
drivers: add cbmem console driver
This adds a CBMEM console driver which gets the cbmem address from a device tree with the coreboot table information.
Signed-off-by: Jeffrey Kardatzke <jkardatzke@
drivers: add cbmem console driver
This adds a CBMEM console driver which gets the cbmem address from a device tree with the coreboot table information.
Signed-off-by: Jeffrey Kardatzke <jkardatzke@google.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 9e3c57c8 | 28-Feb-2023 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: dt_driver: move related content from dt.h to dt_driver.h
Moves so-called dt_driver related declarations and definitions from dt.h to dt_drivers.h. Incidentally adds an inline description to en
core: dt_driver: move related content from dt.h to dt_driver.h
Moves so-called dt_driver related declarations and definitions from dt.h to dt_drivers.h. Incidentally adds an inline description to enum dt_driver_type. This change clarifies when a source file shall include dt.h and/or dt_driver.h.
This change updates driver source files to include none, one or both of these header files where applicable.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 86ce921f | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add core_mmu_get_secure_memory()
Adds core_mmu_get_secure_memory() with the primary purpose of being used to find out the memory range to pass to memtag_set_tags().
Signed-off-by: Jens Wiklan
core: add core_mmu_get_secure_memory()
Adds core_mmu_get_secure_memory() with the primary purpose of being used to find out the memory range to pass to memtag_set_tags().
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 439d2a89 | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: pass secure memory parameter to virt_init_memory()
Pass the physical secure memory range as a parameter from secure_only[]. This avoids using hard coded defines in virt_init_memory().
CFG_NS_
core: pass secure memory parameter to virt_init_memory()
Pass the physical secure memory range as a parameter from secure_only[]. This avoids using hard coded defines in virt_init_memory().
CFG_NS_VIRTUALIZATION=y depends on secure_only[] to have all memory as consecutive memory ranges, but that's unchanged behaviour from before since it was expected that the entire range from TEE_RAM_START to TA_RAM_START + TA_RAM_SIZE is usable memory.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| ee34e7ea | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: remove TEE_RAM_VA_START and TEE_TEXT_VA_START
TEE_RAM_VA_START and TEE_TEXT_VA_START are defined to exactly the same thing as TEE_RAM_START and TEE_LOAD_ADDR respectively. They don't deal with
core: remove TEE_RAM_VA_START and TEE_TEXT_VA_START
TEE_RAM_VA_START and TEE_TEXT_VA_START are defined to exactly the same thing as TEE_RAM_START and TEE_LOAD_ADDR respectively. They don't deal with virtual addresses as the names suggests, they too represent physical addresses. So remove TEE_RAM_VA_START and TEE_TEXT_VA_START to get rid of some redundancy.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| c24c1950 | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: linker.h: remove *_SZ_UNSAFE defines
Removes the now unused *_SZ_UNSAFE defines.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.
core: linker.h: remove *_SZ_UNSAFE defines
Removes the now unused *_SZ_UNSAFE defines.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| a45f7eea | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: improve register_phys_mem_pgdir() debug print
Improves the debug prints emitted by register_phys_mem_pgdir() to use the define of the base address instead. For example: ROUNDDOWN(0x09040000, C
core: improve register_phys_mem_pgdir() debug print
Improves the debug prints emitted by register_phys_mem_pgdir() to use the define of the base address instead. For example: ROUNDDOWN(0x09040000, CORE_MMU_PGDIR_SIZE) type IO_SEC 0x09000000 size 0x00200000 becomes: CONSOLE_UART_BASE type IO_SEC 0x09000000 size 0x00200000
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| ff843c89 | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: linker.h: fix ASAN_MAP_PA and ASAN_SHADOW_PA
Fixes ASAN_MAP_PA and ASAN_SHADOW_PA to cast via vaddr_t to paddr_t to avoid compile errors when paddr_t is larger than a pointer, that is, with CF
core: linker.h: fix ASAN_MAP_PA and ASAN_SHADOW_PA
Fixes ASAN_MAP_PA and ASAN_SHADOW_PA to cast via vaddr_t to paddr_t to avoid compile errors when paddr_t is larger than a pointer, that is, with CFG_CORE_LARGE_PHYS_ADDR on 32-bit platforms.
core/include/kernel/linker.h:113:26: error: cast from pointer to integer of diff erent size [-Werror=pointer-to-int-cast] 113 | #define ASAN_MAP_PA ((paddr_t)__asan_map_start) | ^
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 0f2735cd | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: linker.h: fix VCORE_NEX_RW_SZ
Fixes the VCORE_NEX_RW_SZ define by adding a missing pair of ( ).
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.c
core: linker.h: fix VCORE_NEX_RW_SZ
Fixes the VCORE_NEX_RW_SZ define by adding a missing pair of ( ).
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 3734abd2 | 22-Mar-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
core: dt: remove fdt_check_node()
The function is never implemented, remove the ghost prototype.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etie
core: dt: remove fdt_check_node()
The function is never implemented, remove the ghost prototype.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 07ced948 | 22-Mar-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
core: dt: add kernel DT API to retrieve regs by name
This patch adds _fdt_get_reg_props_by_index() and _fdt_get_reg_props_by_name() APIs.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.
core: dt: add kernel DT API to retrieve regs by name
This patch adds _fdt_get_reg_props_by_index() and _fdt_get_reg_props_by_name() APIs.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 7c3a6b7b | 22-Mar-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
core: dt: add kernel DT API fdt_read_uint32_index()
This patch adds fdt_read_uint32_index() API. This API reads one cell from a given multi-value property.
This patch updates fdt_read_uint32() and
core: dt: add kernel DT API fdt_read_uint32_index()
This patch adds fdt_read_uint32_index() API. This API reads one cell from a given multi-value property.
This patch updates fdt_read_uint32() and fdt_read_uint32_default() to use fdt_read_uint32_index() API
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| f354a5d8 | 05-Apr-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
core: replace _fdt_ prefix with fdt_ for device tree API
As per upstream discussion, there is no reason to keep _fdt_ prefix. Replaces it with fdt_ for all occurrences.
Signed-off-by: Gatien Cheval
core: replace _fdt_ prefix with fdt_ for device tree API
As per upstream discussion, there is no reason to keep _fdt_ prefix. Replaces it with fdt_ for all occurrences.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 8bc9c9e2 | 16-Dec-2022 |
Clément Léger <clement.leger@bootlin.com> |
drivers: i2c: add a simple framework to handle i2c devices
Add simple i2c support which provides support for I2C controllers and devices using the generic DT mechanisms that already exists. I2C cont
drivers: i2c: add a simple framework to handle i2c devices
Add simple i2c support which provides support for I2C controllers and devices using the generic DT mechanisms that already exists. I2C controllers needs to implement i2c_ctrl_ops to provide i2c operations such as read, write and smbus commands depending on their capabilities. I2C devices driver can then be defined using DEFINE_I2C_DEV_DRIVER(). This macros will use a default i2c probe function (__i2c_probe()) which will then call the I2C device probe function by passing a i2c_dev struct that can be used to communicate with the I2C device defined in the device-tree.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| e7a2db34 | 14-Mar-2023 |
Clément Léger <clement.leger@bootlin.com> |
core: dt_driver: add support for DT_DRIVER_I2C
Integrating I2C support within the dt_driver mechanism require to change the way controller are retrieved. Indeed, when using i2c, the children are loc
core: dt_driver: add support for DT_DRIVER_I2C
Integrating I2C support within the dt_driver mechanism require to change the way controller are retrieved. Indeed, when using i2c, the children are located under a parent I2C controller node. This implies to use another method to parse node heriarchy and ignore the case when the provider has no phandle.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 33cc94df | 13-Mar-2023 |
Clément Léger <clement.leger@bootlin.com> |
core: dt_driver: add phandle node and fdt to dt_driver_phandle_args
With pinctrl, it is necessary for the provider to access the node which will need to be apply since it contains custom controller
core: dt_driver: add phandle node and fdt to dt_driver_phandle_args
With pinctrl, it is necessary for the provider to access the node which will need to be apply since it contains custom controller properties that need to be parsed. In order to integrate pinctrl with the existing dt_driver generic support, add these members and fill them when invoking the get_of_device() callback.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 753e6fe4 | 24-Feb-2023 |
Clement Faure <clement.faure@nxp.com> |
drivers: imx_mu: increase maximum MU message size
Increase MU message maximum size to 17 words. It corresponds to the biggest message of the ELE API.
Signed-off-by: Clement Faure <clement.faure@nxp
drivers: imx_mu: increase maximum MU message size
Increase MU message maximum size to 17 words. It corresponds to the biggest message of the ELE API.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 088116c9 | 24-Feb-2023 |
Clement Faure <clement.faure@nxp.com> |
drivers: imx_mu: add support for imx93
Add MU support for imx93.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carr
drivers: imx_mu: add support for imx93
Add MU support for imx93.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| bfedef0c | 10-Mar-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm64: SHA-3 using ARMv8.2-A cryptographic extensions
Import SHA-3 assembly code from the Linux kernel (Linaro contribution). Enabled with CFG_CRYPTO_SHA3_ARM_CE=y, set by default if CFG_CRYPT
core: arm64: SHA-3 using ARMv8.2-A cryptographic extensions
Import SHA-3 assembly code from the Linux kernel (Linaro contribution). Enabled with CFG_CRYPTO_SHA3_ARM_CE=y, set by default if CFG_CRYPTO_WITH_CE82=y.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 8b5fb12e | 07-Mar-2023 |
Xu Yizhou <xuyizhou1@huawei.com> |
core: arm64: SM4-AESE optimization for ARMv8
Enabled with CFG_CRYPTO_SM4_ARM_AESE=y, set by default if CFG_CRYPTO_WITH_CE=y.
Signed-off-by: Xu Yizhou <xuyizhou1@huawei.com> Acked-by: Tianjia Zhang
core: arm64: SM4-AESE optimization for ARMv8
Enabled with CFG_CRYPTO_SM4_ARM_AESE=y, set by default if CFG_CRYPTO_WITH_CE=y.
Signed-off-by: Xu Yizhou <xuyizhou1@huawei.com> Acked-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| d538d293 | 23-Jan-2023 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: add manufacturing protection feature
The CAAM features a "manufacturing protection" functionality. It is a authentication process used to authenticate the chip to the OEM's server. Th
drivers: caam: add manufacturing protection feature
The CAAM features a "manufacturing protection" functionality. It is a authentication process used to authenticate the chip to the OEM's server. The authentication process can ensure the chip: * is a genuine NXP part * is a correct part type * has been properly fused * is running a authenticated software * runs in secure/trusted mode.
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 90dee57a | 04-Apr-2022 |
Clément Léger <clement.leger@bootlin.com> |
drivers: clk: sam: export audiopll_fracck and usbck
This allows to modify the clocks rate and parents from the device-tree using assigned-clock-parents/rate properties rather than hardcoding the clo
drivers: clk: sam: export audiopll_fracck and usbck
This allows to modify the clocks rate and parents from the device-tree using assigned-clock-parents/rate properties rather than hardcoding the clocks rate.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| c0e9e857 | 04-Apr-2022 |
Clément Léger <clement.leger@bootlin.com> |
drivers: clk: sam: add a macro for count of main clocks
Add a macro instead of using clock index name to define the count of main clocks. This will ease the changes when exposing new clocks.
Signed
drivers: clk: sam: add a macro for count of main clocks
Add a macro instead of using clock index name to define the count of main clocks. This will ease the changes when exposing new clocks.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 809fa817 | 10-Feb-2023 |
Balint Dobszay <balint.dobszay@arm.com> |
core: ffa: add TOS_FW_CONFIG handling
At boot TF-A passes two DT addresses (HW_CONFIG and TOS_FW_CONFIG), but currently only the HW_CONFIG address is saved, the other one is dropped. This commit add
core: ffa: add TOS_FW_CONFIG handling
At boot TF-A passes two DT addresses (HW_CONFIG and TOS_FW_CONFIG), but currently only the HW_CONFIG address is saved, the other one is dropped. This commit adds functionality to save the TOS_FW_CONFIG too, so we can retrieve it later. This is necessary for the CFG_CORE_SEL1_SPMC use case, because the SPMC manifest is passed in this DT.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
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