1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2021-2022, STMicroelectronics 4 */ 5 6 #include <drivers/clk.h> 7 #include <drivers/clk_dt.h> 8 #include <drivers/stm32_tamp.h> 9 #include <io.h> 10 #include <kernel/dt.h> 11 #include <kernel/dt_driver.h> 12 #include <kernel/interrupt.h> 13 #include <libfdt.h> 14 #include <mm/core_memprot.h> 15 #include <stdbool.h> 16 17 /* STM32 Registers */ 18 #define _TAMP_CR1 0x00U 19 #define _TAMP_CR2 0x04U 20 #define _TAMP_CR3 0x08U 21 #define _TAMP_FLTCR 0x0CU 22 #define _TAMP_ATCR1 0x10U 23 #define _TAMP_ATSEEDR 0x14U 24 #define _TAMP_ATOR 0x18U 25 #define _TAMP_ATCR2 0x1CU 26 #define _TAMP_SECCFGR 0x20U 27 #define _TAMP_SMCR 0x20U 28 #define _TAMP_PRIVCFGR 0x24U 29 #define _TAMP_IER 0x2CU 30 #define _TAMP_SR 0x30U 31 #define _TAMP_MISR 0x34U 32 #define _TAMP_SMISR 0x38U 33 #define _TAMP_SCR 0x3CU 34 #define _TAMP_COUNTR 0x40U 35 #define _TAMP_COUNT2R 0x44U 36 #define _TAMP_OR 0x50U 37 #define _TAMP_ERCFGR 0X54U 38 #define _TAMP_HWCFGR2 0x3ECU 39 #define _TAMP_HWCFGR1 0x3F0U 40 #define _TAMP_VERR 0x3F4U 41 #define _TAMP_IPIDR 0x3F8U 42 #define _TAMP_SIDR 0x3FCU 43 44 /* _TAMP_SECCFGR bit fields */ 45 #define _TAMP_SECCFGR_BKPRWSEC_MASK GENMASK_32(7, 0) 46 #define _TAMP_SECCFGR_BKPRWSEC_SHIFT 0U 47 #define _TAMP_SECCFGR_CNT2SEC BIT(14) 48 #define _TAMP_SECCFGR_CNT1SEC BIT(15) 49 #define _TAMP_SECCFGR_BKPWSEC_MASK GENMASK_32(23, 16) 50 #define _TAMP_SECCFGR_BKPWSEC_SHIFT 16U 51 #define _TAMP_SECCFGR_BHKLOCK BIT(30) 52 #define _TAMP_SECCFGR_TAMPSEC BIT(31) 53 #define _TAMP_SECCFGR_BUT_BKP_MASK (GENMASK_32(31, 30) | \ 54 GENMASK_32(15, 14)) 55 56 /* _TAMP_SMCR bit fields */ 57 #define _TAMP_SMCR_BKPRWDPROT_MASK GENMASK_32(7, 0) 58 #define _TAMP_SMCR_BKPRWDPROT_SHIFT 0U 59 #define _TAMP_SMCR_BKPWDPROT_MASK GENMASK_32(23, 16) 60 #define _TAMP_SMCR_BKPWDPROT_SHIFT 16U 61 #define _TAMP_SMCR_DPROT BIT(31) 62 /* 63 * _TAMP_PRIVCFGR bit fields 64 */ 65 #define _TAMP_PRIVCFG_CNT2PRIV BIT(14) 66 #define _TAMP_PRIVCFG_CNT1PRIV BIT(15) 67 #define _TAMP_PRIVCFG_BKPRWPRIV BIT(29) 68 #define _TAMP_PRIVCFG_BKPWPRIV BIT(30) 69 #define _TAMP_PRIVCFG_TAMPPRIV BIT(31) 70 #define _TAMP_PRIVCFGR_MASK (GENMASK_32(31, 29) | \ 71 GENMASK_32(15, 14)) 72 73 /* 74 * _TAMP_PRIVCFGR bit fields 75 */ 76 #define _TAMP_PRIVCFG_CNT2PRIV BIT(14) 77 #define _TAMP_PRIVCFG_CNT1PRIV BIT(15) 78 #define _TAMP_PRIVCFG_BKPRWPRIV BIT(29) 79 #define _TAMP_PRIVCFG_BKPWPRIV BIT(30) 80 #define _TAMP_PRIVCFG_TAMPPRIV BIT(31) 81 #define _TAMP_PRIVCFGR_MASK (GENMASK_32(31, 29) | \ 82 GENMASK_32(15, 14)) 83 84 /* _TAMP_HWCFGR2 bit fields */ 85 #define _TAMP_HWCFGR2_TZ GENMASK_32(11, 8) 86 #define _TAMP_HWCFGR2_OR GENMASK_32(7, 0) 87 88 /* _TAMP_HWCFGR1 bit fields */ 89 #define _TAMP_HWCFGR1_BKPREG GENMASK_32(7, 0) 90 #define _TAMP_HWCFGR1_TAMPER GENMASK_32(11, 8) 91 #define _TAMP_HWCFGR1_ACTIVE GENMASK_32(15, 12) 92 #define _TAMP_HWCFGR1_INTERN GENMASK_32(31, 16) 93 #define _TAMP_HWCFGR1_ITAMP_MAX_ID 16U 94 #define _TAMP_HWCFGR1_ITAMP(id) BIT((id) - INT_TAMP1 + 16U) 95 96 /* _TAMP_VERR bit fields */ 97 #define _TAMP_VERR_MINREV GENMASK_32(3, 0) 98 #define _TAMP_VERR_MAJREV GENMASK_32(7, 4) 99 100 /* 101 * TAMP instance data 102 * @base - IOMEM base address 103 * @clock - TAMP clock 104 * @it - TAMP interrupt number 105 * @hwconf1 - Copy of TAMP HWCONF1 register content 106 * @hwconf2 - Copy of TAMP HWCONF2 register content 107 * @compat - Reference to compat data passed at driver initialization 108 */ 109 struct stm32_tamp_instance { 110 struct io_pa_va base; 111 struct clk *clock; 112 int it; 113 uint32_t hwconf1; 114 uint32_t hwconf2; 115 struct stm32_tamp_compat *compat; 116 }; 117 118 /* 119 * Compatibility capabilities 120 * TAMP_HAS_REGISTER_SECCFG - Supports SECCFGR, otherwise supports SMCR register 121 * TAMP_HAS_REGISTER_PRIVCFG - Supports PRIVCFGR configuration register 122 */ 123 #define TAMP_HAS_REGISTER_SECCFG BIT(0) 124 #define TAMP_HAS_REGISTER_PRIVCFGR BIT(1) 125 126 /* 127 * @nb_monotonic_counter - Number of monotic counter supported 128 * @tags - Bit flags TAMP_HAS_* for compatibily management 129 */ 130 struct stm32_tamp_compat { 131 int nb_monotonic_counter; 132 uint32_t tags; 133 }; 134 135 /* Expects at most a single instance */ 136 static struct stm32_tamp_instance *stm32_tamp_device; 137 138 TEE_Result stm32_tamp_set_secure_bkpregs(struct stm32_bkpregs_conf *bkr_conf) 139 { 140 struct stm32_tamp_instance *tamp = stm32_tamp_device; 141 vaddr_t base = 0; 142 uint32_t first_z2 = 0; 143 uint32_t first_z3 = 0; 144 145 if (!tamp) 146 return TEE_ERROR_DEFER_DRIVER_INIT; 147 148 if (!bkr_conf) 149 return TEE_ERROR_BAD_PARAMETERS; 150 151 base = io_pa_or_va(&tamp->base, 1); 152 153 first_z2 = bkr_conf->nb_zone1_regs; 154 first_z3 = bkr_conf->nb_zone1_regs + bkr_conf->nb_zone2_regs; 155 156 if ((first_z2 > (tamp->hwconf1 & _TAMP_HWCFGR1_BKPREG)) || 157 (first_z3 > (tamp->hwconf1 & _TAMP_HWCFGR1_BKPREG))) 158 return TEE_ERROR_BAD_PARAMETERS; 159 160 if (tamp->compat && (tamp->compat->tags & TAMP_HAS_REGISTER_SECCFG)) { 161 io_clrsetbits32(base + _TAMP_SECCFGR, 162 _TAMP_SECCFGR_BKPRWSEC_MASK, 163 (first_z2 << _TAMP_SECCFGR_BKPRWSEC_SHIFT) & 164 _TAMP_SECCFGR_BKPRWSEC_MASK); 165 166 io_clrsetbits32(base + _TAMP_SECCFGR, 167 _TAMP_SECCFGR_BKPWSEC_MASK, 168 (first_z3 << _TAMP_SECCFGR_BKPWSEC_SHIFT) & 169 _TAMP_SECCFGR_BKPWSEC_MASK); 170 } else { 171 io_clrsetbits32(base + _TAMP_SMCR, 172 _TAMP_SMCR_BKPRWDPROT_MASK, 173 (first_z2 << _TAMP_SMCR_BKPRWDPROT_SHIFT) & 174 _TAMP_SMCR_BKPRWDPROT_MASK); 175 176 io_clrsetbits32(base + _TAMP_SMCR, 177 _TAMP_SMCR_BKPWDPROT_MASK, 178 (first_z3 << _TAMP_SMCR_BKPWDPROT_SHIFT) & 179 _TAMP_SMCR_BKPWDPROT_MASK); 180 } 181 182 return TEE_SUCCESS; 183 } 184 185 static void stm32_tamp_set_secure(struct stm32_tamp_instance *tamp, 186 uint32_t mode) 187 { 188 vaddr_t base = io_pa_or_va(&tamp->base, 1); 189 190 if (tamp->compat && (tamp->compat->tags & TAMP_HAS_REGISTER_SECCFG)) { 191 io_clrsetbits32(base + _TAMP_SECCFGR, 192 _TAMP_SECCFGR_BUT_BKP_MASK, 193 mode & _TAMP_SECCFGR_BUT_BKP_MASK); 194 } else { 195 /* 196 * Note: MP15 doesn't use SECCFG register and 197 * inverts the secure bit. 198 */ 199 if (mode & _TAMP_SECCFGR_TAMPSEC) 200 io_clrbits32(base + _TAMP_SMCR, _TAMP_SMCR_DPROT); 201 else 202 io_setbits32(base + _TAMP_SMCR, _TAMP_SMCR_DPROT); 203 } 204 } 205 206 static void stm32_tamp_set_privilege(struct stm32_tamp_instance *tamp, 207 uint32_t mode) 208 { 209 vaddr_t base = io_pa_or_va(&tamp->base, 1); 210 211 if (tamp->compat && (tamp->compat->tags & TAMP_HAS_REGISTER_PRIVCFGR)) 212 io_clrsetbits32(base + _TAMP_PRIVCFGR, _TAMP_PRIVCFGR_MASK, 213 mode & _TAMP_PRIVCFGR_MASK); 214 } 215 216 static TEE_Result stm32_tamp_parse_fdt(struct stm32_tamp_instance *tamp, 217 const void *fdt, int node, 218 const void *compat) 219 { 220 struct dt_node_info dt_tamp = { }; 221 222 fdt_fill_device_info(fdt, &dt_tamp, node); 223 224 if (dt_tamp.reg == DT_INFO_INVALID_REG || 225 dt_tamp.reg_size == DT_INFO_INVALID_REG_SIZE) 226 return TEE_ERROR_BAD_PARAMETERS; 227 228 tamp->compat = (struct stm32_tamp_compat *)compat; 229 tamp->it = dt_tamp.interrupt; 230 tamp->base.pa = dt_tamp.reg; 231 io_pa_or_va_secure(&tamp->base, dt_tamp.reg_size); 232 233 return clk_dt_get_by_index(fdt, node, 0, &tamp->clock); 234 } 235 236 static TEE_Result stm32_tamp_probe(const void *fdt, int node, 237 const void *compat_data) 238 { 239 struct stm32_tamp_instance *tamp = NULL; 240 uint32_t __maybe_unused revision = 0; 241 TEE_Result res = TEE_SUCCESS; 242 vaddr_t base = 0; 243 244 tamp = calloc(1, sizeof(*tamp)); 245 if (!tamp) 246 return TEE_ERROR_OUT_OF_MEMORY; 247 248 res = stm32_tamp_parse_fdt(tamp, fdt, node, compat_data); 249 if (res) 250 goto err; 251 252 clk_enable(tamp->clock); 253 254 base = io_pa_or_va(&tamp->base, 1); 255 256 tamp->hwconf1 = io_read32(base + _TAMP_HWCFGR1); 257 tamp->hwconf2 = io_read32(base + _TAMP_HWCFGR2); 258 259 revision = io_read32(base + _TAMP_VERR); 260 FMSG("STM32 TAMPER V%"PRIx32".%"PRIu32, 261 (revision & _TAMP_VERR_MAJREV) >> 4, revision & _TAMP_VERR_MINREV); 262 263 if (!(tamp->hwconf2 & _TAMP_HWCFGR2_TZ)) { 264 EMSG("TAMP doesn't support TrustZone"); 265 res = TEE_ERROR_NOT_SUPPORTED; 266 goto err_clk; 267 } 268 269 /* 270 * Enforce secure only access to protected TAMP registers. 271 * Allow non-secure access to monotonic counter. 272 */ 273 stm32_tamp_set_secure(tamp, _TAMP_SECCFGR_TAMPSEC); 274 275 /* 276 * Enforce privilege only access to TAMP registers, backup 277 * registers and monotonic counter. 278 */ 279 stm32_tamp_set_privilege(tamp, _TAMP_PRIVCFG_TAMPPRIV | 280 _TAMP_PRIVCFG_BKPRWPRIV | 281 _TAMP_PRIVCFG_BKPWPRIV); 282 283 stm32_tamp_device = tamp; 284 285 return TEE_SUCCESS; 286 287 err_clk: 288 clk_disable(tamp->clock); 289 err: 290 free(tamp); 291 return res; 292 } 293 294 static const struct stm32_tamp_compat mp13_compat = { 295 .nb_monotonic_counter = 2, 296 .tags = TAMP_HAS_REGISTER_SECCFG | TAMP_HAS_REGISTER_PRIVCFGR, 297 }; 298 299 static const struct stm32_tamp_compat mp15_compat = { 300 .nb_monotonic_counter = 1, 301 .tags = 0, 302 }; 303 304 static const struct dt_device_match stm32_tamp_match_table[] = { 305 { .compatible = "st,stm32mp13-tamp", .compat_data = &mp13_compat }, 306 { .compatible = "st,stm32-tamp", .compat_data = &mp15_compat }, 307 { } 308 }; 309 310 DEFINE_DT_DRIVER(stm32_tamp_dt_driver) = { 311 .name = "stm32-tamp", 312 .match_table = stm32_tamp_match_table, 313 .probe = stm32_tamp_probe, 314 }; 315