1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2022 Microchip 4 * 5 * Driver for AT91 PIOBU 6 */ 7 8 #include <assert.h> 9 #include <drivers/atmel_rtc.h> 10 #include <dt-bindings/gpio/atmel,piobu.h> 11 #include <gpio.h> 12 #include <io.h> 13 #include <kernel/boot.h> 14 #include <kernel/dt.h> 15 #include <kernel/dt_driver.h> 16 #include <kernel/pm.h> 17 #include <libfdt.h> 18 #include <mm/core_memprot.h> 19 20 #define SECUMOD_MAX_PINS 8 21 #define SECUMOD_PIN_MASK (BIT(SECUMOD_MAX_PINS) - 1) 22 #define SECUMOD_PIN_SHIFT 16 23 #define SECUMOD_PIN_VAL(pin) BIT(SECUMOD_PIN_SHIFT + (pin)) 24 25 #define DT_GPIO_CELLS 2 26 27 #define SECUMOD_CR 0x0 28 #define SECUMOD_CR_KEY_SHIFT 16 29 #define SECUMOD_CR_KEY SHIFT_U32(0x89CA, SECUMOD_CR_KEY_SHIFT) 30 #define SECUMOD_CR_BACKUP BIT(0) 31 #define SECUMOD_CR_NORMAL BIT(1) 32 33 #define SECUMOD_SR 0x8 34 #define SECUMOD_SR_JTAG BIT(3) 35 #define SECUMOD_SR_TST_PIN BIT(2) 36 37 #define SECUMOD_SCR 0x10 38 39 #define SECUMOD_PIOBU(x) (0x18 + (x) * 0x4) 40 #define SECUMOD_PIOBU_AFV_MASK GENMASK_32(3, 0) 41 #define SECUMOD_PIOBU_RFV_SHIFT 4 42 #define SECUMOD_PIOBU_OUTPUT BIT(8) 43 #define SECUMOD_PIOBU_SOD BIT(9) 44 #define SECUMOD_PIOBU_PDS BIT(10) 45 #define SECUMOD_PIOBU_PULLUP_SHIFT 12 46 #define SECUMOD_PIOBU_SWITCH_SHIFT 15 47 48 #define SECUMOD_JTAGCR 0x68 49 #define SECUMOD_JTAGCR_FNTRST 0x1 50 51 #define SECUMOD_BMPR 0x7C 52 #define SECUMOD_NMPR 0x80 53 #define SECUMOD_NIEPR 0x84 54 #define SECUMOD_NIDPR 0x88 55 #define SECUMOD_NIMPR 0x8C 56 #define SECUMOD_WKPR 0x90 57 58 static vaddr_t secumod_base; 59 static uint32_t gpio_protected; 60 static struct gpio_chip secumod_chip; 61 62 /* 63 * Get value from GPIO controller 64 * chip: pointer to GPIO controller chip instance 65 * gpio_pin: pin from which value needs to be read 66 * Return target GPIO pin level. 67 */ 68 static enum gpio_level gpio_get_value(struct gpio_chip *chip __unused, 69 unsigned int gpio_pin) 70 { 71 vaddr_t piobu_addr = 0; 72 uint32_t piobu = 0; 73 74 assert(gpio_pin < SECUMOD_MAX_PINS && 75 !(gpio_protected & BIT32(gpio_pin))); 76 77 piobu_addr = secumod_base + SECUMOD_PIOBU(gpio_pin); 78 piobu = io_read32(piobu_addr); 79 80 if (piobu & SECUMOD_PIOBU_PDS) 81 return GPIO_LEVEL_HIGH; 82 else 83 return GPIO_LEVEL_LOW; 84 } 85 86 /* 87 * Set value for GPIO controller 88 * chip: pointer to GPIO controller chip instance 89 * gpio_pin: pin to which value needs to be written 90 * value: Level state for the target pin 91 */ 92 static void gpio_set_value(struct gpio_chip *chip __unused, 93 unsigned int gpio_pin, enum gpio_level value) 94 { 95 vaddr_t piobu_addr = 0; 96 97 assert(gpio_pin < SECUMOD_MAX_PINS && 98 !(gpio_protected & BIT32(gpio_pin))); 99 100 piobu_addr = secumod_base + SECUMOD_PIOBU(gpio_pin); 101 102 if (value == GPIO_LEVEL_HIGH) 103 io_setbits32(piobu_addr, SECUMOD_PIOBU_SOD); 104 else 105 io_clrbits32(piobu_addr, SECUMOD_PIOBU_SOD); 106 } 107 108 /* 109 * Get direction from GPIO controller 110 * chip: pointer to GPIO controller chip instance 111 * gpio_pin: pin from which direction needs to be read 112 */ 113 static enum gpio_dir gpio_get_direction(struct gpio_chip *chip __unused, 114 unsigned int gpio_pin) 115 { 116 vaddr_t piobu_addr = 0; 117 uint32_t piobu = 0; 118 119 assert(gpio_pin < SECUMOD_MAX_PINS && 120 !(gpio_protected & BIT32(gpio_pin))); 121 122 piobu_addr = secumod_base + SECUMOD_PIOBU(gpio_pin); 123 piobu = io_read32(piobu_addr); 124 125 if (piobu & SECUMOD_PIOBU_OUTPUT) 126 return GPIO_DIR_OUT; 127 else 128 return GPIO_DIR_IN; 129 } 130 131 /* 132 * Set direction for GPIO controller 133 * chip: pointer to GPIO controller chip instance 134 * gpio_pin: pin on which direction needs to be set 135 * direction: direction which needs to be set on pin 136 */ 137 static void gpio_set_direction(struct gpio_chip *chip __unused, 138 unsigned int gpio_pin, enum gpio_dir direction) 139 { 140 vaddr_t piobu_addr = 0; 141 142 assert(gpio_pin < SECUMOD_MAX_PINS && 143 !(gpio_protected & BIT32(gpio_pin))); 144 145 piobu_addr = secumod_base + SECUMOD_PIOBU(gpio_pin); 146 147 if (direction == GPIO_DIR_OUT) 148 io_setbits32(piobu_addr, SECUMOD_PIOBU_OUTPUT); 149 else 150 io_clrbits32(piobu_addr, SECUMOD_PIOBU_OUTPUT); 151 } 152 153 /* 154 * Get interrupt from GPIO controller 155 * chip: pointer to GPIO controller chip instance 156 * gpio_pin: pin from which interrupt value needs to be read 157 */ 158 static enum gpio_interrupt gpio_get_interrupt(struct gpio_chip *chip __unused, 159 unsigned int gpio_pin) 160 { 161 vaddr_t nimpr_addr = secumod_base + SECUMOD_NIMPR; 162 uint32_t data = 0; 163 164 assert(gpio_pin < SECUMOD_MAX_PINS && 165 !(gpio_protected & BIT32(gpio_pin))); 166 167 data = io_read32(nimpr_addr); 168 169 if (data & SECUMOD_PIN_VAL(gpio_pin)) 170 return GPIO_INTERRUPT_ENABLE; 171 else 172 return GPIO_INTERRUPT_DISABLE; 173 } 174 175 /* 176 * Set interrupt event for GPIO controller 177 * chip: pointer to GPIO controller chip instance 178 * gpio_pin: pin on which interrupt value needs to be set 179 * interrupt: interrupt value which needs to be set on pin 180 */ 181 static void gpio_set_interrupt(struct gpio_chip *chip __unused, 182 unsigned int gpio_pin, 183 enum gpio_interrupt interrupt) 184 { 185 vaddr_t niepr_addr = secumod_base + SECUMOD_NIEPR; 186 187 assert(gpio_pin < SECUMOD_MAX_PINS && 188 !(gpio_protected & BIT32(gpio_pin))); 189 190 if (interrupt == GPIO_INTERRUPT_ENABLE) 191 io_setbits32(niepr_addr, SECUMOD_PIN_VAL(gpio_pin)); 192 else 193 io_clrbits32(niepr_addr, SECUMOD_PIN_VAL(gpio_pin)); 194 } 195 196 static const struct gpio_ops atmel_piobu_ops = { 197 .get_direction = gpio_get_direction, 198 .set_direction = gpio_set_direction, 199 .get_value = gpio_get_value, 200 .set_value = gpio_set_value, 201 .get_interrupt = gpio_get_interrupt, 202 .set_interrupt = gpio_set_interrupt, 203 }; 204 205 static enum itr_return secumod_it_handler(struct itr_handler *handler __unused) 206 { 207 int i = 0; 208 struct optee_rtc_time tm = { }; 209 TEE_Result res = TEE_ERROR_GENERIC; 210 uint32_t sr = io_read32(secumod_base + SECUMOD_SR); 211 212 for (i = 0; i < SECUMOD_MAX_PINS; i++) { 213 if (sr & SECUMOD_PIN_VAL(i)) 214 EMSG("Detected tampering on pin %d", i); 215 } 216 217 if (sr & SECUMOD_SR_JTAG) 218 EMSG("JTAG tampering attempt"); 219 220 if (sr & SECUMOD_SR_TST_PIN) 221 EMSG("Test pin tampering attempt"); 222 223 res = atmel_rtc_get_tamper_timestamp(&tm); 224 if (!res) { 225 EMSG("Date of tampering: %02"PRIu32"/%02"PRIu32"/%02"PRIu32"", 226 tm.tm_mday, tm.tm_mon, tm.tm_year); 227 EMSG("Time of tampering: %02"PRIu32":%02"PRIu32":%02"PRIu32"", 228 tm.tm_hour, tm.tm_min, tm.tm_sec); 229 } 230 231 io_write32(secumod_base + SECUMOD_SCR, 232 SECUMOD_PIN_MASK << SECUMOD_PIN_SHIFT); 233 234 panic("Tampering detected, system halted"); 235 236 return ITRR_HANDLED; 237 } 238 239 static struct itr_handler secumod_itr_handler = { 240 .it = AT91C_ID_SECUMOD, 241 .handler = secumod_it_handler, 242 }; 243 244 static void secumod_interrupt_init(void) 245 { 246 itr_add_type_prio(&secumod_itr_handler, IRQ_TYPE_LEVEL_HIGH, 7); 247 itr_enable(secumod_itr_handler.it); 248 } 249 250 static void secumod_cfg_input_pio(uint8_t gpio_pin, uint32_t config) 251 { 252 vaddr_t piobu_addr = 0; 253 uint8_t afv = 0; 254 uint8_t rfv = 0; 255 uint8_t pull_mode = PIOBU_PIN_PULL_NONE; 256 uint8_t def_level = PIOBU_PIN_DEF_LEVEL_LOW; 257 258 assert(gpio_pin < SECUMOD_MAX_PINS); 259 260 piobu_addr = secumod_base + SECUMOD_PIOBU(gpio_pin); 261 262 /* Set GPIO as input */ 263 io_clrbits32(piobu_addr, SECUMOD_PIOBU_OUTPUT); 264 265 afv = PIOBU_PIN_AFV(config); 266 rfv = PIOBU_PIN_RFV(config); 267 pull_mode = PIOBU_PIN_PULL_MODE(config); 268 def_level = PIOBU_PIN_DEF_LEVEL(config); 269 270 io_write32(piobu_addr, afv | rfv << SECUMOD_PIOBU_RFV_SHIFT | 271 pull_mode << SECUMOD_PIOBU_PULLUP_SHIFT | 272 def_level << SECUMOD_PIOBU_SWITCH_SHIFT); 273 274 /* Enable Tampering Interrupt */ 275 gpio_set_interrupt(&secumod_chip, gpio_pin, GPIO_INTERRUPT_ENABLE); 276 277 /* Enable Intrusion Detection */ 278 io_setbits32(secumod_base + SECUMOD_NMPR, SECUMOD_PIN_VAL(gpio_pin)); 279 280 /* Enable Wakeup */ 281 if (PIOBU_PIN_WAKEUP(config)) 282 io_setbits32(secumod_base + SECUMOD_WKPR, 283 SECUMOD_PIN_VAL(gpio_pin)); 284 285 gpio_protected |= BIT32(gpio_pin); 286 } 287 288 static void secumod_hw_init(const void *fdt, int node) 289 { 290 int i = 0; 291 int len = 0; 292 uint8_t gpio_pin = 0; 293 uint32_t config = 0; 294 const uint32_t *prop = NULL; 295 296 /* Disable JTAG Reset and Debug */ 297 io_write32(secumod_base + SECUMOD_JTAGCR, SECUMOD_JTAGCR_FNTRST); 298 299 /* Switch IOs to normal mode */ 300 io_write32(secumod_base + SECUMOD_CR, SECUMOD_CR_KEY | 301 SECUMOD_CR_NORMAL); 302 303 /* Clear all detection intrusion in normal mode */ 304 io_write32(secumod_base + SECUMOD_NMPR, 0); 305 306 /* Clear Alarms */ 307 io_write32(secumod_base + SECUMOD_SCR, 308 SECUMOD_PIN_MASK << SECUMOD_PIN_SHIFT); 309 310 /* Configure each IOs */ 311 prop = fdt_getprop(fdt, node, "gpios", &len); 312 if (!prop) 313 return; 314 315 len /= sizeof(uint32_t); 316 for (i = 0; i < len; i += DT_GPIO_CELLS) { 317 gpio_pin = fdt32_to_cpu(prop[i]); 318 config = fdt32_to_cpu(prop[i + 1]); 319 320 secumod_cfg_input_pio(gpio_pin, config); 321 } 322 } 323 324 #ifdef CFG_PM_ARM32 325 static TEE_Result piobu_pm(enum pm_op op, uint32_t pm_hint __unused, 326 const struct pm_callback_handle *hdl __unused) 327 { 328 switch (op) { 329 case PM_OP_RESUME: 330 io_write32(secumod_base + SECUMOD_CR, SECUMOD_CR_KEY | 331 SECUMOD_CR_NORMAL); 332 break; 333 case PM_OP_SUSPEND: 334 /* Enter backup mode before suspending */ 335 io_write32(secumod_base + SECUMOD_CR, SECUMOD_CR_KEY | 336 SECUMOD_CR_BACKUP); 337 break; 338 default: 339 panic("Invalid PM operation"); 340 } 341 342 return TEE_SUCCESS; 343 } 344 345 static void piobu_register_pm(void) 346 { 347 register_pm_driver_cb(piobu_pm, NULL, "piobu"); 348 } 349 #else 350 static void piobu_register_pm(void) {} 351 #endif 352 353 static TEE_Result atmel_secumod_probe(const void *fdt, int node, 354 const void *compat_data __unused) 355 { 356 size_t size = 0; 357 358 if (secumod_base) 359 return TEE_ERROR_GENERIC; 360 361 if (dt_map_dev(fdt, node, &secumod_base, &size, DT_MAP_AUTO) < 0) 362 return TEE_ERROR_GENERIC; 363 364 secumod_hw_init(fdt, node); 365 secumod_interrupt_init(); 366 367 secumod_chip.ops = &atmel_piobu_ops; 368 369 piobu_register_pm(); 370 371 return TEE_SUCCESS; 372 } 373 374 static const struct dt_device_match atmel_secumod_match_table[] = { 375 { .compatible = "atmel,sama5d2-secumod" }, 376 { } 377 }; 378 379 DEFINE_DT_DRIVER(atmel_secumod_dt_driver) = { 380 .name = "atmel_secumod", 381 .type = DT_DRIVER_NOTYPE, 382 .match_table = atmel_secumod_match_table, 383 .probe = atmel_secumod_probe, 384 }; 385