1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015 Atmel Corporation, 4 * Nicolas Ferre <nicolas.ferre@atmel.com> 5 * Copyright (c) 2021, Microchip 6 */ 7 8 #include <drivers/atmel_shdwc.h> 9 #include <drivers/sam/at91_ddr.h> 10 #include <drivers/pm/sam/atmel_pm.h> 11 #include <io.h> 12 #include <kernel/dt.h> 13 #include <kernel/dt_driver.h> 14 #include <kernel/thread.h> 15 #include <libfdt.h> 16 #include <matrix.h> 17 #include <sama5d2.h> 18 #include <stdbool.h> 19 #include <tee_api_defines.h> 20 #include <tee_api_types.h> 21 #include <trace.h> 22 #include <types_ext.h> 23 #include <util.h> 24 25 #include "at91_clk.h" 26 27 #define SHDW_WK_PIN(reg, cfg) ((reg) & \ 28 AT91_SHDW_WKUPIS((cfg)->wkup_pin_input)) 29 #define SHDW_RTCWK(reg, cfg) (((reg) >> ((cfg)->sr_rtcwk_shift)) & 0x1) 30 #define SHDW_RTTWK(reg, cfg) (((reg) >> ((cfg)->sr_rttwk_shift)) & 0x1) 31 #define SHDW_RTCWKEN(cfg) BIT((cfg)->mr_rtcwk_shift) 32 #define SHDW_RTTWKEN(cfg) BIT((cfg)->mr_rttwk_shift) 33 34 #define SLOW_CLK_FREQ 32768ULL 35 #define DBC_PERIOD_US(x) DIV_ROUND_UP((1000000ULL * (x)), SLOW_CLK_FREQ) 36 37 static vaddr_t shdwc_base; 38 static vaddr_t mpddrc_base; 39 40 bool atmel_shdwc_available(void) 41 { 42 return shdwc_base != 0; 43 } 44 45 void __noreturn atmel_shdwc_shutdown(void) 46 { 47 vaddr_t pmc_base = at91_pmc_get_base(); 48 49 /* 50 * Mask exception before entering assembly which does not expect to be 51 * interrupted. 52 */ 53 thread_mask_exceptions(THREAD_EXCP_ALL); 54 55 __atmel_shdwc_shutdown(mpddrc_base, shdwc_base, pmc_base); 56 57 /* We are going to shutdown the CPU so we will never hit this loop */ 58 while (true) 59 ; 60 } 61 62 static const unsigned long long sdwc_dbc_period[] = { 63 0, 3, 32, 512, 4096, 32768, 64 }; 65 66 static uint32_t at91_shdwc_debouncer_value(uint32_t in_period_us) 67 { 68 int i = 0; 69 int max_idx = ARRAY_SIZE(sdwc_dbc_period) - 1; 70 uint64_t period_us = 0; 71 uint64_t max_period_us = DBC_PERIOD_US(sdwc_dbc_period[max_idx]); 72 73 if (in_period_us > max_period_us) { 74 DMSG("debouncer period %"PRIu32" too big, using %"PRIu64" us", 75 in_period_us, max_period_us); 76 return max_idx; 77 } 78 79 for (i = max_idx - 1; i > 0; i--) { 80 period_us = DBC_PERIOD_US(sdwc_dbc_period[i]); 81 if (in_period_us > period_us) 82 break; 83 } 84 85 return i + 1; 86 } 87 88 static uint32_t at91_shdwc_get_wakeup_input(const void *fdt, int np) 89 { 90 const uint32_t *prop = NULL; 91 uint32_t wk_input_mask = 0; 92 uint32_t wuir = 0; 93 uint32_t wk_input = 0; 94 int child = 0; 95 int len = 0; 96 97 fdt_for_each_subnode(child, fdt, np) { 98 prop = fdt_getprop(fdt, child, "reg", &len); 99 if (!prop || len != sizeof(uint32_t)) { 100 DMSG("reg property is missing for node %s", 101 fdt_get_name(fdt, child, NULL)); 102 continue; 103 } 104 wk_input = fdt32_to_cpu(*prop); 105 wk_input_mask = BIT32(wk_input); 106 if (!(wk_input_mask & AT91_SHDW_WKUPEN_MASK)) { 107 DMSG("wake-up input %"PRId32" out of bounds ignore", 108 wk_input); 109 continue; 110 } 111 wuir |= wk_input_mask; 112 113 if (fdt_getprop(fdt, child, "atmel,wakeup-active-high", NULL)) 114 wuir |= AT91_SHDW_WKUPT(wk_input); 115 } 116 117 return wuir; 118 } 119 120 static void at91_shdwc_dt_configure(const void *fdt, int np) 121 { 122 const uint32_t *prop = NULL; 123 uint32_t mode = 0; 124 uint32_t tmp = 0; 125 uint32_t input = 0; 126 int len = 0; 127 128 prop = fdt_getprop(fdt, np, "debounce-delay-us", &len); 129 if (prop && len == sizeof(uint32_t)) { 130 tmp = fdt32_to_cpu(*prop); 131 mode |= AT91_SHDW_WKUPDBC(at91_shdwc_debouncer_value(tmp)); 132 } 133 134 if (fdt_getprop(fdt, np, "atmel,wakeup-rtc-timer", &len)) 135 mode |= AT91_SHDW_RTCWKEN; 136 137 io_write32(shdwc_base + AT91_SHDW_MR, mode); 138 139 input = at91_shdwc_get_wakeup_input(fdt, np); 140 io_write32(shdwc_base + AT91_SHDW_WUIR, input); 141 } 142 143 static TEE_Result atmel_shdwc_probe(const void *fdt, int node, 144 const void *compat_data __unused) 145 { 146 int ddr_node = 0; 147 size_t size = 0; 148 uint32_t ddr = AT91_DDRSDRC_MD_LPDDR2; 149 150 /* 151 * Assembly code relies on the fact that there is only one CPU to avoid 152 * any other one to invalidate TLB/I-Cache. 153 */ 154 COMPILE_TIME_ASSERT(CFG_TEE_CORE_NB_CORE == 1); 155 156 if (fdt_get_status(fdt, node) != DT_STATUS_OK_SEC) 157 return TEE_ERROR_BAD_PARAMETERS; 158 159 matrix_configure_periph_secure(AT91C_ID_SYS); 160 161 if (dt_map_dev(fdt, node, &shdwc_base, &size, DT_MAP_AUTO) < 0) 162 return TEE_ERROR_GENERIC; 163 164 ddr_node = fdt_node_offset_by_compatible(fdt, -1, 165 "atmel,sama5d3-ddramc"); 166 if (ddr_node < 0) 167 return TEE_ERROR_GENERIC; 168 169 if (dt_map_dev(fdt, ddr_node, &mpddrc_base, &size, DT_MAP_AUTO) < 0) 170 return TEE_ERROR_GENERIC; 171 172 ddr = io_read32(mpddrc_base + AT91_DDRSDRC_MDR) & AT91_DDRSDRC_MD; 173 if (ddr != AT91_DDRSDRC_MD_LPDDR2 && ddr != AT91_DDRSDRC_MD_LPDDR3) 174 mpddrc_base = 0; 175 176 at91_shdwc_dt_configure(fdt, node); 177 178 return sama5d2_pm_init(fdt, shdwc_base); 179 } 180 181 static const struct dt_device_match atmel_shdwc_match_table[] = { 182 { .compatible = "atmel,sama5d2-shdwc" }, 183 { } 184 }; 185 186 DEFINE_DT_DRIVER(atmel_shdwc_dt_driver) = { 187 .name = "atmel_shdwc", 188 .type = DT_DRIVER_NOTYPE, 189 .match_table = atmel_shdwc_match_table, 190 .probe = atmel_shdwc_probe, 191 }; 192