drivers: imx_ocotp: write support i.MX6ULL

Reuse the same write function as the other i.MX6 SoCs since
the OCOTP IP is the same. i.MX6ULL just has fewer fuse banks
than i.MX6UL.

Reviewed-by: Sahil

drivers: imx_ocotp: write support i.MX6ULL

Reuse the same write function as the other i.MX6 SoCs since
the OCOTP IP is the same. i.MX6ULL just has fewer fuse banks
than i.MX6UL.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[m.felsch@pengutronix.de: adapt function name after renaming]
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: write support i.MX6Q/D/S/DL/UL

Reuse the same write functions as for i.MX8M SoC since they seem to use
the same OCOTP IP core according to the reference manual.

While on it, ren

drivers: imx_ocotp: write support i.MX6Q/D/S/DL/UL

Reuse the same write functions as for i.MX8M SoC since they seem to use
the same OCOTP IP core according to the reference manual.

While on it, rename the fuse write function and the set_timing helper
since it's no longer imx8m specific.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
[m.felsch@pengutronix.de: add function renaming]
[m.felsch@pengutronix.de: adapt commit message]
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: add support to burn fuses

This adds the support to burn fuses on i.MX8M SoCs. This approach assume
that the IPG clock is running at 66.67 MHz which is AHB/2 (AHB max.
clock = 133

drivers: imx_ocotp: add support to burn fuses

This adds the support to burn fuses on i.MX8M SoCs. This approach assume
that the IPG clock is running at 66.67 MHz which is AHB/2 (AHB max.
clock = 133 MHz). Due to lack of HW I added only the i.MX8M support.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: fix ocotp_ctrl_wait_for for i.MX6

Make use of the udelay() function and the newly added
OCOTP_OP_BUSY_TIMEOUT_US to align platforms which don't support
architected timers, like i

drivers: imx_ocotp: fix ocotp_ctrl_wait_for for i.MX6

Make use of the udelay() function and the newly added
OCOTP_OP_BUSY_TIMEOUT_US to align platforms which don't support
architected timers, like i.MX6Q with the ones that support architected
timers.

udelay() can be used since we have added the plat_get_freq() support for
all i.MX SoCs which don't support architected timers previously.

While on it drop the dsb() since the memory is mapped as non-cacheable
device-memory. So there is no need for a data barrier. Keep the isb() to
not send use-less register loads.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: make use of hw timers during ocotp_ctrl_wait_for

Use the ARM architected timer instead of assuming that the CPU is
running at 500MHz and the poll takes around ~20us.

Reviewed-by

drivers: imx_ocotp: make use of hw timers during ocotp_ctrl_wait_for

Use the ARM architected timer instead of assuming that the CPU is
running at 500MHz and the poll takes around ~20us.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: fix imx_ocotp_read g_base_addr and g_ocotp check

Check the g_base_addr and g_ocotp before do the first access.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by

drivers: imx_ocotp: fix imx_ocotp_read g_base_addr and g_ocotp check

Check the g_base_addr and g_ocotp before do the first access.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: fix clearing the error bit

According the reference manuals the ERROR bit should be cleared by
writing a '1' to the OCOTP_CTRL_CLR register and not by writing to the
OCOTP_CTRL di

drivers: imx_ocotp: fix clearing the error bit

According the reference manuals the ERROR bit should be cleared by
writing a '1' to the OCOTP_CTRL_CLR register and not by writing to the
OCOTP_CTRL direct.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: fix error/busy defines for i.MX8MP

The i.MX8MP has an OCOTP_CTRL_ADDR field which is 8-bit wide compared to
all other current supported i.MX SoCs. Due to the larger ADDR field al

drivers: imx_ocotp: fix error/busy defines for i.MX8MP

The i.MX8MP has an OCOTP_CTRL_ADDR field which is 8-bit wide compared to
all other current supported i.MX SoCs. Due to the larger ADDR field all
bits shifted by 1 bit.

Also make some minor style fixes while on it by replacing the mix of
tabs and spaces with tabs-only.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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driver: crypto: hisilicon: fix qm timeout variable type

The type of the timeout variable is fixed to prevent overflow

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wi

driver: crypto: hisilicon: fix qm timeout variable type

The type of the timeout variable is fixed to prevent overflow

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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driver: crypto: hisilicon: fix CKEY_LEN macro value

Fix CKEY_LEN macro value for hisilicon SEC driver

Fixes: 562874beda99 ("drivers: crypto: hisilicon: Add cipher algorithm")
Signed-off-by: Zexi Yu

driver: crypto: hisilicon: fix CKEY_LEN macro value

Fix CKEY_LEN macro value for hisilicon SEC driver

Fixes: 562874beda99 ("drivers: crypto: hisilicon: Add cipher algorithm")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: fix SM2 ECC encrypt and decrypt

Adds checks that the destination buffer has room for the result in
ecc_sm2_decrypt() and ecc_sm2_encrypt(). Note that these two functions
not reachab

drivers: crypto: fix SM2 ECC encrypt and decrypt

Adds checks that the destination buffer has room for the result in
ecc_sm2_decrypt() and ecc_sm2_encrypt(). Note that these two functions
not reachable upstream since none of the crypto drivers registers ECC
encrypt or decrypt drivers. So fix this before it becomes a problem.

Fixes: f4f85ac774af ("drivers: crypto: add SM2 ECC encrypt and decrypt")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Zexi Yu <yuzexi@hisilicon.com>

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gic: refactor implementation of GICv3 to add GICv4 support

Refactor the definitions of GICv3 to facilitate adding support for
GICv4 by:
* Add macro for registers frame sizes based on GIC versions.
*

gic: refactor implementation of GICv3 to add GICv4 support

Refactor the definitions of GICv3 to facilitate adding support for
GICv4 by:
* Add macro for registers frame sizes based on GIC versions.
* Add macro for number of frame count for GICR based on GICv3 or GICv4.
* Add single GICR region size definition (GIC_REDIST_REG_SIZE)
based on GIC version in platform independent include/drivers/gic.h
along with existing GIC_CPU_REG_SIZE and GIC_DIST_REG_SIZE
definitions.
* Amend usage of the now platform independent GIC_REDIST_REG_SIZE
as it no longer includes a multiplication by the number of core on
the target platform.
* Sort in ascending order the listing of GICR register definitions and
add comments to denote each definitions sections.
* Add definitions for each GICR frames.
* Ensure that all relevant code sections that compile for CFG_ARM_GICV3
also compile for CFG_ARM_GICV4.

Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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pta: stm32mp: add debug access PTA

Add the debug access PTA that is responsible of validating whether
a given debug profile is configured or not. This basically means that
the debug configuration sh

pta: stm32mp: add debug access PTA

Add the debug access PTA that is responsible of validating whether
a given debug profile is configured or not. This basically means that
the debug configuration should allow (at least!) access to the debug
peripherals requiring the debug profile being checked.

For now, as it is specific to BSEC, only embed the PTA if the BSEC support
is embedded as well.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@st.com>

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drivers: caam: improve empty aad updates

In caam_ae_update_aad an update without data was already handled as long
as the data pointer was NULL. This change updates the logic to also
account for the

drivers: caam: improve empty aad updates

In caam_ae_update_aad an update without data was already handled as long
as the data pointer was NULL. This change updates the logic to also
account for the case where the pointer is non-null but the length is
zero. When that was the case caam_cpy_buf would exit early without
allocating, leaving aad->data as NULL, making caam_cpy_block_src fail.

This was found through the Android Keymint tests because Rust represents
empty buffers (Rust slices) with a non-null pointer and length 0.

Fixes: faaf0c5975d2 ("drivers: caam: Add AES GCM")
Signed-off-by: Martin Nyhus <martin@nyhus.dev>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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drivers: qcom: prng: add PRNG driver

The Qualcomm PRNG hardware generates cryptographic keys and random
numbers.

The PRNG is configured by the first-stage bootloader. This includes the
reseed frequ

drivers: qcom: prng: add PRNG driver

The Qualcomm PRNG hardware generates cryptographic keys and random
numbers.

The PRNG is configured by the first-stage bootloader. This includes the
reseed frequency.

This driver only consumes the generated output.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Tony Hamilton <tonyh@qti.qualcomm.com>

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drivers: qcom: ramblur: configure pIMEM access

Configure memory access to enable execution of Trusted Applications.

OP-TEE and its Trusted Applications execute from pIMEM, a region protected
by the

drivers: qcom: ramblur: configure pIMEM access

Configure memory access to enable execution of Trusted Applications.

OP-TEE and its Trusted Applications execute from pIMEM, a region protected
by the RAMBLUR IP block.

RAMBLUR provides anti-rollback protection as well as confidentiality and
integrity guarantees for the memory region under its control.

Any agent accessing the pIMEM-protected region performs normal reads or
writes to the pIMEM address range in the SNoC. The SNoC routes these
transactions to the pIMEM slave port, and pIMEM remasters them to DDR.

For write transactions, pIMEM applies the required cryptographic
operations before committing data to DDR.

For read transactions, pIMEM applies the corresponding cryptographic
operations before returning the data from DDR to the requesting master.

The reserved DDR region used by pIMEM to store cryptographically
processed data and associated cryptographic state is referred to as the
pIMEM vault.

With the current U-Boot (tag 2026.01-rc3), the pIMEM Vault DDR
reservation is derived from the TZ node in U-Boot’s built-in device tree
(specifically the trusted_apps_mem reserved-memory node).

U-Boot uses this node to construct the EFI memory map that is later
passed to the kernel.

A future update will remove this dependency on the built-in device tree.
Instead, U-Boot will obtain the memory configuration directly from SMEM.
Because of this transition, the current version of the driver does not
generate a DT overlay for U-Boot to consume.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Tony Hamilton <tonyh@qti.qualcomm.com>

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drivers: ele: update struct get_info_rsp{} fields

update struct get_info_rsp{} fields

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.or

drivers: ele: update struct get_info_rsp{} fields

update struct get_info_rsp{} fields

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: ele: enable getting HUK/RNG from ELE on i.MX943

Enable support for getting HUK/RNG from ELE on i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <r

drivers: ele: enable getting HUK/RNG from ELE on i.MX943

Enable support for getting HUK/RNG from ELE on i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: imx_mu: add support for i.MX943

Enable MU driver support for i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked

drivers: imx_mu: add support for i.MX943

Enable MU driver support for i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_i2c: fallback to interrupt access when no bottom half

Change stm32_i2c driver to allow I2C transfers in interrupt context
before bottom half thread is initialized and after it's relea

drivers: stm32_i2c: fallback to interrupt access when no bottom half

Change stm32_i2c driver to allow I2C transfers in interrupt context
before bottom half thread is initialized and after it's released.

This can be needed by PMIC driver to handle PMCI interrupt events
when bottom half thread is not supported by normal wold.
In that case, PMIC driver would need to register its interrupt to
stm32_i2c driver.

Thread accesses to the bus still start by locking the I2C bus mutex.
Before using the bus, the sequence now masks the PMIC interrupt and
polls (with timeout) on I2C bus access atomic lock. This lock
may be held by an I2C transfer currently executing in an interrupt
context. A 100ms timeout is short enough to also allow
debug console traces in the interrupt sequence. Masking the interrupt
before polling the lock ensures no new pending interrupt will interrupt
us (and execute a I2C transfer) while the thread context accesses the
I2C bus.

Interrupt accesses to the bus atomically set/clear the I2C bus access
lock while executing the interrupt sequence.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_i2c: add support of stm32mp2 family

Add compatible st,stm32mp25-i2c to support stm32mp2x SoCs.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carri

drivers: stm32_i2c: add support of stm32mp2 family

Add compatible st,stm32mp25-i2c to support stm32mp2x SoCs.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: ele: remove sab_init() initialization

ELE firmware has been divided into 2 firmwares for i.MX8ULP and i.MX95:
Primary and secondary firmware.
SAB init command is in Secondary firmware, whic

drivers: ele: remove sab_init() initialization

ELE firmware has been divided into 2 firmwares for i.MX8ULP and i.MX95:
Primary and secondary firmware.
SAB init command is in Secondary firmware, which will be loaded when
rootfs comes up, so this command is not available when OP-TEE is
initializing.
Moreover, we are not using any ELE command which is available in
secondary firmware, So removing sab_init() function.
Will add it when it will be used in driver.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: ele: update struct get_info_rsp{} fields

There has been an addition of PQC related fields in
Get Info Command response for i.MX95.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Ac

drivers: ele: update struct get_info_rsp{} fields

There has been an addition of PQC related fields in
Get Info Command response for i.MX95.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: ele: enable getting HUK/RNG from ELE on imx95

Enable support of getting HUK and RNG from ELE on imx95

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.

drivers: ele: enable getting HUK/RNG from ELE on imx95

Enable support of getting HUK and RNG from ELE on imx95

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: imx: mu: add support for imx95

Add MU driver support for imx95

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>