1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /*
3 * Copyright (c) 2017-2023, STMicroelectronics
4 */
5
6 #ifndef __DRIVERS_STM32_I2C_H
7 #define __DRIVERS_STM32_I2C_H
8
9 #include <drivers/clk.h>
10 #include <drivers/i2c.h>
11 #include <drivers/pinctrl.h>
12 #include <kernel/dt.h>
13 #include <kernel/dt_driver.h>
14 #include <kernel/mutex_pm_aware.h>
15 #include <mm/core_memprot.h>
16 #include <stdbool.h>
17 #include <stdint.h>
18 #include <sys/queue.h>
19 #include <util.h>
20 #include <types_ext.h>
21
22 /*
23 * I2C specification values as per version 6.0, 4th of April 2014 [1],
24 * table 10 page 48: Characteristics of the SDA and SCL bus lines for
25 * Standard, Fast, and Fast-mode Plus I2C-bus devices.
26 *
27 * [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf
28 */
29 #define I2C_STANDARD_RATE U(100000)
30 #define I2C_FAST_RATE U(400000)
31 #define I2C_FAST_PLUS_RATE U(1000000)
32
33 /*
34 * struct stm32_i2c_init_s - STM32 I2C configuration data
35 *
36 * @pbase: I2C interface base address
37 * @reg_size: I2C interface register map size
38 * @clock: I2C bus/interface clock
39 * @addr_mode_10b_not_7b: True if 10bit addressing mode, otherwise 7bit mode
40 * @own_address1: 7-bit or 10-bit first device own address.
41 * @dual_address_mode: True if enabling Dual-Addressing mode
42 * @own_address2: 7-bit second device own address (Dual-Addressing mode)
43 * @own_address2_masks: Acknowledge mask address (Dual-Addressing mode)
44 * @general_call_mode: True if enbling General-Call mode
45 * @no_stretch_mode: If enabling the No-Stretch mode
46 * @rise_time: SCL clock pin rising time in nanoseconds
47 * @fall_time: SCL clock pin falling time in nanoseconds
48 * @bus_rate: Specifies the I2C clock frequency in Hertz
49 * @analog_filter: True if enabling analog filter
50 * @digital_filter_coef: filter coef (below STM32_I2C_DIGITAL_FILTER_MAX)
51 */
52 struct stm32_i2c_init_s {
53 paddr_t pbase;
54 size_t reg_size;
55 struct clk *clock;
56 bool addr_mode_10b_not_7b;
57 uint32_t own_address1;
58 bool dual_address_mode;
59 uint32_t own_address2;
60 uint32_t own_address2_masks;
61 bool general_call_mode;
62 bool no_stretch_mode;
63 uint32_t rise_time;
64 uint32_t fall_time;
65 uint32_t bus_rate;
66 bool analog_filter;
67 uint8_t digital_filter_coef;
68 };
69
70 enum i2c_state_e {
71 I2C_STATE_RESET, /* Not yet initialized */
72 I2C_STATE_READY, /* Ready for use */
73 I2C_STATE_BUSY, /* Internal process ongoing */
74 I2C_STATE_BUSY_TX, /* Data Transmission ongoing */
75 I2C_STATE_BUSY_RX, /* Data Reception ongoing */
76 I2C_STATE_SUSPENDED, /* Bus is supended */
77 };
78
79 enum i2c_mode_e {
80 I2C_MODE_NONE, /* No active communication */
81 I2C_MODE_MASTER, /* Communication in Master Mode */
82 I2C_MODE_SLAVE, /* Communication in Slave Mode */
83 I2C_MODE_MEM, /* Communication in Memory Mode */
84 };
85
86 #define I2C_ERROR_NONE U(0x0)
87 #define I2C_ERROR_BERR BIT(0)
88 #define I2C_ERROR_ARLO BIT(1)
89 #define I2C_ERROR_ACKF BIT(2)
90 #define I2C_ERROR_OVR BIT(3)
91 #define I2C_ERROR_DMA BIT(4)
92 #define I2C_ERROR_TIMEOUT BIT(5)
93 #define I2C_ERROR_SIZE BIT(6)
94
95 /* I2C interface registers state */
96 struct i2c_cfg {
97 uint32_t timingr;
98 uint32_t oar1;
99 uint32_t oar2;
100 uint32_t cr1;
101 uint32_t cr2;
102 };
103
104 /*
105 * struct stm32_itr_dep - Interrupts requesting atomic access
106 *
107 * @chip: Interrupt chip reference
108 * @num: Target tnterrupt number in @chip context
109 * @link: Link in registered consumer list
110 *
111 * Consumer requesting interrupt accesses to the I2C bus
112 * while executing in interrupt context, to handle external
113 * device events before a thread context like the bottom
114 * half is ready.
115 */
116 struct stm32_itr_dep {
117 struct itr_chip *chip;
118 size_t num;
119 SLIST_ENTRY(stm32_itr_dep) link;
120 };
121
122 /*
123 * I2C bus device
124 * @base: I2C SoC registers base address
125 * @reg_size: I2C SoC registers address map size
126 * @clock: clock ID
127 * @i2c_state: Driver state ID I2C_STATE_*
128 * @i2c_err: Last error code I2C_ERROR_*
129 * @saved_timing: Saved timing value if already computed
130 * @saved_frequency: Saved frequency value if already computed
131 * @sec_cfg: I2C registers configuration storage
132 * @pinctrl: Pin control configuration for the I2C bus in active state
133 * @pinctrl_sleep: Pin control configuration for the I2C bus in standby state
134 * @mu: Protection on concurrent access to the I2C bus considering PM context
135 * @i2c_secure: Indicates that the I2C is secure
136 * @consumer_itr_lock: 1 when an interrupt handler accesses the bus, 0 if not
137 * @consumer_itr_head: List head of interrupts registered for interrupt accesses
138 * @consumer_itr_masked: True if consumer interrupts were masked
139 */
140 struct i2c_handle_s {
141 struct io_pa_va base;
142 size_t reg_size;
143 struct clk *clock;
144 enum i2c_state_e i2c_state;
145 uint32_t i2c_err;
146 uint32_t saved_timing;
147 unsigned long saved_frequency;
148 struct i2c_cfg sec_cfg;
149 struct pinctrl_state *pinctrl;
150 struct pinctrl_state *pinctrl_sleep;
151 struct mutex_pm_aware mu;
152 bool i2c_secure;
153 int consumer_itr_lock;
154 SLIST_HEAD(, stm32_itr_dep) consumer_itr_head;
155 bool consumer_itr_masked;
156 };
157
158 /*
159 * struct stm32_i2c_dev - Bus consumer device over an STM32 I2C bus
160 * @i2c_dev: I2C consumer instance
161 * @i2c_ctrl: I2C bus control operation
162 * @handle: Handle on a single STM32 I2C bus interface
163 */
164 struct stm32_i2c_dev {
165 struct i2c_dev i2c_dev;
166 struct i2c_ctrl i2c_ctrl;
167 struct i2c_handle_s *handle;
168 };
169
170 /* STM32 specific defines */
171 #define STM32_I2C_RISE_TIME_DEFAULT U(25) /* ns */
172 #define STM32_I2C_FALL_TIME_DEFAULT U(10) /* ns */
173 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN U(50) /* ns */
174 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX U(260) /* ns */
175 #define STM32_I2C_DIGITAL_FILTER_MAX U(16)
176
177 /*
178 * Fill struct stm32_i2c_init_s from DT content for a given I2C node
179 *
180 * @fdt: Reference to DT
181 * @node: Target I2C node in the DT
182 * @init: Output stm32_i2c_init_s structure
183 * @pinctrl_active: Output active I2C pinctrl state
184 * @pinctrl_sleep: Output suspended I2C pinctrl state
185 * Return a TEE_Result compliant value
186 */
187 TEE_Result stm32_i2c_get_setup_from_fdt(void *fdt, int node,
188 struct stm32_i2c_init_s *init,
189 struct pinctrl_state **pinctrl_active,
190 struct pinctrl_state **pinctrl_sleep);
191
192 /*
193 * Initialize I2C bus handle from input configuration directives
194 *
195 * @hi2c: Reference to I2C bus handle structure
196 * @init_data: Input stm32_i2c_init_s structure
197 * Return 0 on success else a negative value
198 */
199 int stm32_i2c_init(struct i2c_handle_s *hi2c,
200 struct stm32_i2c_init_s *init_data);
201
202 /*
203 * Send a memory write request in the I2C bus
204 *
205 * @hi2c: Reference to I2C bus handle structure
206 * @dev_addr: Target device I2C address
207 * @mem_addr: Target device memory address
208 * @mem_addr_size: Byte size of internal memory address
209 * @p_data: Data to be written
210 * @size: Byte size of the data to be written
211 * @timeout_ms: Timeout value in milliseconds
212 * Return 0 on success else a negative value
213 */
214 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr,
215 uint32_t mem_addr, uint32_t mem_addr_size,
216 uint8_t *p_data, size_t size, unsigned int timeout_ms);
217
218 /*
219 * Send a memory read request in the I2C bus
220 *
221 * @hi2c: Reference to I2C bus handle structure
222 * @dev_addr: Target device I2C address
223 * @mem_addr: Target device memory address
224 * @mem_addr_size: Byte size of internal memory address
225 * @p_data: Data to be read
226 * @size: Byte size of the data to be read
227 * @timeout_ms: Timeout value in milliseconds
228 * Return 0 on success else a negative value
229 */
230 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr,
231 uint32_t mem_addr, uint32_t mem_addr_size,
232 uint8_t *p_data, size_t size, unsigned int timeout_ms);
233
234 /*
235 * Send a data buffer in master mode on the I2C bus
236 *
237 * @hi2c: Reference to I2C bus handle structure
238 * @dev_addr: Target device I2C address
239 * @p_data: Data to be sent
240 * @size: Byte size of the data to be sent
241 * @timeout_ms: Timeout value in milliseconds
242 * Return 0 on success else a negative value
243 */
244 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr,
245 uint8_t *p_data, size_t size,
246 unsigned int timeout_ms);
247
248 /*
249 * Receive a data buffer in master mode on the I2C bus
250 *
251 * @hi2c: Reference to I2C bus handle structure
252 * @dev_addr: Target device I2C address
253 * @p_data: Buffer for the received data
254 * @size: Byte size of the data to be received
255 * @timeout_ms: Timeout value in milliseconds
256 * Return 0 on success else a negative value
257 */
258 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr,
259 uint8_t *p_data, size_t size,
260 unsigned int timeout_ms);
261
262 /*
263 * Optimized 1 byte read/write function for unpaged sequences.
264 * 8-bit addressing mode / single byte transferred / use default I2C timeout.
265 * Return 0 on success else a negative value
266 */
267 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr,
268 unsigned int mem_addr, uint8_t *p_data,
269 bool write);
270
271 /*
272 * Check link with the I2C device
273 *
274 * @hi2c: Reference to I2C bus handle structure
275 * @dev_addr: Target device I2C address
276 * @trials: Number of attempts of I2C request
277 * @timeout_ms: Timeout value in milliseconds for each I2C request
278 * Return 0 on success else a negative value
279 */
280 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr,
281 unsigned int trials, unsigned int timeout_ms);
282
283 /*
284 * Suspend I2C bus.
285 * Bus owner is reponsible for calling stm32_i2c_suspend().
286 *
287 * @hi2c: Reference to I2C bus handle structure
288 */
289 void stm32_i2c_suspend(struct i2c_handle_s *hi2c);
290
291 /*
292 * Resume I2C bus.
293 * Bus owner is reponsible for calling stm32_i2c_resume().
294 *
295 * @hi2c: Reference to I2C bus handle structure
296 */
297 void stm32_i2c_resume(struct i2c_handle_s *hi2c);
298
299 /*
300 * Return true if I2C bus is enabled for secure world only, false otherwise
301 */
i2c_is_secure(struct i2c_handle_s * hi2c)302 static inline bool i2c_is_secure(struct i2c_handle_s *hi2c)
303 {
304 return hi2c->i2c_secure;
305 }
306
307 /*
308 * Register interrupt for possible I2C bus accesses in interrupt context
309 *
310 * @hi2c: STM32 I2C handle of the bus
311 * @itr_chip: Interrupt chip for the interrupt context access
312 * @itr_num: Interrupt number in @itr_chip for the access
313 *
314 * Register an interrupt (chip and number) for which I2C accesses
315 * must be handled from the interrupt when non-secure world has not
316 * registered for thread execution as the bottom half.
317 */
318 void stm32_i2c_interrupt_access_lockdeps(struct i2c_handle_s *hi2c,
319 struct itr_chip *itr_chip,
320 size_t itr_num);
321 #endif /* __DRIVERS_STM32_I2C_H*/
322