xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision 2157edb3e70e85693b05f7748db7eb093a8d89f8) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8	mx6ulccbv2 \
9
10mx6ull-flavorlist = \
11	mx6ullevk \
12	mx6ulzevk \
13
14mx6q-flavorlist = \
15	mx6qsabrelite \
16	mx6qsabreauto \
17	mx6qsabresd \
18	mx6qhmbedge \
19	mx6qapalis \
20
21mx6qp-flavorlist = \
22	mx6qpsabreauto \
23	mx6qpsabresd \
24
25mx6sl-flavorlist = \
26	mx6slevk
27
28mx6sll-flavorlist = \
29	mx6sllevk
30
31mx6sx-flavorlist = \
32	mx6sxsabreauto \
33	mx6sxsabresd \
34	mx6sxudooneofull \
35
36mx6d-flavorlist = \
37	mx6dhmbedge \
38	mx6dapalis \
39
40mx6dl-flavorlist = \
41	mx6dlsabreauto \
42	mx6dlsabresd \
43	mx6dlhmbedge \
44
45mx6s-flavorlist = \
46	mx6shmbedge \
47	mx6solosabresd \
48	mx6solosabreauto \
49
50mx7d-flavorlist = \
51	mx7dsabresd \
52	mx7dpico_mbl \
53	mx7dclsom \
54
55mx7s-flavorlist = \
56	mx7swarp7 \
57	mx7swarp7_mbl \
58
59mx7ulp-flavorlist = \
60	mx7ulpevk
61
62mx8mq-flavorlist = \
63	mx8mqevk
64
65mx8mm-flavorlist = \
66	mx8mmevk \
67	mx8mm_cl_iot_gate \
68	mx8mm_phyboard_polis \
69	mx8mm_phygate_tauri_l
70
71mx8mn-flavorlist = \
72	mx8mnevk
73
74mx8mp-flavorlist = \
75	mx8mpevk \
76	mx8mp_rsb3720_6g \
77	mx8mp_phyboard_pollux \
78	mx8mp_libra_fpsc
79
80mx8qm-flavorlist = \
81	mx8qmmek \
82
83mx8qx-flavorlist = \
84	mx8qxpmek \
85	mx8dxmek \
86
87mx8dxl-flavorlist = \
88	mx8dxlevk \
89
90mx8ulp-flavorlist = \
91	mx8ulpevk \
92
93mx93-flavorlist = \
94	mx93evk \
95
96mx95-flavorlist = \
97	mx95evk \
98
99mx91-flavorlist = \
100	mx91evk \
101
102mx943-flavorlist = \
103	mx943evk \
104
105ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
106$(call force,CFG_MX6,y)
107$(call force,CFG_MX6UL,y)
108$(call force,CFG_TEE_CORE_NB_CORE,1)
109$(call force,CFG_TZC380,y)
110include core/arch/arm/cpu/cortex-a7.mk
111else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
112$(call force,CFG_MX6,y)
113$(call force,CFG_MX6ULL,y)
114$(call force,CFG_TEE_CORE_NB_CORE,1)
115$(call force,CFG_TZC380,y)
116$(call force,CFG_IMX_CAAM,n)
117$(call force,CFG_NXP_CAAM,n)
118$(call force,CFG_IMX_DCP,y)
119include core/arch/arm/cpu/cortex-a7.mk
120else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
121$(call force,CFG_MX6,y)
122$(call force,CFG_MX6Q,y)
123$(call force,CFG_TEE_CORE_NB_CORE,4)
124$(call force,CFG_TZC380,y)
125else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
126$(call force,CFG_MX6,y)
127$(call force,CFG_MX6QP,y)
128$(call force,CFG_TEE_CORE_NB_CORE,4)
129else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
130$(call force,CFG_MX6,y)
131$(call force,CFG_MX6D,y)
132$(call force,CFG_TEE_CORE_NB_CORE,2)
133$(call force,CFG_TZC380,y)
134else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
135$(call force,CFG_MX6,y)
136$(call force,CFG_MX6DL,y)
137$(call force,CFG_TEE_CORE_NB_CORE,2)
138$(call force,CFG_TZC380,y)
139else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
140$(call force,CFG_MX6,y)
141$(call force,CFG_MX6S,y)
142$(call force,CFG_TEE_CORE_NB_CORE,1)
143else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
144$(call force,CFG_MX6,y)
145$(call force,CFG_MX6SL,y)
146$(call force,CFG_TEE_CORE_NB_CORE,1)
147$(call force,CFG_IMX_CAAM,n)
148$(call force,CFG_NXP_CAAM,n)
149$(call force,CFG_IMX_DCP,y)
150else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
151$(call force,CFG_MX6,y)
152$(call force,CFG_MX6SLL,y)
153$(call force,CFG_TEE_CORE_NB_CORE,1)
154$(call force,CFG_IMX_CAAM,n)
155$(call force,CFG_NXP_CAAM,n)
156$(call force,CFG_IMX_DCP,y)
157$(call force,CFG_NO_SMP,y)
158else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
159$(call force,CFG_MX6,y)
160$(call force,CFG_MX6SX,y)
161$(call force,CFG_TEE_CORE_NB_CORE,1)
162else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
163$(call force,CFG_MX7,y)
164$(call force,CFG_TEE_CORE_NB_CORE,1)
165include core/arch/arm/cpu/cortex-a7.mk
166else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
167$(call force,CFG_MX7,y)
168$(call force,CFG_TEE_CORE_NB_CORE,2)
169include core/arch/arm/cpu/cortex-a7.mk
170else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
171$(call force,CFG_MX7ULP,y)
172$(call force,CFG_TEE_CORE_NB_CORE,1)
173$(call force,CFG_TZC380,n)
174$(call force,CFG_IMX_CSU,n)
175include core/arch/arm/cpu/cortex-a7.mk
176else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
177$(call force,CFG_MX8MQ,y)
178$(call force,CFG_MX8M,y)
179$(call force,CFG_ARM64_core,y)
180$(call force,CFG_TZC380,y)
181CFG_DRAM_BASE ?= 0x40000000
182CFG_TEE_CORE_NB_CORE ?= 4
183else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
184$(call force,CFG_MX8MM,y)
185$(call force,CFG_MX8M,y)
186$(call force,CFG_ARM64_core,y)
187$(call force,CFG_TZC380,y)
188CFG_DRAM_BASE ?= 0x40000000
189CFG_TEE_CORE_NB_CORE ?= 4
190else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
191$(call force,CFG_MX8MN,y)
192$(call force,CFG_MX8M,y)
193$(call force,CFG_ARM64_core,y)
194$(call force,CFG_TZC380,y)
195CFG_DRAM_BASE ?= 0x40000000
196CFG_TEE_CORE_NB_CORE ?= 4
197else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
198$(call force,CFG_MX8MP,y)
199$(call force,CFG_MX8M,y)
200$(call force,CFG_ARM64_core,y)
201$(call force,CFG_TZC380,y)
202CFG_DRAM_BASE ?= 0x40000000
203CFG_TEE_CORE_NB_CORE ?= 4
204else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
205$(call force,CFG_MX8QM,y)
206$(call force,CFG_ARM64_core,y)
207$(call force,CFG_IMX_SNVS,n)
208CFG_IMX_LPUART ?= y
209CFG_DRAM_BASE ?= 0x80000000
210CFG_TEE_CORE_NB_CORE ?= 6
211$(call force,CFG_IMX_OCOTP,n)
212else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
213$(call force,CFG_MX8QX,y)
214$(call force,CFG_ARM64_core,y)
215$(call force,CFG_IMX_SNVS,n)
216CFG_IMX_LPUART ?= y
217CFG_DRAM_BASE ?= 0x80000000
218CFG_TEE_CORE_NB_CORE ?= 4
219$(call force,CFG_IMX_OCOTP,n)
220else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8dxl-flavorlist)))
221$(call force,CFG_MX8DXL,y)
222$(call force,CFG_ARM64_core,y)
223$(call force,CFG_IMX_SNVS,n)
224CFG_IMX_LPUART ?= y
225CFG_DRAM_BASE ?= 0x80000000
226$(call force,CFG_TEE_CORE_NB_CORE,2)
227$(call force,CFG_IMX_OCOTP,n)
228else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8ulp-flavorlist)))
229$(call force,CFG_MX8ULP,y)
230$(call force,CFG_ARM64_core,y)
231CFG_IMX_LPUART ?= y
232CFG_DRAM_BASE ?= 0x80000000
233CFG_TEE_CORE_NB_CORE ?= 2
234$(call force,CFG_NXP_SNVS,n)
235$(call force,CFG_IMX_OCOTP,n)
236CFG_IMX_MU ?= y
237CFG_IMX_ELE ?= n
238else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx93-flavorlist)))
239$(call force,CFG_MX93,y)
240$(call force,CFG_ARM64_core,y)
241CFG_IMX_LPUART ?= y
242CFG_DRAM_BASE ?= 0x80000000
243CFG_TEE_CORE_NB_CORE ?= 2
244$(call force,CFG_NXP_SNVS,n)
245$(call force,CFG_IMX_OCOTP,n)
246$(call force,CFG_TZC380,n)
247$(call force,CFG_CRYPTO_DRIVER,n)
248$(call force,CFG_NXP_CAAM,n)
249CFG_IMX_MU ?= y
250CFG_IMX_ELE ?= y
251else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx95-flavorlist)))
252$(call force,CFG_MX95,y)
253$(call force,CFG_ARM64_core,y)
254CFG_IMX_LPUART ?= y
255CFG_DRAM_BASE ?= 0x80000000
256CFG_TEE_CORE_NB_CORE ?= 6
257$(call force,CFG_NXP_SNVS,n)
258$(call force,CFG_IMX_OCOTP,n)
259$(call force,CFG_TZC380,n)
260$(call force,CFG_NXP_CAAM,n)
261CFG_IMX_MU ?= y
262CFG_IMX_ELE ?= y
263else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx91-flavorlist)))
264$(call force,CFG_MX91,y)
265$(call force,CFG_ARM64_core,y)
266CFG_IMX_LPUART ?= y
267CFG_DRAM_BASE ?= 0x80000000
268CFG_TEE_CORE_NB_CORE ?= 1
269$(call force,CFG_NXP_SNVS,n)
270$(call force,CFG_IMX_OCOTP,n)
271$(call force,CFG_TZC380,n)
272$(call force,CFG_NXP_CAAM,n)
273CFG_IMX_MU ?= y
274CFG_IMX_ELE ?= y
275else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx943-flavorlist)))
276$(call force,CFG_MX943,y)
277$(call force,CFG_ARM64_core,y)
278CFG_IMX_LPUART ?= y
279CFG_DRAM_BASE ?= 0x80000000
280CFG_TEE_CORE_NB_CORE ?= 4
281$(call force,CFG_NXP_SNVS,n)
282$(call force,CFG_IMX_OCOTP,n)
283$(call force,CFG_TZC380,n)
284$(call force,CFG_NXP_CAAM,n)
285else
286$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
287endif
288
289ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
290CFG_DDR_SIZE ?= 0x40000000
291CFG_NS_ENTRY_ADDR ?= 0x80800000
292CFG_IMX_WDOG_EXT_RESET ?= y
293endif
294
295ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
296CFG_DDR_SIZE ?= 0x40000000
297CFG_UART_BASE ?= UART1_BASE
298CFG_IMX_WDOG_EXT_RESET ?= y
299endif
300
301ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
302CFG_DDR_SIZE ?= 0x20000000
303CFG_NS_ENTRY_ADDR ?= 0x87800000
304CFG_DT_ADDR ?= 0x83100000
305CFG_UART_BASE ?= UART5_BASE
306CFG_BOOT_SECONDARY_REQUEST ?= n
307CFG_EXTERNAL_DTB_OVERLAY ?= y
308CFG_IMX_WDOG_EXT_RESET ?= y
309endif
310
311ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
312CFG_DDR_SIZE ?= 0x20000000
313CFG_NS_ENTRY_ADDR ?= 0x80800000
314CFG_BOOT_SECONDARY_REQUEST ?= n
315endif
316
317ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
318CFG_DDR_SIZE ?= 0x20000000
319CFG_NS_ENTRY_ADDR ?= 0x87800000
320CFG_DT_ADDR ?= 0x83100000
321CFG_BOOT_SECONDARY_REQUEST ?= n
322CFG_EXTERNAL_DTB_OVERLAY = y
323CFG_IMX_WDOG_EXT_RESET = y
324endif
325
326ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
327CFG_DDR_SIZE ?= 0x40000000
328CFG_NS_ENTRY_ADDR ?= 0x60800000
329CFG_UART_BASE ?= UART4_BASE
330endif
331
332ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
333	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
334	mx6dapalis mx6qapalis))
335CFG_DDR_SIZE ?= 0x40000000
336CFG_NS_ENTRY_ADDR ?= 0x12000000
337endif
338
339ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
340	mx6dlsabreauto mx6solosabreauto))
341CFG_DDR_SIZE ?= 0x80000000
342CFG_NS_ENTRY_ADDR ?= 0x12000000
343CFG_UART_BASE ?= UART4_BASE
344endif
345
346ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
347CFG_DDR_SIZE ?= 0x80000000
348CFG_UART_BASE ?= UART1_BASE
349endif
350
351ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
352CFG_DDR_SIZE ?= 0x40000000
353CFG_NS_ENTRY_ADDR ?= 0x12000000
354endif
355
356ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
357CFG_DDR_SIZE ?= 0x40000000
358CFG_NS_ENTRY_ADDR ?= 0x12000000
359CFG_UART_BASE ?= UART2_BASE
360endif
361
362ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
363CFG_NS_ENTRY_ADDR ?= 0x80800000
364CFG_DDR_SIZE ?= 0x40000000
365endif
366
367ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
368CFG_NS_ENTRY_ADDR ?= 0x80800000
369CFG_DDR_SIZE ?= 0x80000000
370endif
371
372ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
373CFG_DDR_SIZE ?= 0x80000000
374CFG_NS_ENTRY_ADDR ?= 0x80800000
375endif
376
377ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
378CFG_DDR_SIZE ?= 0x40000000
379CFG_NS_ENTRY_ADDR ?= 0x80800000
380endif
381
382ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
383CFG_DDR_SIZE ?= 0x40000000
384CFG_UART_BASE ?= UART1_BASE
385endif
386
387ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
388CFG_DDR_SIZE ?= 0x20000000
389CFG_NS_ENTRY_ADDR ?= 0x80800000
390endif
391
392ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
393CFG_DDR_SIZE ?= 0x10000000
394CFG_NS_ENTRY_ADDR ?= 0x80800000
395CFG_UART_BASE ?= UART5_BASE
396endif
397
398ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
399CFG_DDR_SIZE ?= 0x10000000
400CFG_NS_ENTRY_ADDR ?= 0x80800000
401endif
402
403ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
404CFG_DDR_SIZE ?= 0x10000000
405CFG_UART_BASE ?= UART7_BASE
406endif
407
408ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
409CFG_DDR_SIZE ?= 0xc0000000
410CFG_UART_BASE ?= UART1_BASE
411endif
412
413ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
414CFG_DDR_SIZE ?= 0x80000000
415CFG_UART_BASE ?= UART2_BASE
416endif
417
418ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_cl_iot_gate))
419CFG_DDR_SIZE ?= 0x40000000
420CFG_UART_BASE ?= UART3_BASE
421CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
422CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
423endif
424
425ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phyboard_polis))
426CFG_DDR_SIZE ?= 0x40000000
427CFG_UART_BASE ?= UART3_BASE
428$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
429$(call force,CFG_CORE_ARM64_PA_BITS,36)
430endif
431
432ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phygate_tauri_l))
433CFG_DDR_SIZE ?= 0x80000000
434CFG_UART_BASE ?= UART3_BASE
435$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
436$(call force,CFG_CORE_ARM64_PA_BITS,36)
437endif
438
439ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
440CFG_DDR_SIZE ?= 0x80000000
441CFG_UART_BASE ?= UART2_BASE
442endif
443
444ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
445CFG_DDR_SIZE ?= UL(0x180000000)
446CFG_UART_BASE ?= UART2_BASE
447$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
448$(call force,CFG_CORE_ARM64_PA_BITS,36)
449endif
450
451ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_libra_fpsc))
452CFG_DDR_SIZE ?= 0x40000000
453CFG_UART_BASE ?= UART4_BASE
454$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
455$(call force,CFG_CORE_ARM64_PA_BITS,36)
456endif
457
458ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_phyboard_pollux))
459CFG_DDR_SIZE ?= 0x40000000
460CFG_UART_BASE ?= UART1_BASE
461$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
462$(call force,CFG_CORE_ARM64_PA_BITS,36)
463endif
464
465ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_rsb3720_6g))
466CFG_DDR_SIZE ?= UL(0x180000000)
467CFG_UART_BASE ?= UART3_BASE
468CFG_TZDRAM_START ?= 0x56000000
469$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
470$(call force,CFG_CORE_ARM64_PA_BITS,36)
471endif
472
473ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
474CFG_DDR_SIZE ?= 0x80000000
475CFG_UART_BASE ?= UART0_BASE
476CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
477CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
478CFG_CORE_ARM64_PA_BITS ?= 40
479endif
480
481ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxmek))
482CFG_DDR_SIZE ?= 0x40000000
483CFG_UART_BASE ?= UART0_BASE
484$(call force,CFG_MX8DX,y)
485endif
486
487ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxlevk))
488CFG_DDR_SIZE ?= 0x40000000
489CFG_UART_BASE ?= UART0_BASE
490CFG_NSEC_DDR_1_BASE ?= 0x800000000UL
491CFG_NSEC_DDR_1_SIZE ?= 0x400000000UL
492CFG_CORE_ARM64_PA_BITS ?= 40
493endif
494
495ifneq (,$(filter $(PLATFORM_FLAVOR),mx8ulpevk))
496CFG_DDR_SIZE ?= 0x80000000
497CFG_UART_BASE ?= UART5_BASE
498endif
499
500ifneq (,$(filter $(PLATFORM_FLAVOR),mx93evk mx91evk))
501CFG_DDR_SIZE ?= 0x80000000
502CFG_UART_BASE ?= UART1_BASE
503endif
504
505ifneq (,$(filter $(PLATFORM_FLAVOR),mx95evk mx943evk))
506CFG_DDR_SIZE ?= 0x80000000
507CFG_UART_BASE ?= UART1_BASE
508CFG_NSEC_DDR_1_BASE ?= 0x100000000UL
509CFG_NSEC_DDR_1_SIZE ?= 0x380000000UL
510CFG_CORE_ARM64_PA_BITS ?= 40
511endif
512
513# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
514ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
515	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
516include core/arch/arm/cpu/cortex-a9.mk
517
518$(call force,CFG_PL310,y)
519
520CFG_PL310_LOCKED ?= y
521CFG_ENABLE_SCTLR_RR ?= y
522CFG_IMX_SCU ?= y
523endif
524
525ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
526CFG_DRAM_BASE ?= 0x10000000
527endif
528
529ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
530	$(CFG_MX6SX)))
531CFG_DRAM_BASE ?= 0x80000000
532endif
533
534ifeq ($(filter y, $(CFG_MX7)), y)
535CFG_INIT_CNTVOFF ?= y
536CFG_DRAM_BASE ?= 0x80000000
537endif
538
539ifeq ($(filter y, $(CFG_MX7ULP)), y)
540CFG_INIT_CNTVOFF ?= y
541CFG_DRAM_BASE ?= UL(0x60000000)
542$(call force,CFG_IMX_LPUART,y)
543$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
544endif
545
546ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
547$(call force,CFG_GIC,y)
548
549CFG_BOOT_SECONDARY_REQUEST ?= y
550CFG_DT ?= y
551CFG_DTB_MAX_SIZE ?= 0x20000
552CFG_PAGEABLE_ADDR ?= 0
553CFG_PSCI_ARM32 ?= y
554CFG_SECURE_TIME_SOURCE_REE ?= y
555CFG_UART_BASE ?= UART1_BASE
556endif
557
558ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8M)))
559$(call force,CFG_IMX_UART,y)
560CFG_IMX_SNVS ?= y
561endif
562
563ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
564CFG_IMX_CSU ?= y
565endif
566
567ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
568CFG_HWSUPP_MEM_PERM_WXN = n
569CFG_IMX_WDOG ?= y
570endif
571
572ifeq ($(CFG_ARM64_core),y)
573# arm-v8 platforms
574include core/arch/arm/cpu/cortex-armv8-0.mk
575$(call force,CFG_ARM_GICV3,y)
576$(call force,CFG_GIC,y)
577$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
578$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
579
580CFG_CRYPTO_WITH_CE ?= y
581
582supported-ta-targets = ta_arm64
583endif
584
585CFG_TZDRAM_SIZE ?= 0x01e00000
586CFG_SHMEM_SIZE ?= 0x00200000
587CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - $(CFG_TZDRAM_SIZE) - $(CFG_SHMEM_SIZE) + $(CFG_DDR_SIZE))
588CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
589
590# Enable embedded tests by default
591CFG_ENABLE_EMBEDDED_TESTS ?= y
592CFG_ATTESTATION_PTA ?= y
593
594# Set default heap size for imx platforms to 128k
595CFG_CORE_HEAP_SIZE ?= 131072
596
597CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
598CFG_MMAP_REGIONS ?= 24
599
600# SE05X and OCOTP both implement tee_otp_get_die_id()
601ifeq ($(CFG_NXP_SE05X),y)
602$(call force,CFG_IMX_OCOTP,n)
603$(call force,CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID,n)
604endif
605CFG_IMX_OCOTP ?= y
606CFG_IMX_DIGPROG ?= y
607CFG_PKCS11_TA ?= y
608CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID ?= y
609
610# Almost all platforms include CAAM HW Modules, except the
611# ones forced to be disabled
612CFG_NXP_CAAM ?= n
613
614ifeq ($(CFG_NXP_CAAM),y)
615ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX) $(CFG_MX8DXL)), y)
616CFG_IMX_SC ?= y
617CFG_IMX_MU ?= y
618endif
619
620else
621
622ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
623CFG_IMX_CAAM ?= y
624endif
625
626endif
627