1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2021 NXP 4 */ 5 #include <arm.h> 6 #include <initcall.h> 7 #include <mm/core_memprot.h> 8 #include <mm/core_mmu.h> 9 #include <imx.h> 10 #include <io.h> 11 #include <drivers/imx_ocotp.h> 12 #include <kernel/delay.h> 13 #include <kernel/delay_arch.h> 14 #include <kernel/tee_common_otp.h> 15 #include <util.h> 16 17 #define OCOTP_CTRL 0x0 18 #define OCOTP_CTRL_SET 0x4 19 #define OCOTP_CTRL_CLR 0x8 20 #define OCOTP_TIMING 0x10 21 #define OCOTP_DATA 0x20 22 23 #define OCOTP_CTRL_WR_UNLOCK_KEY 0x3E77 24 25 #define OCOTP_TIMING_WAIT GENMASK_32(27, 22) 26 #define OCOTP_TIMING_STROBE_READ GENMASK_32(21, 16) 27 #define OCOTP_TIMING_RELAX GENMASK_32(15, 12) 28 #define OCOTP_TIMING_STROBE_PROG GENMASK_32(11, 0) 29 30 #define OCOTP_CTRL_WR_UNLOCK GENMASK_32(31, 16) 31 #if defined(CFG_MX8MP) 32 #define OCOTP_CTRL_RELOAD_SHADOWS BIT32(11) 33 #define OCOTP_CTRL_ERROR BIT32(10) 34 #define OCOTP_CTRL_BUSY BIT32(9) 35 #define OCOTP_CTRL_ADDR GENMASK_32(8, 0) 36 #else 37 #define OCOTP_CTRL_RELOAD_SHADOWS BIT32(10) 38 #define OCOTP_CTRL_ERROR BIT32(9) 39 #define OCOTP_CTRL_BUSY BIT32(8) 40 #define OCOTP_CTRL_ADDR GENMASK_32(7, 0) 41 #endif 42 43 #if defined(CFG_MX6) || defined(CFG_MX7ULP) 44 #define OCOTP_SHADOW_OFFSET(_b, _w) ((_b) * (0x80) + (_w) * (0x10) + 0x400) 45 #else 46 #define OCOTP_SHADOW_OFFSET(_b, _w) ((_b) * (0x40) + (_w) * (0x10) + 0x400) 47 #endif 48 49 /* Shadow reload needs more time if eFuses where written prior */ 50 #define OCOTP_OP_BUSY_TIMEOUT_US 1000 51 52 #define OCOTP_ADDR(_b, _w) (((_b) * (0x40) + (_w) * (0x10)) / 0x10) 53 54 #define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */ 55 #define TIMING_STROBE_READ_NS 37 /* Min time before read */ 56 #define TIMING_RELAX_NS 17 57 58 struct ocotp_instance { 59 unsigned char nb_banks; 60 unsigned char nb_words; 61 TEE_Result (*get_die_id)(uint64_t *ret_uid); 62 TEE_Result (*write_fuse)(unsigned int bank, unsigned int word, 63 uint32_t val); 64 }; 65 66 static vaddr_t g_base_addr; 67 static struct mutex fuse_read = MUTEX_INITIALIZER; 68 static const struct ocotp_instance *g_ocotp; 69 70 #if defined(CFG_MX6) 71 static void ocotp_clock_enable(void) 72 { 73 vaddr_t va = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, CCM_SIZE); 74 75 io_setbits32(va + CCM_CCGR2, BM_CCM_CCGR2_OCOTP_CTRL); 76 } 77 #elif defined(CFG_MX7) 78 static void ocotp_clock_enable(void) 79 { 80 vaddr_t va = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, CCM_SIZE); 81 82 io_setbits32(va + CCM_CCGRx_SET(CCM_CLOCK_DOMAIN_OCOTP), 83 CCM_CCGRx_ALWAYS_ON(0)); 84 } 85 #elif defined(CFG_MX8M) 86 static void ocotp_clock_enable(void) 87 { 88 vaddr_t va = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, CCM_SIZE); 89 90 io_setbits32(va + CCM_CCGRx_SET(CCM_CCRG_OCOTP), 91 CCM_CCGRx_ALWAYS_ON(0)); 92 } 93 #elif defined(CFG_MX7ULP) 94 /* The i.MX7ULP has the OCOTP always powered on */ 95 static inline void ocotp_clock_enable(void) { } 96 #else 97 #error "Platform not supported" 98 #endif 99 100 #if defined(CFG_CORE_HAS_GENERIC_TIMER) 101 static TEE_Result ocotp_ctrl_wait_for(uint32_t mask) 102 { 103 uint32_t val = 0; 104 105 assert(g_base_addr); 106 if (IO_READ32_POLL_TIMEOUT(g_base_addr + OCOTP_CTRL, val, 107 !(val & mask), 0, OCOTP_OP_BUSY_TIMEOUT_US)) 108 return TEE_ERROR_BUSY; 109 110 return TEE_SUCCESS; 111 } 112 #else 113 static TEE_Result ocotp_ctrl_wait_for(uint32_t mask) 114 { 115 uint32_t delay_us = OCOTP_OP_BUSY_TIMEOUT_US; 116 uint32_t reg = 0; 117 118 assert(g_base_addr); 119 for (; delay_us > 0; delay_us--) { 120 reg = io_read32(g_base_addr + OCOTP_CTRL) & mask; 121 if (!reg) 122 return TEE_SUCCESS; 123 udelay(1); 124 isb(); 125 } 126 127 return TEE_ERROR_BUSY; 128 } 129 #endif 130 131 TEE_Result imx_ocotp_read(unsigned int bank, unsigned int word, uint32_t *val) 132 { 133 TEE_Result ret = TEE_ERROR_GENERIC; 134 135 if (!val) 136 return TEE_ERROR_BAD_PARAMETERS; 137 138 assert(g_base_addr && g_ocotp); 139 140 if (bank > g_ocotp->nb_banks || word > g_ocotp->nb_words) 141 return TEE_ERROR_BAD_PARAMETERS; 142 143 mutex_lock(&fuse_read); 144 145 ocotp_clock_enable(); 146 147 /* Clear error bit */ 148 io_write32(g_base_addr + OCOTP_CTRL_CLR, OCOTP_CTRL_ERROR); 149 150 /* Wait for busy flag to be cleared */ 151 ret = ocotp_ctrl_wait_for(OCOTP_CTRL_BUSY); 152 if (ret) { 153 EMSG("OCOTP is busy"); 154 goto out; 155 } 156 157 /* Read shadow register */ 158 *val = io_read32(g_base_addr + OCOTP_SHADOW_OFFSET(bank, word)); 159 160 DMSG("OCOTP Bank %d Word %d Fuse 0x%" PRIx32, bank, word, *val); 161 out: 162 mutex_unlock(&fuse_read); 163 164 return ret; 165 } 166 167 TEE_Result imx_ocotp_write(unsigned int bank, unsigned int word, uint32_t val) 168 { 169 TEE_Result ret = TEE_ERROR_GENERIC; 170 171 if (!val) 172 return TEE_ERROR_BAD_PARAMETERS; 173 174 assert(g_base_addr && g_ocotp); 175 176 if (bank > g_ocotp->nb_banks || word > g_ocotp->nb_words) 177 return TEE_ERROR_BAD_PARAMETERS; 178 179 if (!g_ocotp->write_fuse) 180 return TEE_ERROR_NOT_IMPLEMENTED; 181 182 mutex_lock(&fuse_read); 183 184 ocotp_clock_enable(); 185 186 /* Clear error bit */ 187 io_write32(g_base_addr + OCOTP_CTRL_CLR, OCOTP_CTRL_ERROR); 188 189 /* Wait for busy flag to be cleared */ 190 ret = ocotp_ctrl_wait_for(OCOTP_CTRL_BUSY); 191 if (ret) { 192 EMSG("OCOTP is busy"); 193 goto out; 194 } 195 196 ret = g_ocotp->write_fuse(bank, word, val); 197 if (ret) { 198 EMSG("OCOTP write fuse failed"); 199 goto out; 200 } 201 202 io_write32(g_base_addr + OCOTP_CTRL_SET, OCOTP_CTRL_RELOAD_SHADOWS); 203 204 ret = ocotp_ctrl_wait_for(OCOTP_CTRL_BUSY); 205 if (ret) { 206 EMSG("OCOTP is busy"); 207 goto out; 208 } 209 210 DMSG("OCOTP Bank %d Word %d Fuse 0x%" PRIx32, bank, word, val); 211 out: 212 mutex_unlock(&fuse_read); 213 214 return ret; 215 } 216 217 static TEE_Result ocotp_mx8m_set_timing(void) 218 { 219 uint32_t strobe_read = 0; 220 uint32_t strobe_prog = 0; 221 uint32_t clk_rate = 0; 222 uint32_t timing = 0; 223 uint32_t relax = 0; 224 225 /* Assume the IPG_ROOT clock is running at 66.67 MHz */ 226 clk_rate = 66666667; 227 228 relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1; 229 230 strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS, 231 1000000000); 232 strobe_read += 2 * (relax + 1) - 1; 233 strobe_prog = UDIV_ROUND_NEAREST(clk_rate * TIMING_STROBE_PROG_US, 234 1000000); 235 strobe_prog += 2 * (relax + 1) - 1; 236 237 timing = io_read32(g_base_addr + OCOTP_TIMING) & OCOTP_TIMING_WAIT; 238 timing = set_field_u32(timing, OCOTP_TIMING_RELAX, relax); 239 timing = set_field_u32(timing, OCOTP_TIMING_STROBE_READ, strobe_read); 240 timing = set_field_u32(timing, OCOTP_TIMING_STROBE_PROG, strobe_prog); 241 242 io_write32(g_base_addr + OCOTP_TIMING, timing); 243 244 return ocotp_ctrl_wait_for(OCOTP_CTRL_BUSY); 245 } 246 247 static TEE_Result ocotp_mx8m_write_fuse(unsigned int bank, unsigned int word, 248 uint32_t val) 249 { 250 TEE_Result ret = TEE_ERROR_GENERIC; 251 uint32_t reg = 0; 252 253 ret = ocotp_mx8m_set_timing(); 254 if (ret) { 255 EMSG("OCOTP set_timing failed"); 256 return ret; 257 } 258 259 /* Control register */ 260 reg = io_read32(g_base_addr + OCOTP_CTRL); 261 reg &= ~OCOTP_CTRL_ADDR; 262 reg = set_field_u32(reg, OCOTP_CTRL_ADDR, OCOTP_ADDR(bank, word)); 263 reg = set_field_u32(reg, OCOTP_CTRL_WR_UNLOCK, 264 OCOTP_CTRL_WR_UNLOCK_KEY); 265 io_write32(g_base_addr + OCOTP_CTRL, reg); 266 267 /* Clear error bit */ 268 io_write32(g_base_addr + OCOTP_CTRL_CLR, OCOTP_CTRL_ERROR); 269 270 io_write32(g_base_addr + OCOTP_DATA, val); 271 ret = ocotp_ctrl_wait_for(OCOTP_CTRL_BUSY); 272 if (ret) { 273 EMSG("OCOTP write fuse-val failed"); 274 return ret; 275 } 276 277 /* 278 * Write postamble (TRM): 279 * Due to internal electrical characteristics of the OTP during writes, 280 * all OTP operations following a write must be separated by 2 us after 281 * the clearing of HW_OCOTP_CTRL_BUSY following the write. This 282 * guarantees programming voltages on-chip to reach a steady state when 283 * exiting a write sequence. This includes reads, shadow reloads, or 284 * other writes. 285 */ 286 udelay(2); 287 288 if (io_read32(g_base_addr + OCOTP_CTRL) & OCOTP_CTRL_ERROR) { 289 EMSG("OCOTP bad write status"); 290 return TEE_ERROR_GENERIC; 291 } 292 293 return TEE_SUCCESS; 294 } 295 296 static TEE_Result ocotp_get_die_id_mx7ulp(uint64_t *ret_uid) 297 { 298 TEE_Result res = TEE_ERROR_GENERIC; 299 uint32_t val = 0; 300 uint64_t uid = 0; 301 302 res = imx_ocotp_read(1, 6, &val); 303 if (res) 304 goto out; 305 uid = val & GENMASK_32(15, 0); 306 307 res = imx_ocotp_read(1, 5, &val); 308 if (res) 309 goto out; 310 uid = SHIFT_U64(uid, 16) | (val & GENMASK_32(15, 0)); 311 312 res = imx_ocotp_read(1, 4, &val); 313 if (res) 314 goto out; 315 uid = SHIFT_U64(uid, 16) | (val & GENMASK_32(15, 0)); 316 317 res = imx_ocotp_read(1, 3, &val); 318 if (res) 319 goto out; 320 uid = SHIFT_U64(uid, 16) | (val & GENMASK_32(15, 0)); 321 322 out: 323 if (res == TEE_SUCCESS) 324 *ret_uid = uid; 325 326 return res; 327 } 328 329 static TEE_Result ocotp_get_die_id_mx(uint64_t *ret_uid) 330 { 331 TEE_Result res = TEE_ERROR_GENERIC; 332 uint32_t val = 0; 333 uint64_t uid = 0; 334 335 res = imx_ocotp_read(0, 2, &val); 336 if (res) 337 goto out; 338 uid = val; 339 340 res = imx_ocotp_read(0, 1, &val); 341 if (res) 342 goto out; 343 uid = SHIFT_U64(uid, 32) | val; 344 345 out: 346 if (res == TEE_SUCCESS) 347 *ret_uid = uid; 348 349 return res; 350 } 351 352 static const struct ocotp_instance ocotp_imx6q = { 353 .nb_banks = 16, 354 .nb_words = 8, 355 .get_die_id = ocotp_get_die_id_mx, 356 }; 357 358 static const struct ocotp_instance ocotp_imx6sl = { 359 .nb_banks = 8, 360 .nb_words = 8, 361 .get_die_id = ocotp_get_die_id_mx, 362 }; 363 364 static const struct ocotp_instance ocotp_imx6sll = { 365 .nb_banks = 16, 366 .nb_words = 8, 367 .get_die_id = ocotp_get_die_id_mx, 368 }; 369 370 static const struct ocotp_instance ocotp_imx6sx = { 371 .nb_banks = 16, 372 .nb_words = 8, 373 .get_die_id = ocotp_get_die_id_mx, 374 }; 375 376 static const struct ocotp_instance ocotp_imx6ul = { 377 .nb_banks = 16, 378 .nb_words = 8, 379 .get_die_id = ocotp_get_die_id_mx, 380 }; 381 382 static const struct ocotp_instance ocotp_imx6ull = { 383 .nb_banks = 8, 384 .nb_words = 8, 385 .get_die_id = ocotp_get_die_id_mx, 386 }; 387 388 static const struct ocotp_instance ocotp_imx7d = { 389 .nb_banks = 8, 390 .nb_words = 8, 391 .get_die_id = ocotp_get_die_id_mx, 392 }; 393 394 static const struct ocotp_instance ocotp_imx7ulp = { 395 .nb_banks = 32, 396 .nb_words = 8, 397 .get_die_id = ocotp_get_die_id_mx7ulp, 398 }; 399 400 static const struct ocotp_instance ocotp_imx8m = { 401 .nb_banks = 32, 402 .nb_words = 8, 403 .get_die_id = ocotp_get_die_id_mx, 404 .write_fuse = ocotp_mx8m_write_fuse, 405 }; 406 407 static const struct ocotp_instance ocotp_imx8mp = { 408 .nb_banks = 48, 409 .nb_words = 8, 410 .get_die_id = ocotp_get_die_id_mx, 411 .write_fuse = ocotp_mx8m_write_fuse, 412 }; 413 414 int tee_otp_get_die_id(uint8_t *buffer, size_t len) 415 { 416 size_t max_size_uid = IMX_UID_SIZE; 417 uint64_t uid = 0; 418 419 assert(buffer); 420 assert(g_base_addr && g_ocotp); 421 422 if (g_ocotp->get_die_id(&uid)) 423 goto err; 424 425 memcpy(buffer, &uid, MIN(max_size_uid, len)); 426 return 0; 427 428 err: 429 EMSG("Error while getting die ID"); 430 return -1; 431 } 432 433 register_phys_mem_pgdir(MEM_AREA_IO_SEC, OCOTP_BASE, CORE_MMU_PGDIR_SIZE); 434 static TEE_Result imx_ocotp_init(void) 435 { 436 g_base_addr = core_mmu_get_va(OCOTP_BASE, MEM_AREA_IO_SEC, OCOTP_SIZE); 437 if (!g_base_addr) 438 return TEE_ERROR_GENERIC; 439 440 if (soc_is_imx6sdl() || soc_is_imx6dq() || soc_is_imx6dqp()) { 441 g_ocotp = &ocotp_imx6q; 442 } else if (soc_is_imx6sl()) { 443 g_ocotp = &ocotp_imx6sl; 444 } else if (soc_is_imx6sll()) { 445 g_ocotp = &ocotp_imx6sll; 446 } else if (soc_is_imx6sx()) { 447 g_ocotp = &ocotp_imx6sx; 448 } else if (soc_is_imx6ul()) { 449 g_ocotp = &ocotp_imx6ul; 450 } else if (soc_is_imx6ull()) { 451 g_ocotp = &ocotp_imx6ull; 452 } else if (soc_is_imx7ds()) { 453 g_ocotp = &ocotp_imx7d; 454 } else if (soc_is_imx7ulp()) { 455 g_ocotp = &ocotp_imx7ulp; 456 } else if (soc_is_imx8mm() || soc_is_imx8mn() || soc_is_imx8mq()) { 457 g_ocotp = &ocotp_imx8m; 458 } else if (soc_is_imx8mp()) { 459 g_ocotp = &ocotp_imx8mp; 460 } else { 461 g_ocotp = NULL; 462 return TEE_ERROR_NOT_SUPPORTED; 463 } 464 465 return TEE_SUCCESS; 466 } 467 service_init(imx_ocotp_init); 468