1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2021 NXP 4 */ 5 #include <arm.h> 6 #include <initcall.h> 7 #include <mm/core_memprot.h> 8 #include <mm/core_mmu.h> 9 #include <imx.h> 10 #include <io.h> 11 #include <drivers/imx_ocotp.h> 12 #include <kernel/delay_arch.h> 13 #include <kernel/tee_common_otp.h> 14 15 #define OCOTP_CTRL 0x0 16 #define OCOTP_CTRL_CLR 0x8 17 18 #if defined(CFG_MX8MP) 19 #define OCOTP_CTRL_ERROR BIT32(10) 20 #define OCOTP_CTRL_BUSY BIT32(9) 21 #else 22 #define OCOTP_CTRL_ERROR BIT32(9) 23 #define OCOTP_CTRL_BUSY BIT32(8) 24 #endif 25 26 #if defined(CFG_MX6) || defined(CFG_MX7ULP) 27 #define OCOTP_SHADOW_OFFSET(_b, _w) ((_b) * (0x80) + (_w) * (0x10) + 0x400) 28 #else 29 #define OCOTP_SHADOW_OFFSET(_b, _w) ((_b) * (0x40) + (_w) * (0x10) + 0x400) 30 #endif 31 32 #define OCOTP_OP_BUSY_TIMEOUT_US 20 33 34 struct ocotp_instance { 35 unsigned char nb_banks; 36 unsigned char nb_words; 37 TEE_Result (*get_die_id)(uint64_t *ret_uid); 38 }; 39 40 static vaddr_t g_base_addr; 41 static struct mutex fuse_read = MUTEX_INITIALIZER; 42 static const struct ocotp_instance *g_ocotp; 43 44 #if defined(CFG_MX6) 45 static void ocotp_clock_enable(void) 46 { 47 vaddr_t va = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, CCM_SIZE); 48 49 io_setbits32(va + CCM_CCGR2, BM_CCM_CCGR2_OCOTP_CTRL); 50 } 51 #elif defined(CFG_MX7) 52 static void ocotp_clock_enable(void) 53 { 54 vaddr_t va = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, CCM_SIZE); 55 56 io_setbits32(va + CCM_CCGRx_SET(CCM_CLOCK_DOMAIN_OCOTP), 57 CCM_CCGRx_ALWAYS_ON(0)); 58 } 59 #elif defined(CFG_MX8M) 60 static void ocotp_clock_enable(void) 61 { 62 vaddr_t va = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, CCM_SIZE); 63 64 io_setbits32(va + CCM_CCGRx_SET(CCM_CCRG_OCOTP), 65 CCM_CCGRx_ALWAYS_ON(0)); 66 } 67 #elif defined(CFG_MX7ULP) 68 /* The i.MX7ULP has the OCOTP always powered on */ 69 static inline void ocotp_clock_enable(void) { } 70 #else 71 #error "Platform not supported" 72 #endif 73 74 #if defined(CFG_CORE_HAS_GENERIC_TIMER) 75 static TEE_Result ocotp_ctrl_wait_for(uint32_t mask) 76 { 77 uint32_t val = 0; 78 79 assert(g_base_addr); 80 if (IO_READ32_POLL_TIMEOUT(g_base_addr + OCOTP_CTRL, val, 81 !(val & mask), 0, OCOTP_OP_BUSY_TIMEOUT_US)) 82 return TEE_ERROR_BUSY; 83 84 return TEE_SUCCESS; 85 } 86 #else 87 static TEE_Result ocotp_ctrl_wait_for(uint32_t mask) 88 { 89 uint32_t delay_us = OCOTP_OP_BUSY_TIMEOUT_US; 90 uint32_t reg = 0; 91 92 assert(g_base_addr); 93 for (; delay_us > 0; delay_us--) { 94 reg = io_read32(g_base_addr + OCOTP_CTRL) & mask; 95 if (!reg) 96 return TEE_SUCCESS; 97 udelay(1); 98 isb(); 99 } 100 101 return TEE_ERROR_BUSY; 102 } 103 #endif 104 105 TEE_Result imx_ocotp_read(unsigned int bank, unsigned int word, uint32_t *val) 106 { 107 TEE_Result ret = TEE_ERROR_GENERIC; 108 109 if (!val) 110 return TEE_ERROR_BAD_PARAMETERS; 111 112 assert(g_base_addr && g_ocotp); 113 114 if (bank > g_ocotp->nb_banks || word > g_ocotp->nb_words) 115 return TEE_ERROR_BAD_PARAMETERS; 116 117 mutex_lock(&fuse_read); 118 119 ocotp_clock_enable(); 120 121 /* Clear error bit */ 122 io_write32(g_base_addr + OCOTP_CTRL_CLR, OCOTP_CTRL_ERROR); 123 124 /* Wait for busy flag to be cleared */ 125 ret = ocotp_ctrl_wait_for(OCOTP_CTRL_BUSY); 126 if (ret) { 127 EMSG("OCOTP is busy"); 128 goto out; 129 } 130 131 /* Read shadow register */ 132 *val = io_read32(g_base_addr + OCOTP_SHADOW_OFFSET(bank, word)); 133 134 DMSG("OCOTP Bank %d Word %d Fuse 0x%" PRIx32, bank, word, *val); 135 out: 136 mutex_unlock(&fuse_read); 137 138 return ret; 139 } 140 141 static TEE_Result ocotp_get_die_id_mx7ulp(uint64_t *ret_uid) 142 { 143 TEE_Result res = TEE_ERROR_GENERIC; 144 uint32_t val = 0; 145 uint64_t uid = 0; 146 147 res = imx_ocotp_read(1, 6, &val); 148 if (res) 149 goto out; 150 uid = val & GENMASK_32(15, 0); 151 152 res = imx_ocotp_read(1, 5, &val); 153 if (res) 154 goto out; 155 uid = SHIFT_U64(uid, 16) | (val & GENMASK_32(15, 0)); 156 157 res = imx_ocotp_read(1, 4, &val); 158 if (res) 159 goto out; 160 uid = SHIFT_U64(uid, 16) | (val & GENMASK_32(15, 0)); 161 162 res = imx_ocotp_read(1, 3, &val); 163 if (res) 164 goto out; 165 uid = SHIFT_U64(uid, 16) | (val & GENMASK_32(15, 0)); 166 167 out: 168 if (res == TEE_SUCCESS) 169 *ret_uid = uid; 170 171 return res; 172 } 173 174 static TEE_Result ocotp_get_die_id_mx(uint64_t *ret_uid) 175 { 176 TEE_Result res = TEE_ERROR_GENERIC; 177 uint32_t val = 0; 178 uint64_t uid = 0; 179 180 res = imx_ocotp_read(0, 2, &val); 181 if (res) 182 goto out; 183 uid = val; 184 185 res = imx_ocotp_read(0, 1, &val); 186 if (res) 187 goto out; 188 uid = SHIFT_U64(uid, 32) | val; 189 190 out: 191 if (res == TEE_SUCCESS) 192 *ret_uid = uid; 193 194 return res; 195 } 196 197 static const struct ocotp_instance ocotp_imx6q = { 198 .nb_banks = 16, 199 .nb_words = 8, 200 .get_die_id = ocotp_get_die_id_mx, 201 }; 202 203 static const struct ocotp_instance ocotp_imx6sl = { 204 .nb_banks = 8, 205 .nb_words = 8, 206 .get_die_id = ocotp_get_die_id_mx, 207 }; 208 209 static const struct ocotp_instance ocotp_imx6sll = { 210 .nb_banks = 16, 211 .nb_words = 8, 212 .get_die_id = ocotp_get_die_id_mx, 213 }; 214 215 static const struct ocotp_instance ocotp_imx6sx = { 216 .nb_banks = 16, 217 .nb_words = 8, 218 .get_die_id = ocotp_get_die_id_mx, 219 }; 220 221 static const struct ocotp_instance ocotp_imx6ul = { 222 .nb_banks = 16, 223 .nb_words = 8, 224 .get_die_id = ocotp_get_die_id_mx, 225 }; 226 227 static const struct ocotp_instance ocotp_imx6ull = { 228 .nb_banks = 8, 229 .nb_words = 8, 230 .get_die_id = ocotp_get_die_id_mx, 231 }; 232 233 static const struct ocotp_instance ocotp_imx7d = { 234 .nb_banks = 8, 235 .nb_words = 8, 236 .get_die_id = ocotp_get_die_id_mx, 237 }; 238 239 static const struct ocotp_instance ocotp_imx7ulp = { 240 .nb_banks = 32, 241 .nb_words = 8, 242 .get_die_id = ocotp_get_die_id_mx7ulp, 243 }; 244 245 static const struct ocotp_instance ocotp_imx8m = { 246 .nb_banks = 32, 247 .nb_words = 8, 248 .get_die_id = ocotp_get_die_id_mx, 249 }; 250 251 static const struct ocotp_instance ocotp_imx8mp = { 252 .nb_banks = 48, 253 .nb_words = 8, 254 .get_die_id = ocotp_get_die_id_mx, 255 }; 256 257 int tee_otp_get_die_id(uint8_t *buffer, size_t len) 258 { 259 size_t max_size_uid = IMX_UID_SIZE; 260 uint64_t uid = 0; 261 262 assert(buffer); 263 assert(g_base_addr && g_ocotp); 264 265 if (g_ocotp->get_die_id(&uid)) 266 goto err; 267 268 memcpy(buffer, &uid, MIN(max_size_uid, len)); 269 return 0; 270 271 err: 272 EMSG("Error while getting die ID"); 273 return -1; 274 } 275 276 register_phys_mem_pgdir(MEM_AREA_IO_SEC, OCOTP_BASE, CORE_MMU_PGDIR_SIZE); 277 static TEE_Result imx_ocotp_init(void) 278 { 279 g_base_addr = core_mmu_get_va(OCOTP_BASE, MEM_AREA_IO_SEC, OCOTP_SIZE); 280 if (!g_base_addr) 281 return TEE_ERROR_GENERIC; 282 283 if (soc_is_imx6sdl() || soc_is_imx6dq() || soc_is_imx6dqp()) { 284 g_ocotp = &ocotp_imx6q; 285 } else if (soc_is_imx6sl()) { 286 g_ocotp = &ocotp_imx6sl; 287 } else if (soc_is_imx6sll()) { 288 g_ocotp = &ocotp_imx6sll; 289 } else if (soc_is_imx6sx()) { 290 g_ocotp = &ocotp_imx6sx; 291 } else if (soc_is_imx6ul()) { 292 g_ocotp = &ocotp_imx6ul; 293 } else if (soc_is_imx6ull()) { 294 g_ocotp = &ocotp_imx6ull; 295 } else if (soc_is_imx7ds()) { 296 g_ocotp = &ocotp_imx7d; 297 } else if (soc_is_imx7ulp()) { 298 g_ocotp = &ocotp_imx7ulp; 299 } else if (soc_is_imx8mm() || soc_is_imx8mn() || soc_is_imx8mq()) { 300 g_ocotp = &ocotp_imx8m; 301 } else if (soc_is_imx8mp()) { 302 g_ocotp = &ocotp_imx8mp; 303 } else { 304 g_ocotp = NULL; 305 return TEE_ERROR_NOT_SUPPORTED; 306 } 307 308 return TEE_SUCCESS; 309 } 310 service_init(imx_ocotp_init); 311