1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2021 NXP 4 */ 5 #include <arm.h> 6 #include <initcall.h> 7 #include <mm/core_memprot.h> 8 #include <mm/core_mmu.h> 9 #include <imx.h> 10 #include <io.h> 11 #include <drivers/imx_ocotp.h> 12 #include <kernel/delay.h> 13 #include <kernel/delay_arch.h> 14 #include <kernel/tee_common_otp.h> 15 #include <util.h> 16 17 #define OCOTP_CTRL 0x0 18 #define OCOTP_CTRL_SET 0x4 19 #define OCOTP_CTRL_CLR 0x8 20 #define OCOTP_TIMING 0x10 21 #define OCOTP_DATA 0x20 22 23 #define OCOTP_CTRL_WR_UNLOCK_KEY 0x3E77 24 25 #define OCOTP_TIMING_WAIT GENMASK_32(27, 22) 26 #define OCOTP_TIMING_STROBE_READ GENMASK_32(21, 16) 27 #define OCOTP_TIMING_RELAX GENMASK_32(15, 12) 28 #define OCOTP_TIMING_STROBE_PROG GENMASK_32(11, 0) 29 30 #define OCOTP_CTRL_WR_UNLOCK GENMASK_32(31, 16) 31 #if defined(CFG_MX8MP) 32 #define OCOTP_CTRL_RELOAD_SHADOWS BIT32(11) 33 #define OCOTP_CTRL_ERROR BIT32(10) 34 #define OCOTP_CTRL_BUSY BIT32(9) 35 #define OCOTP_CTRL_ADDR GENMASK_32(8, 0) 36 #else 37 #define OCOTP_CTRL_RELOAD_SHADOWS BIT32(10) 38 #define OCOTP_CTRL_ERROR BIT32(9) 39 #define OCOTP_CTRL_BUSY BIT32(8) 40 #define OCOTP_CTRL_ADDR GENMASK_32(7, 0) 41 #endif 42 43 #if defined(CFG_MX6) || defined(CFG_MX7ULP) 44 #define OCOTP_SHADOW_OFFSET(_b, _w) ((_b) * (0x80) + (_w) * (0x10) + 0x400) 45 #else 46 #define OCOTP_SHADOW_OFFSET(_b, _w) ((_b) * (0x40) + (_w) * (0x10) + 0x400) 47 #endif 48 49 /* Shadow reload needs more time if eFuses where written prior */ 50 #define OCOTP_OP_BUSY_TIMEOUT_US 1000 51 52 #if defined(CFG_MX6) || defined(CFG_MX7ULP) 53 #define OCOTP_ADDR(_b, _w) (((_b) * (0x80) + (_w) * (0x10)) / 0x10) 54 #else 55 #define OCOTP_ADDR(_b, _w) (((_b) * (0x40) + (_w) * (0x10)) / 0x10) 56 #endif 57 58 #define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */ 59 #define TIMING_STROBE_READ_NS 37 /* Min time before read */ 60 #define TIMING_RELAX_NS 17 61 62 struct ocotp_instance { 63 unsigned char nb_banks; 64 unsigned char nb_words; 65 TEE_Result (*get_die_id)(uint64_t *ret_uid); 66 TEE_Result (*write_fuse)(unsigned int bank, unsigned int word, 67 uint32_t val); 68 }; 69 70 static vaddr_t g_base_addr; 71 static struct mutex fuse_read = MUTEX_INITIALIZER; 72 static const struct ocotp_instance *g_ocotp; 73 74 #if defined(CFG_MX6) 75 static void ocotp_clock_enable(void) 76 { 77 vaddr_t va = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, CCM_SIZE); 78 79 io_setbits32(va + CCM_CCGR2, BM_CCM_CCGR2_OCOTP_CTRL); 80 } 81 #elif defined(CFG_MX7) 82 static void ocotp_clock_enable(void) 83 { 84 vaddr_t va = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, CCM_SIZE); 85 86 io_setbits32(va + CCM_CCGRx_SET(CCM_CLOCK_DOMAIN_OCOTP), 87 CCM_CCGRx_ALWAYS_ON(0)); 88 } 89 #elif defined(CFG_MX8M) 90 static void ocotp_clock_enable(void) 91 { 92 vaddr_t va = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, CCM_SIZE); 93 94 io_setbits32(va + CCM_CCGRx_SET(CCM_CCRG_OCOTP), 95 CCM_CCGRx_ALWAYS_ON(0)); 96 } 97 #elif defined(CFG_MX7ULP) 98 /* The i.MX7ULP has the OCOTP always powered on */ 99 static inline void ocotp_clock_enable(void) { } 100 #else 101 #error "Platform not supported" 102 #endif 103 104 #if defined(CFG_CORE_HAS_GENERIC_TIMER) 105 static TEE_Result ocotp_ctrl_wait_for(uint32_t mask) 106 { 107 uint32_t val = 0; 108 109 assert(g_base_addr); 110 if (IO_READ32_POLL_TIMEOUT(g_base_addr + OCOTP_CTRL, val, 111 !(val & mask), 0, OCOTP_OP_BUSY_TIMEOUT_US)) 112 return TEE_ERROR_BUSY; 113 114 return TEE_SUCCESS; 115 } 116 #else 117 static TEE_Result ocotp_ctrl_wait_for(uint32_t mask) 118 { 119 uint32_t delay_us = OCOTP_OP_BUSY_TIMEOUT_US; 120 uint32_t reg = 0; 121 122 assert(g_base_addr); 123 for (; delay_us > 0; delay_us--) { 124 reg = io_read32(g_base_addr + OCOTP_CTRL) & mask; 125 if (!reg) 126 return TEE_SUCCESS; 127 udelay(1); 128 isb(); 129 } 130 131 return TEE_ERROR_BUSY; 132 } 133 #endif 134 135 TEE_Result imx_ocotp_read(unsigned int bank, unsigned int word, uint32_t *val) 136 { 137 TEE_Result ret = TEE_ERROR_GENERIC; 138 139 if (!val) 140 return TEE_ERROR_BAD_PARAMETERS; 141 142 assert(g_base_addr && g_ocotp); 143 144 if (bank > g_ocotp->nb_banks || word > g_ocotp->nb_words) 145 return TEE_ERROR_BAD_PARAMETERS; 146 147 mutex_lock(&fuse_read); 148 149 ocotp_clock_enable(); 150 151 /* Clear error bit */ 152 io_write32(g_base_addr + OCOTP_CTRL_CLR, OCOTP_CTRL_ERROR); 153 154 /* Wait for busy flag to be cleared */ 155 ret = ocotp_ctrl_wait_for(OCOTP_CTRL_BUSY); 156 if (ret) { 157 EMSG("OCOTP is busy"); 158 goto out; 159 } 160 161 /* Read shadow register */ 162 *val = io_read32(g_base_addr + OCOTP_SHADOW_OFFSET(bank, word)); 163 164 DMSG("OCOTP Bank %d Word %d Fuse 0x%" PRIx32, bank, word, *val); 165 out: 166 mutex_unlock(&fuse_read); 167 168 return ret; 169 } 170 171 TEE_Result imx_ocotp_write(unsigned int bank, unsigned int word, uint32_t val) 172 { 173 TEE_Result ret = TEE_ERROR_GENERIC; 174 175 if (!val) 176 return TEE_ERROR_BAD_PARAMETERS; 177 178 assert(g_base_addr && g_ocotp); 179 180 if (bank > g_ocotp->nb_banks || word > g_ocotp->nb_words) 181 return TEE_ERROR_BAD_PARAMETERS; 182 183 if (!g_ocotp->write_fuse) 184 return TEE_ERROR_NOT_IMPLEMENTED; 185 186 mutex_lock(&fuse_read); 187 188 ocotp_clock_enable(); 189 190 /* Clear error bit */ 191 io_write32(g_base_addr + OCOTP_CTRL_CLR, OCOTP_CTRL_ERROR); 192 193 /* Wait for busy flag to be cleared */ 194 ret = ocotp_ctrl_wait_for(OCOTP_CTRL_BUSY); 195 if (ret) { 196 EMSG("OCOTP is busy"); 197 goto out; 198 } 199 200 ret = g_ocotp->write_fuse(bank, word, val); 201 if (ret) { 202 EMSG("OCOTP write fuse failed"); 203 goto out; 204 } 205 206 io_write32(g_base_addr + OCOTP_CTRL_SET, OCOTP_CTRL_RELOAD_SHADOWS); 207 208 ret = ocotp_ctrl_wait_for(OCOTP_CTRL_BUSY); 209 if (ret) { 210 EMSG("OCOTP is busy"); 211 goto out; 212 } 213 214 DMSG("OCOTP Bank %d Word %d Fuse 0x%" PRIx32, bank, word, val); 215 out: 216 mutex_unlock(&fuse_read); 217 218 return ret; 219 } 220 221 static TEE_Result ocotp_set_timing(void) 222 { 223 uint32_t strobe_read = 0; 224 uint32_t strobe_prog = 0; 225 uint32_t clk_rate = 0; 226 uint32_t timing = 0; 227 uint32_t relax = 0; 228 229 /* Assume the IPG_ROOT clock is running at 66.67 MHz */ 230 clk_rate = 66666667; 231 232 relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1; 233 234 strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS, 235 1000000000); 236 strobe_read += 2 * (relax + 1) - 1; 237 strobe_prog = UDIV_ROUND_NEAREST(clk_rate * TIMING_STROBE_PROG_US, 238 1000000); 239 strobe_prog += 2 * (relax + 1) - 1; 240 241 timing = io_read32(g_base_addr + OCOTP_TIMING) & OCOTP_TIMING_WAIT; 242 timing = set_field_u32(timing, OCOTP_TIMING_RELAX, relax); 243 timing = set_field_u32(timing, OCOTP_TIMING_STROBE_READ, strobe_read); 244 timing = set_field_u32(timing, OCOTP_TIMING_STROBE_PROG, strobe_prog); 245 246 io_write32(g_base_addr + OCOTP_TIMING, timing); 247 248 return ocotp_ctrl_wait_for(OCOTP_CTRL_BUSY); 249 } 250 251 static TEE_Result ocotp_write_fuse(unsigned int bank, unsigned int word, 252 uint32_t val) 253 { 254 TEE_Result ret = TEE_ERROR_GENERIC; 255 uint32_t reg = 0; 256 257 ret = ocotp_set_timing(); 258 if (ret) { 259 EMSG("OCOTP set_timing failed"); 260 return ret; 261 } 262 263 /* Control register */ 264 reg = io_read32(g_base_addr + OCOTP_CTRL); 265 reg &= ~OCOTP_CTRL_ADDR; 266 reg = set_field_u32(reg, OCOTP_CTRL_ADDR, OCOTP_ADDR(bank, word)); 267 reg = set_field_u32(reg, OCOTP_CTRL_WR_UNLOCK, 268 OCOTP_CTRL_WR_UNLOCK_KEY); 269 io_write32(g_base_addr + OCOTP_CTRL, reg); 270 271 /* Clear error bit */ 272 io_write32(g_base_addr + OCOTP_CTRL_CLR, OCOTP_CTRL_ERROR); 273 274 io_write32(g_base_addr + OCOTP_DATA, val); 275 ret = ocotp_ctrl_wait_for(OCOTP_CTRL_BUSY); 276 if (ret) { 277 EMSG("OCOTP write fuse-val failed"); 278 return ret; 279 } 280 281 /* 282 * Write postamble (TRM): 283 * Due to internal electrical characteristics of the OTP during writes, 284 * all OTP operations following a write must be separated by 2 us after 285 * the clearing of HW_OCOTP_CTRL_BUSY following the write. This 286 * guarantees programming voltages on-chip to reach a steady state when 287 * exiting a write sequence. This includes reads, shadow reloads, or 288 * other writes. 289 */ 290 udelay(2); 291 292 if (io_read32(g_base_addr + OCOTP_CTRL) & OCOTP_CTRL_ERROR) { 293 EMSG("OCOTP bad write status"); 294 return TEE_ERROR_GENERIC; 295 } 296 297 return TEE_SUCCESS; 298 } 299 300 static TEE_Result ocotp_get_die_id_mx7ulp(uint64_t *ret_uid) 301 { 302 TEE_Result res = TEE_ERROR_GENERIC; 303 uint32_t val = 0; 304 uint64_t uid = 0; 305 306 res = imx_ocotp_read(1, 6, &val); 307 if (res) 308 goto out; 309 uid = val & GENMASK_32(15, 0); 310 311 res = imx_ocotp_read(1, 5, &val); 312 if (res) 313 goto out; 314 uid = SHIFT_U64(uid, 16) | (val & GENMASK_32(15, 0)); 315 316 res = imx_ocotp_read(1, 4, &val); 317 if (res) 318 goto out; 319 uid = SHIFT_U64(uid, 16) | (val & GENMASK_32(15, 0)); 320 321 res = imx_ocotp_read(1, 3, &val); 322 if (res) 323 goto out; 324 uid = SHIFT_U64(uid, 16) | (val & GENMASK_32(15, 0)); 325 326 out: 327 if (res == TEE_SUCCESS) 328 *ret_uid = uid; 329 330 return res; 331 } 332 333 static TEE_Result ocotp_get_die_id_mx(uint64_t *ret_uid) 334 { 335 TEE_Result res = TEE_ERROR_GENERIC; 336 uint32_t val = 0; 337 uint64_t uid = 0; 338 339 res = imx_ocotp_read(0, 2, &val); 340 if (res) 341 goto out; 342 uid = val; 343 344 res = imx_ocotp_read(0, 1, &val); 345 if (res) 346 goto out; 347 uid = SHIFT_U64(uid, 32) | val; 348 349 out: 350 if (res == TEE_SUCCESS) 351 *ret_uid = uid; 352 353 return res; 354 } 355 356 static const struct ocotp_instance ocotp_imx6q = { 357 .nb_banks = 16, 358 .nb_words = 8, 359 .get_die_id = ocotp_get_die_id_mx, 360 .write_fuse = ocotp_write_fuse, 361 }; 362 363 static const struct ocotp_instance ocotp_imx6sl = { 364 .nb_banks = 8, 365 .nb_words = 8, 366 .get_die_id = ocotp_get_die_id_mx, 367 }; 368 369 static const struct ocotp_instance ocotp_imx6sll = { 370 .nb_banks = 16, 371 .nb_words = 8, 372 .get_die_id = ocotp_get_die_id_mx, 373 }; 374 375 static const struct ocotp_instance ocotp_imx6sx = { 376 .nb_banks = 16, 377 .nb_words = 8, 378 .get_die_id = ocotp_get_die_id_mx, 379 }; 380 381 static const struct ocotp_instance ocotp_imx6ul = { 382 .nb_banks = 16, 383 .nb_words = 8, 384 .get_die_id = ocotp_get_die_id_mx, 385 .write_fuse = ocotp_write_fuse, 386 }; 387 388 static const struct ocotp_instance ocotp_imx6ull = { 389 .nb_banks = 8, 390 .nb_words = 8, 391 .get_die_id = ocotp_get_die_id_mx, 392 }; 393 394 static const struct ocotp_instance ocotp_imx7d = { 395 .nb_banks = 8, 396 .nb_words = 8, 397 .get_die_id = ocotp_get_die_id_mx, 398 }; 399 400 static const struct ocotp_instance ocotp_imx7ulp = { 401 .nb_banks = 32, 402 .nb_words = 8, 403 .get_die_id = ocotp_get_die_id_mx7ulp, 404 }; 405 406 static const struct ocotp_instance ocotp_imx8m = { 407 .nb_banks = 32, 408 .nb_words = 8, 409 .get_die_id = ocotp_get_die_id_mx, 410 .write_fuse = ocotp_write_fuse, 411 }; 412 413 static const struct ocotp_instance ocotp_imx8mp = { 414 .nb_banks = 48, 415 .nb_words = 8, 416 .get_die_id = ocotp_get_die_id_mx, 417 .write_fuse = ocotp_write_fuse, 418 }; 419 420 int tee_otp_get_die_id(uint8_t *buffer, size_t len) 421 { 422 size_t max_size_uid = IMX_UID_SIZE; 423 uint64_t uid = 0; 424 425 assert(buffer); 426 assert(g_base_addr && g_ocotp); 427 428 if (g_ocotp->get_die_id(&uid)) 429 goto err; 430 431 memcpy(buffer, &uid, MIN(max_size_uid, len)); 432 return 0; 433 434 err: 435 EMSG("Error while getting die ID"); 436 return -1; 437 } 438 439 register_phys_mem_pgdir(MEM_AREA_IO_SEC, OCOTP_BASE, CORE_MMU_PGDIR_SIZE); 440 static TEE_Result imx_ocotp_init(void) 441 { 442 g_base_addr = core_mmu_get_va(OCOTP_BASE, MEM_AREA_IO_SEC, OCOTP_SIZE); 443 if (!g_base_addr) 444 return TEE_ERROR_GENERIC; 445 446 if (soc_is_imx6sdl() || soc_is_imx6dq() || soc_is_imx6dqp()) { 447 g_ocotp = &ocotp_imx6q; 448 } else if (soc_is_imx6sl()) { 449 g_ocotp = &ocotp_imx6sl; 450 } else if (soc_is_imx6sll()) { 451 g_ocotp = &ocotp_imx6sll; 452 } else if (soc_is_imx6sx()) { 453 g_ocotp = &ocotp_imx6sx; 454 } else if (soc_is_imx6ul()) { 455 g_ocotp = &ocotp_imx6ul; 456 } else if (soc_is_imx6ull()) { 457 g_ocotp = &ocotp_imx6ull; 458 } else if (soc_is_imx7ds()) { 459 g_ocotp = &ocotp_imx7d; 460 } else if (soc_is_imx7ulp()) { 461 g_ocotp = &ocotp_imx7ulp; 462 } else if (soc_is_imx8mm() || soc_is_imx8mn() || soc_is_imx8mq()) { 463 g_ocotp = &ocotp_imx8m; 464 } else if (soc_is_imx8mp()) { 465 g_ocotp = &ocotp_imx8mp; 466 } else { 467 g_ocotp = NULL; 468 return TEE_ERROR_NOT_SUPPORTED; 469 } 470 471 return TEE_SUCCESS; 472 } 473 service_init(imx_ocotp_init); 474