| 65873b54 | 14-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: add support for CFG_SCMI_MSG_SMT_FASTCALL_ENTRY
Add necessary calls to scmi_smt_fastcall_smc_entry from sm_platform handler to be able to do SCMI calls via SMC.
Signed-off-by: Clément Lég
plat-sam: add support for CFG_SCMI_MSG_SMT_FASTCALL_ENTRY
Add necessary calls to scmi_smt_fastcall_smc_entry from sm_platform handler to be able to do SCMI calls via SMC.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
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| 3ae16402 | 06-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: add SCMI server foundation
Add foundations for SCMI server support. This will be used to expose clocks and regulators to non-secure world.
Signed-off-by: Clément Léger <clement.leger@boot
plat-sam: add SCMI server foundation
Add foundations for SCMI server support. This will be used to expose clocks and regulators to non-secure world.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
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| 513a3100 | 16-Mar-2023 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: nsec-service: Fix include order
Reorder includes in alphabetical order.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> |
| 2651558d | 12-May-2023 |
Ralph Siemsen <ralph.siemsen@linaro.org> |
plat-rzn1: increase DDR size to 1GB
There are now some RZ/N1 devices with 1GB rather than 256MB. The first-stage bootloader does not support passing a DT to OP-TEE, so static values are set at compi
plat-rzn1: increase DDR size to 1GB
There are now some RZ/N1 devices with 1GB rather than 256MB. The first-stage bootloader does not support passing a DT to OP-TEE, so static values are set at compile time. Increase the DDR size so as to avoid OP-TEE calls failing with TEEC_ERROR_OUT_OF_MEMORY.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
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| 0d928692 | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: support physically relocatable OP-TEE binary
With CFG_CORE_PHYS_RELOCATABLE=y enable support in OP-TEE to relocate itself to allow it to run from physical address that differs from the link ad
core: support physically relocatable OP-TEE binary
With CFG_CORE_PHYS_RELOCATABLE=y enable support in OP-TEE to relocate itself to allow it to run from physical address that differs from the link address.
This feature is currently only supported with CFG_CORE_SEL2_SPMC=y since the TEE core has to know the range of available memory. With SPMC at EL2 this is accomplished via get_sec_mem_from_manifest(). An SPMC at S-EL2 may need to load OP-TEE at a different address depending on configuration.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| e1602654 | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: ffa: parse boot info
With CFG_CORE_SEL2_SPMC=y OP-TEE is executed as an SP at S-EL1. The manifest describing the OP-TEE SP is passed as a boot argument.
The manifest contains among other thin
core: ffa: parse boot info
With CFG_CORE_SEL2_SPMC=y OP-TEE is executed as an SP at S-EL1. The manifest describing the OP-TEE SP is passed as a boot argument.
The manifest contains among other things the two properties "load-address" and "mem-size". These cover the secure memory allocated for OP-TEE to cover core and TA memory. The retrieved memory range is saved with a call to core_mmu_set_secure_memory() to be used when initializing MMU and other memory configuration.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 5489e94f | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: ffa: add boot info structs and defines
Adds defines to interpret FF-A Boot Info header and descriptor using two new structs and accompanying defines.
Acked-by: Etienne Carriere <etienne.carri
core: ffa: add boot info structs and defines
Adds defines to interpret FF-A Boot Info header and descriptor using two new structs and accompanying defines.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 3003505d | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: generic_ram_layout.h: remove TA_RAM_*
Removes the TA_RAM_START and TA_RAM_SIZE defines since core_mmu.c can calculate the values based registered secure_only memory.
Reviewed-by: Etienne
core: arm: generic_ram_layout.h: remove TA_RAM_*
Removes the TA_RAM_START and TA_RAM_SIZE defines since core_mmu.c can calculate the values based registered secure_only memory.
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 54e4b08c | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: virt: use core_mmu_get_ta_range()
In get_ta_ram_size() use core_mmu_get_ta_range() instead of the define TA_RAM_SIZE.
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by
core: virt: use core_mmu_get_ta_range()
In get_ta_ram_size() use core_mmu_get_ta_range() instead of the define TA_RAM_SIZE.
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 23419643 | 10-Jan-2023 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: notif: fix input comment typo
Fixes inline comment typo in OP-TEE standard SMCs description and CFG_CORE_ASYNC_NOTIF switch description.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org
core: notif: fix input comment typo
Fixes inline comment typo in OP-TEE standard SMCs description and CFG_CORE_ASYNC_NOTIF switch description.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| f7f7b505 | 02-May-2023 |
Etienne Carriere <etienne.carriere@linaro.org> |
plat-vexpress: remove TPM2 MMIO driver
Disable TPM2 MMIO driver and remove its integration from platform vexpress. OP-TEE will instead rely on a remote REE TPM2 driver allowing REE OS to embed TPM2
plat-vexpress: remove TPM2 MMIO driver
Disable TPM2 MMIO driver and remove its integration from platform vexpress. OP-TEE will instead rely on a remote REE TPM2 driver allowing REE OS to embed TPM2 software stack and leverage TPM2 features.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| d8cc16cf | 17-Apr-2023 |
Clement Faure <clement.faure@nxp.com> |
core: ls: remove CFG_WITH_SOFTWARE_PRNG default definition for LS platforms
Remove the enablement of CFG_WITH_SOFTWARE_PRNG flag when the CAAM is disabled. CFG_WITH_SOFTWARE_PRNG is enabled by defau
core: ls: remove CFG_WITH_SOFTWARE_PRNG default definition for LS platforms
Remove the enablement of CFG_WITH_SOFTWARE_PRNG flag when the CAAM is disabled. CFG_WITH_SOFTWARE_PRNG is enabled by default.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| e8e3c6a9 | 13-Apr-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: remove CFG_WITH_SOFTWARE_PRNG default definition for i.MX platforms
Remove the enablement of CFG_WITH_SOFTWARE_PRNG ?= y since it's already globally enabled.
Signed-off-by: Clement Faure
core: imx: remove CFG_WITH_SOFTWARE_PRNG default definition for i.MX platforms
Remove the enablement of CFG_WITH_SOFTWARE_PRNG ?= y since it's already globally enabled.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 83ee3b4d | 28-Apr-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: remove drivers directory
Remove drivers directory from plat-imx/ since all drivers should go to core/drivers/. Move tzc380.c to plat-imx/
Signed-off-by: Clement Faure <clement.faure@nxp.
core: imx: remove drivers directory
Remove drivers directory from plat-imx/ since all drivers should go to core/drivers/. Move tzc380.c to plat-imx/
Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 92b64e4f | 28-Apr-2023 |
Clement Faure <clement.faure@nxp.com> |
drivers: imx_csu: move imx_csu driver source file
Move imx_csu driver from plat-imx/ to core/drivers/ Rename CFG_CSU to CFG_IMX_CSU compilation flag.
Signed-off-by: Clement Faure <clement.faure@nxp
drivers: imx_csu: move imx_csu driver source file
Move imx_csu driver from plat-imx/ to core/drivers/ Rename CFG_CSU to CFG_IMX_CSU compilation flag.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 40c3f16e | 28-Apr-2023 |
Clement Faure <clement.faure@nxp.com> |
drivers: imx_scu: move imx_scu driver source file
Move imx_scu driver from plat-imx/ to core/drivers/ Rename CFG_SCU to CFG_IMX_SCU compilation flag.
Signed-off-by: Clement Faure <clement.faure@nxp
drivers: imx_scu: move imx_scu driver source file
Move imx_scu driver from plat-imx/ to core/drivers/ Rename CFG_SCU to CFG_IMX_SCU compilation flag.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| fab76a67 | 28-Apr-2023 |
Clement Faure <clement.faure@nxp.com> |
driver: imx_caam: move imx_caam driver source file
Move imx_caam driver from plat-imx/ to core/drivers/
Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Jerome Forissier <jerome.fo
driver: imx_caam: move imx_caam driver source file
Move imx_caam driver from plat-imx/ to core/drivers/
Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| f727e838 | 28-Apr-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: caam: remove imx_caam.h header file
Remove imx_caam header file and move its content to source file.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jero
core: imx: caam: remove imx_caam.h header file
Remove imx_caam header file and move its content to source file.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| c7f21af4 | 28-Apr-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: remove unnecessary preprocessor directive
Remove error regarding CFG_WITH_PAGER and CFG_WITH_LPAE on imx6ul/ull.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome For
core: imx: remove unnecessary preprocessor directive
Remove error regarding CFG_WITH_PAGER and CFG_WITH_LPAE on imx6ul/ull.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 28638023 | 28-Apr-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: scu: move SCU configuration values to source file
Move SCU configuration values from header file to the SCU source file.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Je
core: imx: scu: move SCU configuration values to source file
Move SCU configuration values from header file to the SCU source file.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 249c9780 | 17-Apr-2023 |
Clement Faure <clement.faure@nxp.com> |
core: imx: remove imx_sip.h
Remove imx_sip.h header file. Move definitions to the source file.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@l
core: imx: remove imx_sip.h
Remove imx_sip.h header file. Move definitions to the source file.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| acaba7aa | 19-Apr-2023 |
Balint Dobszay <balint.dobszay@arm.com> |
core: spmc: handle HW feature info in SP manifest
Provide information to the SP about available HW features by updating the relevant DT node in the SP manifest. Currently only the CRC32 feature is s
core: spmc: handle HW feature info in SP manifest
Provide information to the SP about available HW features by updating the relevant DT node in the SP manifest. Currently only the CRC32 feature is supported.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
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| d4351c1e | 17-Apr-2023 |
Balint Dobszay <balint.dobszay@arm.com> |
core: arm64: add CRC32 HW support discovery
Add helper function to check if the CRC32 instructions are implemented by the PE.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: J
core: arm64: add CRC32 HW support discovery
Add helper function to check if the CRC32 instructions are implemented by the PE.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
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| 9e3c57c8 | 28-Feb-2023 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: dt_driver: move related content from dt.h to dt_driver.h
Moves so-called dt_driver related declarations and definitions from dt.h to dt_drivers.h. Incidentally adds an inline description to en
core: dt_driver: move related content from dt.h to dt_driver.h
Moves so-called dt_driver related declarations and definitions from dt.h to dt_drivers.h. Incidentally adds an inline description to enum dt_driver_type. This change clarifies when a source file shall include dt.h and/or dt_driver.h.
This change updates driver source files to include none, one or both of these header files where applicable.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| d690c838 | 11-Apr-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: kern.ld.S: assert load address page aligned
Simplify things and assert that the start of text or load address is page aligned instead. This replaces the more relaxed check for 32-byte or
core: arm: kern.ld.S: assert load address page aligned
Simplify things and assert that the start of text or load address is page aligned instead. This replaces the more relaxed check for 32-byte or 128-byte alignment depending on ARM32 or ARM64. This also helps later when introducing physical relocation of the OP-TEE binary.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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