plat-stm32mp1: introduce CFG_STM32MP1_SHARED_RESOURCES

It is now mandatory to enable CFG_STM32MP1_SHARED_RESOURCES to embed
shared_resources.c.

It is forced enabled for STM32MP15x boards and forced

plat-stm32mp1: introduce CFG_STM32MP1_SHARED_RESOURCES

It is now mandatory to enable CFG_STM32MP1_SHARED_RESOURCES to embed
shared_resources.c.

It is forced enabled for STM32MP15x boards and forced disabled for
STM32MP13x boards.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_shared_io: introduce shared io driver

This commit implements shared registers support, previously handled in
core/arch/arm/plat-stm32mp1/shared_resources.c, at platform level.

Defaul

drivers: stm32_shared_io: introduce shared io driver

This commit implements shared registers support, previously handled in
core/arch/arm/plat-stm32mp1/shared_resources.c, at platform level.

Default enable CFG_STM32_SHARED_IO.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: handle large holes in S-EL0 map

Prior to this patch it was assumed that the memory map of a user mode
context had no holes or very small holes. This leads to a higher pressure
on the translati

core: handle large holes in S-EL0 map

Prior to this patch it was assumed that the memory map of a user mode
context had no holes or very small holes. This leads to a higher pressure
on the translation tables than necessary.

So fix this by skipping to allocate translation tables for holes in the
memory map of a user mode context where possible.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ls: add CAAM_SIZE values for LS platforms

Add CAAM_SIZE values for all LS platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

core: imx: add CAAM_SIZE values for i.MX platforms

Add CAAM_SIZE values for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.

core: imx: add CAAM_SIZE values for i.MX platforms

Add CAAM_SIZE values for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: sama5d2: Set tcb1 as secure

Add missing status-okay line to enable tcb1 for OP-TEE usage. Indeed,
the TCB block is used to provide a secure time source to OP-TEE TA.

Signed-off-by: Clément Lég

dts: sama5d2: Set tcb1 as secure

Add missing status-okay line to enable tcb1 for OP-TEE usage. Indeed,
the TCB block is used to provide a secure time source to OP-TEE TA.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: make sure build date is always in English

Setting LANG=C before invoking the date command doesn't always result in
the "C" (English) locale being selected. The correct way is to set
LC_ALL. As

core: make sure build date is always in English

Setting LANG=C before invoking the date command doesn't always result in
the "C" (English) locale being selected. The correct way is to set
LC_ALL. As explained in the locale(7) man page:

If the second argument to setlocale(3) is an empty string, "", for the
default locale, it is determined using the following steps:

1. If there is a non-null environment variable LC_ALL, the value of
LC_ALL is used.

2. If an environment variable with the same name as one of the
categories above exists and is non-null, its value is used for that
category.

3. If there is a non-null environment variable LANG, the value of LANG
is used.

Fixes: 3e2b963515c1 ("core: use C locale when generating the build date")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Tested-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: remove SCMI0 channel index

Removes index 0 from SCMI DT binding ID macros and driver labels to
synchronize with Linux kernel 5.18 that considers a single SCMI
channel, see [1] and [2]

plat-stm32mp1: remove SCMI0 channel index

Removes index 0 from SCMI DT binding ID macros and driver labels to
synchronize with Linux kernel 5.18 that considers a single SCMI
channel, see [1] and [2].

Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-4-alexandre.torgue@foss.st.com
Link: [2] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-5-alexandre.torgue@foss.st.com
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: scmi_server: removed unused channel SCMI1

Remove this SCMI channel from DT bindings and platform driver as it is
unused.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.c

plat-stm32mp1: scmi_server: removed unused channel SCMI1

Remove this SCMI channel from DT bindings and platform driver as it is
unused.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: use helper header file stm32mp_dt_bindings.h

Changes plat-stm32mp1 and its drivers to rely on stm32mp_dt_bindings.h
which simplifies support of both variants STM32MP15 and STM32MP13 t

plat-stm32mp1: use helper header file stm32mp_dt_bindings.h

Changes plat-stm32mp1 and its drivers to rely on stm32mp_dt_bindings.h
which simplifies support of both variants STM32MP15 and STM32MP13 that
will use each specific DT bindings.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: default disable ASLR

Default disable CFG_CORE_ASLR on stm32mp1. The platform memory
firewall does not allow secure world to access external DTB in
non-secure memory when MMU is

plat-stm32mp1: conf: default disable ASLR

Default disable CFG_CORE_ASLR on stm32mp1. The platform memory
firewall does not allow secure world to access external DTB in
non-secure memory when MMU is OFF, which is what the software attempts
to do when CFG_CORE_ASLR=y.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: update RAM configuration

Align platform RAM configuration with TF-A.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.car

plat-stm32mp1: conf: update RAM configuration

Align platform RAM configuration with TF-A.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: default heap size to 48kB when pager is on

Changes default heap size from 64kB to 48kB when pager is enabled.
The saved physical pages are assigned to pager pool.

Signed-off-by

plat-stm32mp1: conf: default heap size to 48kB when pager is on

Changes default heap size from 64kB to 48kB when pager is enabled.
The saved physical pages are assigned to pager pool.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: allow BSEC writing in debug mode

Default embed support for burning fuses when in debug build configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Rev

plat-stm32mp1: conf: allow BSEC writing in debug mode

Default embed support for burning fuses when in debug build configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: disable TA compression when pager is on

Disable CFG_EARLY_TA_COMPRESS when CFG_WITH_PAGER is enabled. With this
change, the TAs will not be compressed into the TEE binary. Now,

plat-stm32mp1: conf: disable TA compression when pager is on

Disable CFG_EARLY_TA_COMPRESS when CFG_WITH_PAGER is enabled. With this
change, the TAs will not be compressed into the TEE binary. Now, core
heap can be smaller than 64kB and platform can leverage that to assign
more physical pages in the pager pool.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: conf: remove shared memory configuration

This change fully removes the reserved static shared memory
(CFG_SHMEM_START/CFG_SHMEM_SIZE) that is no more needed since U-Boot
and Linux bot

plat-stm32mp1: conf: remove shared memory configuration

This change fully removes the reserved static shared memory
(CFG_SHMEM_START/CFG_SHMEM_SIZE) that is no more needed since U-Boot
and Linux both use their standard system memory as TEE shared memory.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-k3: drivers: Fix SA2UL background firewall size

For GP devices this first firewall region should be a background region
that spans the whole address space managed by this firewall. This allows

plat-k3: drivers: Fix SA2UL background firewall size

For GP devices this first firewall region should be a background region
that spans the whole address space managed by this firewall. This allows
normal use of devices behind it even when not explicitly permitted.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-k3: drivers: Add SA2UL RNG driver

TI K3 family devices contain a set of crypto accelerators under
the umbrella device SA2UL. Add support for setting up the power
and firewalls for this device.

plat-k3: drivers: Add SA2UL RNG driver

TI K3 family devices contain a set of crypto accelerators under
the umbrella device SA2UL. Add support for setting up the power
and firewalls for this device. Then add support for the TRNG
sub-device.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-k3: Move TI-SCI setup out of HUK function

The TI-SCI components are used for more than just the hardware
unique key, move the setup out into a service_init so it is
not tied to just HUK.

While

plat-k3: Move TI-SCI setup out of HUK function

The TI-SCI components are used for more than just the hardware
unique key, move the setup out into a service_init so it is
not tied to just HUK.

While here remove the device check for HUK, it works on all
supported K3 devices.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-k3: drivers: ti-sci: Add support for setting firewall state

This adds support for the TI-SCI firewall messages:
* TI_SCI_MSG_FWL_SET
* TI_SCI_MSG_FWL_GET
* TI_SCI_MSG_FWL_CHANGE_OWNER

Signe

plat-k3: drivers: ti-sci: Add support for setting firewall state

This adds support for the TI-SCI firewall messages:
* TI_SCI_MSG_FWL_SET
* TI_SCI_MSG_FWL_GET
* TI_SCI_MSG_FWL_CHANGE_OWNER

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-k3: drivers: ti-sci: Add support for setting device state

This adds support for the TI-SCI TI_SCI_MSG_SET_DEVICE_STATE message.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Foriss

plat-k3: drivers: ti-sci: Add support for setting device state

This adds support for the TI-SCI TI_SCI_MSG_SET_DEVICE_STATE message.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: clk: remove stm32_clock_*() helpers

Removes function that were deprecated: stm32_clock_is_enabled(),
stm32_clock_enable(), stm32_clock_disable() and stm32_clock_get_rate().

Signed-off-by:

drivers: clk: remove stm32_clock_*() helpers

Removes function that were deprecated: stm32_clock_is_enabled(),
stm32_clock_enable(), stm32_clock_disable() and stm32_clock_get_rate().

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: armv7: fix ASLR error

With commit 528dabb28254 ("core: suppress text relocation on
stack_tmp_export") the stack pointer is calculated using a relative
address instead of based on an absolute a

core: armv7: fix ASLR error

With commit 528dabb28254 ("core: suppress text relocation on
stack_tmp_export") the stack pointer is calculated using a relative
address instead of based on an absolute address which is relocated with
ASLR enabled.

Prior to this on Armv7 we compensate for a relocation update for
stack_tmp_export_rel in reset_secondary() just after the stack pointer
was initialized. So now when the relocation update of stack_tmp_export_rel
is gone remove the compensating code too.

Fixes: 528dabb28254 ("core: suppress text relocation on stack_tmp_export")
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: sp: handle memory regions w/o base address

The FF-A spec states that in the SP manifest a base address is not
mandatory for memory regions. If the field is not present, the specified
memory re

core: sp: handle memory regions w/o base address

The FF-A spec states that in the SP manifest a base address is not
mandatory for memory regions. If the field is not present, the specified
memory region must be allocated by the SPMC and mapped to the SP's
context.

A copy of the SP manifest fdt is used for passing the memory region
virtual addresses to the SP. Additional space is allocated when copying
the fdt so the originally not present base address fields can be added
later.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
[jf: edit description to avoid checkpatch spelling warning]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: sp: map memory regions from SP manifest

Currently the SP manifest processing only handles the device regions,
add support to handle the normal memory regions too.

Note: if the region's base a

core: sp: map memory regions from SP manifest

Currently the SP manifest processing only handles the device regions,
add support to handle the normal memory regions too.

Note: if the region's base address is a PA, according to the FF-A spec
it has to be identity mapped to the same VA. This requirement will be
removed in the spec's next version, so the current implementation should
be acceptable.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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