1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 3flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 4flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 5flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 6 7flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) 8 9flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 10 11flavorlist-cryp-1G = $(flavor_dts_file-157C_ED1) \ 12 $(flavor_dts_file-157C_EV1) 13 14flavorlist-no_cryp = $(flavorlist-no_cryp-512M) 15 16flavorlist-512M = $(flavorlist-cryp-512M) \ 17 $(flavorlist-no_cryp-512M) 18 19flavorlist-1G = $(flavorlist-cryp-1G) 20 21ifneq ($(PLATFORM_FLAVOR),) 22ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 23$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 24endif 25CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 26endif 27 28ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 29$(call force,CFG_STM32_CRYP,n) 30endif 31 32include core/arch/arm/cpu/cortex-a7.mk 33 34$(call force,CFG_CORE_RESERVED_SHM,n) 35$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 36$(call force,CFG_DRIVERS_CLK,y) 37$(call force,CFG_DRIVERS_CLK_FIXED,n) 38$(call force,CFG_GIC,y) 39$(call force,CFG_INIT_CNTVOFF,y) 40$(call force,CFG_PSCI_ARM32,y) 41$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 42$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 43$(call force,CFG_SM_PLATFORM_HANDLER,y) 44$(call force,CFG_WITH_SOFTWARE_PRNG,y) 45 46CFG_TEE_CORE_NB_CORE ?= 2 47CFG_WITH_PAGER ?= y 48CFG_WITH_LPAE ?= y 49CFG_MMAP_REGIONS ?= 23 50CFG_DTB_MAX_SIZE ?= (256 * 1024) 51 52ifeq ($(CFG_EMBED_DTB_SOURCE_FILE),) 53# Some drivers mandate DT support 54$(call force,CFG_DRIVERS_CLK_DT,n) 55$(call force,CFG_STM32_CRYP,n) 56$(call force,CFG_STM32_GPIO,n) 57$(call force,CFG_STM32_I2C,n) 58$(call force,CFG_STM32_IWDG,n) 59$(call force,CFG_STM32_TAMP,n) 60$(call force,CFG_STPMIC1,n) 61$(call force,CFG_STM32MP1_SCMI_SIP,n) 62$(call force,CFG_SCMI_PTA,n) 63else 64$(call force,CFG_DRIVERS_CLK_DT,y) 65endif 66 67ifeq ($(CFG_STM32MP13),y) 68$(call force,CFG_STM32MP15,n) 69$(call force,CFG_STM32MP_CLK_CORE,y) 70$(call force,CFG_STM32MP13_CLK,y) 71$(call force,CFG_STM32MP15_CLK,n) 72CFG_STM32MP_OPP_COUNT ?= 2 73else 74$(call force,CFG_STM32MP15,y) 75$(call force,CFG_STM32MP15_CLK,y) 76endif 77 78ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 79CFG_TZDRAM_START ?= 0xde000000 80CFG_DRAM_SIZE ?= 0x20000000 81endif 82 83CFG_DRAM_BASE ?= 0xc0000000 84CFG_DRAM_SIZE ?= 0x40000000 85CFG_TZSRAM_START ?= 0x2ffc0000 86CFG_TZSRAM_SIZE ?= 0x0003f000 87CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000 88CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000 89ifeq ($(CFG_STM32MP15),y) 90CFG_TZDRAM_START ?= 0xfe000000 91CFG_TZDRAM_SIZE ?= 0x01e00000 92else 93CFG_TZDRAM_SIZE ?= 0x02000000 94CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 95endif #CFG_STM32MP15 96 97CFG_STM32_BSEC ?= y 98CFG_STM32_CRYP ?= y 99CFG_STM32_ETZPC ?= y 100CFG_STM32_GPIO ?= y 101CFG_STM32_I2C ?= y 102CFG_STM32_IWDG ?= y 103CFG_STM32_RNG ?= y 104CFG_STM32_RSTCTRL ?= y 105CFG_STM32_TAMP ?= y 106CFG_STM32_UART ?= y 107CFG_STPMIC1 ?= y 108CFG_TZC400 ?= y 109 110ifeq ($(CFG_STPMIC1),y) 111$(call force,CFG_STM32_I2C,y) 112$(call force,CFG_STM32_GPIO,y) 113endif 114 115# if any crypto driver is enabled, enable the crypto-framework layer 116ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y) 117$(call force,CFG_STM32_CRYPTO_DRIVER,y) 118endif 119 120CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 121$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 122 123CFG_WDT ?= $(CFG_STM32_IWDG) 124 125# Platform specific configuration 126CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 127 128# SiP/OEM service for non-secure world 129CFG_STM32_BSEC_SIP ?= y 130CFG_STM32MP1_SCMI_SIP ?= n 131ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 132$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 133$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 134$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 135endif 136 137# Default enable SCMI PTA support 138CFG_SCMI_PTA ?= y 139ifeq ($(CFG_SCMI_PTA),y) 140$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 141$(call force,CFG_SCMI_MSG_SMT_THREAD_ENTRY,y,Mandated by CFG_SCMI_PTA) 142CFG_SCMI_MSG_SHM_MSG ?= y 143CFG_SCMI_MSG_SMT ?= y 144endif 145 146CFG_SCMI_MSG_DRIVERS ?= n 147ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 148$(call force,CFG_SCMI_MSG_CLOCK,y) 149$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 150CFG_SCMI_MSG_SHM_MSG ?= y 151CFG_SCMI_MSG_SMT ?= y 152CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 153$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 154endif 155 156# Provision enough threads to pass xtest 157ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 158ifeq ($(CFG_WITH_PAGER),y) 159CFG_NUM_THREADS ?= 3 160else 161CFG_NUM_THREADS ?= 10 162endif 163endif 164 165# Default enable some test facitilites 166CFG_ENABLE_EMBEDDED_TESTS ?= y 167CFG_WITH_STATS ?= y 168 169# Enable to allow debug 170CFG_STM32_BSEC_WRITE ?= $(CFG_TEE_CORE_DEBUG) 171 172# Default disable some support for pager memory size constraint 173ifeq ($(CFG_WITH_PAGER),y) 174CFG_TEE_CORE_DEBUG ?= n 175CFG_UNWIND ?= n 176CFG_LOCKDEP ?= n 177CFG_CORE_ASLR ?= n 178CFG_TA_BGET_TEST ?= n 179# Default disable early TA compression to support a smaller HEAP size 180CFG_EARLY_TA_COMPRESS ?= n 181CFG_CORE_HEAP_SIZE ?= 49152 182endif 183 184# Non-secure UART and GPIO/pinctrl for the output console 185CFG_WITH_NSEC_GPIOS ?= y 186CFG_WITH_NSEC_UARTS ?= y 187# UART instance used for early console (0 disables early console) 188CFG_STM32_EARLY_CONSOLE_UART ?= 4 189