| 8c38a70c | 04-Nov-2025 |
Thomas Bourgoin <thomas.bourgoin@foss.st.com> |
plat-stm32mp2: conf: default enable CFG_STM32_I2C for stm32mp2 family
Default enable STM32 I2C driver on STM32MP2 platforms.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Reviewed-by
plat-stm32mp2: conf: default enable CFG_STM32_I2C for stm32mp2 family
Default enable STM32 I2C driver on STM32MP2 platforms.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 967e7220 | 11-Sep-2025 |
Thomas Bourgoin <thomas.bourgoin@foss.st.com> |
plat-stm32mp2: conf: support STM32MP23x SoC family
Add support for the STM32MP23 SoC family and the stm32mp235f-dk board.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Reviewed-by: E
plat-stm32mp2: conf: support STM32MP23x SoC family
Add support for the STM32MP23 SoC family and the stm32mp235f-dk board.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 31e114fa | 12-Sep-2025 |
Thomas Bourgoin <thomas.bourgoin@foss.st.com> |
plat-stm32mp2: conf: default enable CFG_SCMI_SCPFW
For STM32MP2x families the SCP firmware is the only SCMI server supported. Default enable CFG_SCMI_SCPFW=y in conf.mk
Signed-off-by: Thomas Bourgo
plat-stm32mp2: conf: default enable CFG_SCMI_SCPFW
For STM32MP2x families the SCP firmware is the only SCMI server supported. Default enable CFG_SCMI_SCPFW=y in conf.mk
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 68248727 | 02-Jan-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp2: conf: add stm32mp257f-dk board support
Add support for the stm32mp257f-dk board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Thomas Bourgoin <thom
plat-stm32mp2: conf: add stm32mp257f-dk board support
Add support for the stm32mp257f-dk board.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 11d68b67 | 11-Jan-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp2: enable watchdog SMC service
Enable Arm watchdog SMC service using function ID 0xbc000000.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Clément Le Gof
plat-stm32mp2: enable watchdog SMC service
Enable Arm watchdog SMC service using function ID 0xbc000000.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 9bfde4b3 | 12-Jan-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp2: conf: default enable CFG_STM32_IWDG
Default enable STM32 IWDG driver on STM32MP2 platforms.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Clément Le G
plat-stm32mp2: conf: default enable CFG_STM32_IWDG
Default enable STM32 IWDG driver on STM32MP2 platforms.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| d8bfc12a | 25-Apr-2025 |
Thomas Bourgoin <thomas.bourgoin@foss.st.com> |
plat: stm32mp2: sysconf: fix CA35SS register names
Align register names with the reference manuel for Arm Cortex-A35 (CA35SS) - CA35SS SYSCFG registers (with 0x2000 offset) - CA35SS Standardized sta
plat: stm32mp2: sysconf: fix CA35SS register names
Align register names with the reference manuel for Arm Cortex-A35 (CA35SS) - CA35SS SYSCFG registers (with 0x2000 offset) - CA35SS Standardized status and control (SSC) registers
This path removes the confusion between SSC and subsystem (SS).
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Co-developed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| fcbd9ef9 | 25-Apr-2025 |
Thomas Bourgoin <thomas.bourgoin@foss.st.com> |
plat-stm32mp2: sysconfig: fix ordering of SYSCFG defines
Reorder SYSCFG defines to prepare renaming so the defines use the same name as the one in the reference manual.
Signed-off-by: Thomas Bourgo
plat-stm32mp2: sysconfig: fix ordering of SYSCFG defines
Reorder SYSCFG defines to prepare renaming so the defines use the same name as the one in the reference manual.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 072babca | 16-Jun-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp2: implement do_reset() API to force a system reset
Implement the do_reset() API that traps all cores if the SoC has multiple cores, then prints a message and forces a system reset.
Sig
plat-stm32mp2: implement do_reset() API to force a system reset
Implement the do_reset() API that traps all cores if the SoC has multiple cores, then prints a message and forces a system reset.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 7653887e | 18-Jun-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
core: panic: allow core halting on SGI in other cases than panic()
There may be cases where we want to halt several cores outside of a panic() sequence.
Therefore, add CFG_MULTI_CORE_HALTING switch
core: panic: allow core halting on SGI in other cases than panic()
There may be cases where we want to halt several cores outside of a panic() sequence.
Therefore, add CFG_MULTI_CORE_HALTING switch that allows to register an interrupt handler for the CFG_HALT_CORES_SGI that is dedicated to halt other cores.
This reduces the scope of CFG_HALT_CORES_ON_PANIC that is now used only for halting other cores in a panic() sequence.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 446da993 | 27-Jun-2025 |
Clément Le Goffic <clement.legoffic@foss.st.com> |
drivers: stm32_rtc: add init configuration function
The init function aims to contains init configurations of the RTC peripheral such as prescalers, config or calibration registers. Add "CFG_STM32_H
drivers: stm32_rtc: add init configuration function
The init function aims to contains init configurations of the RTC peripheral such as prescalers, config or calibration registers. Add "CFG_STM32_HIGH_ACCURACY" (default to no) config to enable the high accuracy mode which allow the highest refresh rate of the subsecond register. Also merge the functions `stm32_rtc_wait_sync()` with `stm32_exit_init_mode()` as every stm32 exit init mode was followed by a wait sync.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| f6f2dc44 | 09-Nov-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp2: enable async notif with GIC PPI 15
Enables OP-TEE async notif (asynchronous notification from OP-TEE to the non-secure world) using GIC PPI 15 (GIC interrupt line 31).
Signed-off-by:
plat-stm32mp2: enable async notif with GIC PPI 15
Enables OP-TEE async notif (asynchronous notification from OP-TEE to the non-secure world) using GIC PPI 15 (GIC interrupt line 31).
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| f2699bc4 | 09-Feb-2024 |
Clément Le Goffic <clement.legoffic@foss.st.com> |
plat-stm32mp2: add support for RTC PTA
Compile the RTC PTA and the RTC driver if the RTC driver for stm32 is enabled.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Reviewed-by: Et
plat-stm32mp2: add support for RTC PTA
Compile the RTC PTA and the RTC driver if the RTC driver for stm32 is enabled.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| ce59899c | 15-May-2025 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
plat-stm32mp2: update reset and clocks driver flags for STM32MP21
Add CFG_STM32MP21_CLK and CFG_STM32MP21_RSTCTRL flags to enable RCC drivers.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@fo
plat-stm32mp2: update reset and clocks driver flags for STM32MP21
Add CFG_STM32MP21_CLK and CFG_STM32MP21_RSTCTRL flags to enable RCC drivers.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 7b8c7554 | 03-Jun-2025 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz
When clkext2f is selected as the clock source, a division by 2 must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL) becau
clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz
When clkext2f is selected as the clock source, a division by 2 must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL) because the clkext2f frequency of 400MHz is not supported.
This patch also rename the function stm32mp2_a35_ss_on_hsi to stm32mp2_a35_ss_on_bypass to be aligned with reference manual.
Fixes: 28c10f9efa6a ("clk: stm32mp25: Introduce STM32MP25 clocks platform") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 6bf5be91 | 26-May-2025 |
Antonio Borneo <antonio.borneo@foss.st.com> |
plat-stm32mp2: conf: default enable CFG_STM32_EXTI
Enable the driver stm32_exti on stm32mp2xx.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carr
plat-stm32mp2: conf: default enable CFG_STM32_EXTI
Enable the driver stm32_exti on stm32mp2xx.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 90648185 | 27-May-2025 |
Thomas Bourgoin <thomas.bourgoin@foss.st.com> |
plat-stm32mp2: conf: support STM32MP21x SoC family
Add support for the STM32MP21x SoC family.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.che
plat-stm32mp2: conf: support STM32MP21x SoC family
Add support for the STM32MP21x SoC family.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 0a54a402 | 05-Feb-2025 |
Valentin Caron <valentin.caron@foss.st.com> |
plat: stm32mp2: make the platform ready to compile with SCP-Fw
STM32MP2 could use SCP-Fw to handle SCMI messages. By default this is disabled, but it could be enable with these config: CFG_SCMI_SC
plat: stm32mp2: make the platform ready to compile with SCP-Fw
STM32MP2 could use SCP-Fw to handle SCMI messages. By default this is disabled, but it could be enable with these config: CFG_SCMI_SCPFW=y CFG_SCP_FIRMWARE=<path_to_SCP-Fw_srcs>
On STM32MP2, OP-TEE use the resources describe in the "scmi" device-tree node to configure SCP-Fw.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 4561617b | 21-May-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp2: conf: support Octo-SPI manager driver
Default enable Octo-SPI manager driver on stm32mp2x platforms.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Eti
plat-stm32mp2: conf: support Octo-SPI manager driver
Default enable Octo-SPI manager driver on stm32mp2x platforms.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 22c24182 | 21-May-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp2: sysconfig: add OSPIs address mapping
This patch adds an API to handle OSPIs address mapping. The different configurations are: - OSPI1(256 MBytes), OSPI2(unmapped) - OSPI1(192 MByte
plat-stm32mp2: sysconfig: add OSPIs address mapping
This patch adds an API to handle OSPIs address mapping. The different configurations are: - OSPI1(256 MBytes), OSPI2(unmapped) - OSPI1(192 MBytes), OSPI2(64 MBytes) - OSPI1(128 MBytes), OSPI2(128 MBytes) - OSPI1(64 MBytes), OSPI2(192 MBytes) - OSPI1(unmapped), OSPI2(256 MBytes).
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 321b5b24 | 11-Oct-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp2: add platform-specific abort handler
When a data abort occurs and its fault type is FAULT_TYPE_IGNORE, it may be an abort generated by the SERC hardware block. Check if a SERC Illegal
plat-stm32mp2: add platform-specific abort handler
When a data abort occurs and its fault type is FAULT_TYPE_IGNORE, it may be an abort generated by the SERC hardware block. Check if a SERC Illegal Access was caught and print the SERC register and panic() if that is the case.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 37de1791 | 12-Dec-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp2: conf: default enable STGEN for STM32MP2 platforms
Default enable STGEN for STM32MP2 platforms.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne C
plat-stm32mp2: conf: default enable STGEN for STM32MP2 platforms
Default enable STGEN for STM32MP2 platforms.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| dcdbcea2 | 12-Dec-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp2: enable RTC framework if CFG_DRIVERS_RTC is set
If CFG_DRIVERS_RTC is enabled, force the compilation of the file core/drivers/rtc/rtc.c in order to share the generic functions.
Signed
plat-stm32mp2: enable RTC framework if CFG_DRIVERS_RTC is set
If CFG_DRIVERS_RTC is enabled, force the compilation of the file core/drivers/rtc/rtc.c in order to share the generic functions.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 4dcbaa6d | 12-Dec-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp2: conf: default enable the RTC driver
Default enable the RTC driver support on stm32mp2 platforms.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne
plat-stm32mp2: conf: default enable the RTC driver
Default enable the RTC driver support on stm32mp2 platforms.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 0ba375c0 | 23-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp2: remove deprecated shared_resource stub functions
Remove stm32mp2 platform shared_resources driver stub functions stm32mp_register_secure_periph_iomem(), stm32mp_register_non_secure_pe
plat-stm32mp2: remove deprecated shared_resource stub functions
Remove stm32mp2 platform shared_resources driver stub functions stm32mp_register_secure_periph_iomem(), stm32mp_register_non_secure_periph_iomem() and stm32mp_register_gpioz_pin_count() since shared_resources platform driver, inherited from stm32mp1, has been fully removed in the source tree.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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