1flavor_dts_file-215F_DK = stm32mp215f-dk.dts 2flavor_dts_file-235F_DK = stm32mp235f-dk.dts 3flavor_dts_file-257F_DK = stm32mp257f-dk.dts 4flavor_dts_file-257F_EV1 = stm32mp257f-ev1.dts 5 6flavorlist-MP21 = $(flavor_dts_file-215F_DK) 7 8flavorlist-MP23 = $(flavor_dts_file-235F_DK) 9 10flavorlist-MP25 = $(flavor_dts_file-257F_DK) \ 11 $(flavor_dts_file-257F_EV1) 12 13# List of all DTS for this PLATFORM 14ALL_DTS = $(flavorlist-MP21) $(flavorlist-MP23) $(flavorlist-MP25) 15 16ifneq ($(PLATFORM_FLAVOR),) 17ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 18$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 19endif 20CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 21endif 22CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp257f-ev1.dts 23 24ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP21)),) 25$(call force,CFG_STM32MP21,y) 26endif 27ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP23)),) 28$(call force,CFG_STM32MP23,y) 29endif 30ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP25)),) 31$(call force,CFG_STM32MP25,y) 32endif 33 34# CFG_STM32MP2x switches are exclusive. 35# - CFG_STM32MP21 is enabled for STM32MP21x-* targets 36# - CFG_STM32MP23 is enabled for STM32MP23x-* targets 37# - CFG_STM32MP25 is enabled for STM32MP25x-* targets (default) 38ifeq ($(CFG_STM32MP21),y) 39$(call force,CFG_STM32MP23,n) 40$(call force,CFG_STM32MP25,n) 41else ifeq ($(CFG_STM32MP23),y) 42$(call force,CFG_STM32MP21,n) 43$(call force,CFG_STM32MP25,n) 44else 45$(call force,CFG_STM32MP21,n) 46$(call force,CFG_STM32MP23,n) 47$(call force,CFG_STM32MP25,y) 48endif 49 50include core/arch/arm/cpu/cortex-armv8-0.mk 51supported-ta-targets ?= ta_arm64 52 53$(call force,CFG_ARM64_core,y) 54$(call force,CFG_CORE_ASYNC_NOTIF,y) 55$(call force,CFG_CORE_ASYNC_NOTIF_GIC_INTID,31) 56$(call force,CFG_DRIVERS_CLK,y) 57$(call force,CFG_DRIVERS_CLK_DT,y) 58$(call force,CFG_DRIVERS_GPIO,y) 59$(call force,CFG_DRIVERS_PINCTRL,y) 60$(call force,CFG_DT,y) 61$(call force,CFG_GIC,y) 62$(call force,CFG_HALT_CORES_SGI,15) 63$(call force,CFG_INIT_CNTVOFF,y) 64$(call force,CFG_SCMI_SCPFW_PRODUCT,stm32mp2) 65$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 66$(call force,CFG_STM32_SHARED_IO,y) 67$(call force,CFG_STM32_STGEN,y) 68$(call force,CFG_STM32MP_CLK_CORE,y) 69$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 70$(call force,CFG_WITH_LPAE,y) 71 72ifeq ($(CFG_STM32MP21),y) 73$(call force,CFG_STM32MP21_CLK,y) 74$(call force,CFG_STM32MP21_RSTCTRL,y) 75else 76$(call force,CFG_STM32MP25_CLK,y) 77$(call force,CFG_STM32MP25_RSTCTRL,y) 78endif 79 80CFG_TZDRAM_START ?= 0x82000000 81CFG_TZDRAM_SIZE ?= 0x02000000 82 83# Support DDR ranges up to 8GBytes (address range: 0x80000000 + DDR size) 84CFG_CORE_LARGE_PHYS_ADDR ?= y 85CFG_CORE_ARM64_PA_BITS ?= 34 86 87CFG_CORE_HEAP_SIZE ?= 262144 88CFG_CORE_RESERVED_SHM ?= n 89CFG_DTB_MAX_SIZE ?= 262144 90CFG_MULTI_CORE_HALTING ?= y 91CFG_MMAP_REGIONS ?= 30 92CFG_NUM_THREADS ?= 5 93ifeq ($(CFG_STM32MP21),y) 94$(call force,CFG_TEE_CORE_NB_CORE,1) 95endif 96CFG_TEE_CORE_NB_CORE ?= 2 97CFG_STM32MP_OPP_COUNT ?= 3 98 99CFG_STM32_EXTI ?= y 100CFG_STM32_FMC ?= y 101CFG_STM32_GPIO ?= y 102CFG_STM32_HPDMA ?= y 103CFG_STM32_HSEM ?= y 104CFG_STM32_I2C ?= y 105CFG_STM32_IAC ?= y 106CFG_STM32_IPCC ?= y 107CFG_STM32_IWDG ?= y 108CFG_STM32_OMM ?= y 109CFG_STM32_RIF ?= y 110CFG_STM32_RIFSC ?= y 111CFG_STM32_RISAB ?= y 112CFG_STM32_RISAF ?= y 113CFG_STM32_RNG ?= y 114CFG_STM32_RTC ?= y 115CFG_STM32_SERC ?= y 116CFG_STM32_TAMP ?= y 117CFG_STM32_UART ?= y 118 119CFG_DRIVERS_I2C ?= $(CFG_STM32_I2C) 120 121# Default RTC accuracy, higher accuracy means higher power consumption 122CFG_STM32_RTC_HIGH_ACCURACY ?= n 123 124CFG_SCMI_PTA ?= y 125CFG_SCMI_SCPFW ?= y 126CFG_SCMI_SCPFW_FROM_DT ?= y 127CFG_SCMI_SERVER_CLOCK_CONSUMER ?= y 128CFG_SCMI_SERVER_RESET_CONSUMER ?= y 129# Default enable some test facitilites 130CFG_ENABLE_EMBEDDED_TESTS ?= y 131CFG_WITH_STATS ?= y 132 133# Default disable ASLR 134CFG_CORE_ASLR ?= n 135 136# UART instance used for early console (0 disables early console) 137CFG_STM32_EARLY_CONSOLE_UART ?= 2 138 139# Default disable external DT support 140CFG_EXTERNAL_DT ?= n 141 142# Default enable HWRNG PTA support 143CFG_HWRNG_PTA ?= y 144ifeq ($(CFG_HWRNG_PTA),y) 145$(call force,CFG_STM32_RNG,y,Required by CFG_HWRNG_PTA) 146$(call force,CFG_WITH_SOFTWARE_PRNG,n,Required by CFG_HWRNG_PTA) 147CFG_HWRNG_QUALITY ?= 1024 148endif 149 150# Watchdog SMC service to non-secure world 151CFG_WDT ?= $(CFG_STM32_IWDG) 152CFG_WDT_SM_HANDLER ?= $(CFG_WDT) 153CFG_WDT_SM_HANDLER_ID ?= 0xbc000000 154 155# Enable reset control 156ifeq ($(CFG_STM32MP21_RSTCTRL),y) 157$(call force,CFG_DRIVERS_RSTCTRL,y) 158$(call force,CFG_STM32_RSTCTRL,y) 159endif 160ifeq ($(CFG_STM32MP25_RSTCTRL),y) 161$(call force,CFG_DRIVERS_RSTCTRL,y) 162$(call force,CFG_STM32_RSTCTRL,y) 163endif 164 165# Optional behavior upon receiving illegal access events 166CFG_STM32_PANIC_ON_IAC_EVENT ?= y 167ifeq ($(CFG_TEE_CORE_DEBUG),y) 168CFG_STM32_PANIC_ON_SERC_EVENT ?= n 169else 170CFG_STM32_PANIC_ON_SERC_EVENT ?= y 171endif 172 173# Default enable firewall support 174CFG_DRIVERS_FIREWALL ?= y 175ifeq ($(call cfg-one-enabled, CFG_STM32_RISAB CFG_STM32_RIFSC),y) 176$(call force,CFG_DRIVERS_FIREWALL,y) 177endif 178 179# Enable RTC 180ifeq ($(CFG_STM32_RTC),y) 181$(call force,CFG_DRIVERS_RTC,y) 182$(call force,CFG_RTC_PTA,y) 183endif 184 185ifeq ($(CFG_STM32_SERC),y) 186$(call force,CFG_EXTERNAL_ABORT_PLAT_HANDLER,y) 187endif 188