1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2018-2025, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <drivers/clk.h> 7 #include <drivers/clk_dt.h> 8 #include <drivers/rtc.h> 9 #include <drivers/stm32_rtc.h> 10 #include <drivers/stm32_rif.h> 11 #include <drivers/stm32_rtc.h> 12 #include <io.h> 13 #include <keep.h> 14 #include <kernel/dt.h> 15 #include <kernel/dt_driver.h> 16 #include <kernel/interrupt.h> 17 #include <kernel/notif.h> 18 #include <kernel/panic.h> 19 #include <kernel/pm.h> 20 #include <kernel/spinlock.h> 21 #include <libfdt.h> 22 #include <mm/core_memprot.h> 23 24 /* 25 * Registers 26 */ 27 #define RTC_TR U(0x00) 28 #define RTC_DR U(0x04) 29 #define RTC_SSR U(0x08) 30 #define RTC_ICSR U(0x0C) 31 #define RTC_PRER U(0x10) 32 #define RTC_WUTR U(0x14) 33 #define RTC_CR U(0x18) 34 #define RTC_PRIVCFGR U(0x1C) 35 /* RTC_SMCR is linked to RTC3v1_2 */ 36 #define RTC_SMCR U(0x20) 37 /* RTC_SECCFGR is linked to RTC3v3_2 and above */ 38 #define RTC_SECCFGR U(0x20) 39 #define RTC_WPR U(0x24) 40 #define RTC_CALR U(0x28) 41 #define RTC_SHIFTR U(0x2C) 42 #define RTC_TSTR U(0x30) 43 #define RTC_TSDR U(0x34) 44 #define RTC_TSSSR U(0x38) 45 #define RTC_ALRMAR U(0x40) 46 #define RTC_ALRMASSR U(0x44) 47 #define RTC_ALRMBR U(0x48) 48 #define RTC_ALRMBSSR U(0x4C) 49 #define RTC_SR U(0x50) 50 #define RTC_SCR U(0x5C) 51 #define RTC_OR U(0x60) 52 #define RTC_CIDCFGR(x) (U(0x80) + U(0x4) * (x)) 53 54 #define RTC_TR_SU_MASK GENMASK_32(3, 0) 55 #define RTC_TR_ST_MASK GENMASK_32(6, 4) 56 #define RTC_TR_ST_SHIFT U(4) 57 #define RTC_TR_MNU_MASK GENMASK_32(11, 8) 58 #define RTC_TR_MNU_SHIFT U(8) 59 #define RTC_TR_MNT_MASK GENMASK_32(14, 12) 60 #define RTC_TR_MNT_SHIFT U(12) 61 #define RTC_TR_HU_MASK GENMASK_32(19, 16) 62 #define RTC_TR_HU_SHIFT U(16) 63 #define RTC_TR_HT_MASK GENMASK_32(21, 20) 64 #define RTC_TR_HT_SHIFT U(20) 65 #define RTC_TR_PM BIT(22) 66 67 #define RTC_DR_DU_MASK GENMASK_32(3, 0) 68 #define RTC_DR_DT_MASK GENMASK_32(5, 4) 69 #define RTC_DR_DT_SHIFT U(4) 70 #define RTC_DR_MU_MASK GENMASK_32(11, 8) 71 #define RTC_DR_MU_SHIFT U(8) 72 #define RTC_DR_MT_MASK BIT(12) 73 #define RTC_DR_MT_SHIFT U(12) 74 #define RTC_DR_WDU_MASK GENMASK_32(15, 13) 75 #define RTC_DR_WDU_SHIFT U(13) 76 #define RTC_DR_YU_MASK GENMASK_32(19, 16) 77 #define RTC_DR_YU_SHIFT U(16) 78 #define RTC_DR_YT_MASK GENMASK_32(23, 20) 79 #define RTC_DR_YT_SHIFT U(20) 80 81 #define RTC_SSR_SS_MASK GENMASK_32(15, 0) 82 83 #define RTC_ICSR_RSF BIT(5) 84 #define RTC_ICSR_INITF BIT(6) 85 #define RTC_ICSR_INIT BIT(7) 86 87 #define RTC_PRER_PREDIV_S_SHIFT U(0) 88 #define RTC_PRER_PREDIV_S_MASK GENMASK_32(14, 0) 89 #define RTC_PRER_PREDIV_A_SHIFT U(16) 90 #define RTC_PRER_PREDIV_A_MASK GENMASK_32(22, 16) 91 92 #define RTC_CR_BYPSHAD BIT(5) 93 #define RTC_CR_BYPSHAD_SHIFT U(5) 94 #define RTC_CR_FMT BIT(6) 95 #define RTC_CR_ALRAE BIT(8) 96 #define RTC_CR_ALRAIE BIT(12) 97 #define RTC_CR_TAMPTS BIT(25) 98 99 #define RTC_PRIVCFGR_VALUES GENMASK_32(3, 0) 100 #define RTC_PRIVCFGR_VALUES_TO_SHIFT GENMASK_32(5, 4) 101 #define RTC_PRIVCFGR_SHIFT U(9) 102 #define RTC_PRIVCFGR_MASK (GENMASK_32(14, 13) | GENMASK_32(3, 0)) 103 #define RTC_PRIVCFGR_FULL_PRIV BIT(15) 104 105 #define RTC_SMCR_TS_DPROT BIT(3) 106 107 #define RTC_SECCFGR_VALUES GENMASK_32(3, 0) 108 #define RTC_SECCFGR_TS_SEC BIT(3) 109 #define RTC_SECCFGR_VALUES_TO_SHIFT GENMASK_32(5, 4) 110 #define RTC_SECCFGR_SHIFT U(9) 111 #define RTC_SECCFGR_MASK (GENMASK_32(14, 13) | GENMASK_32(3, 0)) 112 #define RTC_SECCFGR_FULL_SEC BIT(15) 113 114 #define RTC_WPR_KEY1 U(0xCA) 115 #define RTC_WPR_KEY2 U(0x53) 116 #define RTC_WPR_KEY_LOCK U(0xFF) 117 118 #define RTC_TSDR_MU_MASK GENMASK_32(11, 8) 119 #define RTC_TSDR_MU_SHIFT U(8) 120 #define RTC_TSDR_DT_MASK GENMASK_32(5, 4) 121 #define RTC_TSDR_DT_SHIFT U(4) 122 #define RTC_TSDR_DU_MASK GENMASK_32(3, 0) 123 #define RTC_TSDR_DU_SHIFT U(0) 124 125 #define RTC_ALRMXR_SEC_UNITS_MASK GENMASK_32(3, 0) 126 #define RTC_ALRMXR_SEC_UNITS_SHIFT U(0) 127 #define RTC_ALRMXR_SEC_TENS_MASK GENMASK_32(6, 4) 128 #define RTC_ALRMXR_SEC_TENS_SHIFT U(4) 129 #define RTC_ALRMXR_SEC_MASK BIT(7) 130 #define RTC_ALRMXR_MIN_UNITS_MASK GENMASK_32(11, 8) 131 #define RTC_ALRMXR_MIN_UNITS_SHIFT U(8) 132 #define RTC_ALRMXR_MIN_TENS_MASK GENMASK_32(14, 12) 133 #define RTC_ALRMXR_MIN_TENS_SHIFT U(12) 134 #define RTC_ALRMXR_MIN_MASK BIT(15) 135 #define RTC_ALRMXR_HOUR_UNITS_MASK GENMASK_32(19, 16) 136 #define RTC_ALRMXR_HOUR_UNITS_SHIFT U(16) 137 #define RTC_ALRMXR_HOUR_TENS_MASK GENMASK_32(21, 20) 138 #define RTC_ALRMXR_HOUR_TENS_SHIFT U(20) 139 #define RTC_ALRMXR_PM BIT(22) 140 #define RTC_ALRMXR_HOUR_MASK BIT(23) 141 #define RTC_ALRMXR_DATE_UNITS_MASK GENMASK_32(27, 24) 142 #define RTC_ALRMXR_DATE_UNITS_SHIFT U(24) 143 #define RTC_ALRMXR_DATE_TENS_MASK GENMASK_32(29, 28) 144 #define RTC_ALRMXR_DATE_TENS_SHIFT U(28) 145 146 #define RTC_SR_ALRAF BIT(0) 147 #define RTC_SR_TSF BIT(3) 148 #define RTC_SR_TSOVF BIT(4) 149 150 #define RTC_SCR_CALRAF BIT(0) 151 #define RTC_SCR_CTSF BIT(3) 152 #define RTC_SCR_CTSOVF BIT(4) 153 154 #define RTC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 155 #define RTC_CIDCFGR_SCID_MASK_SHIFT U(4) 156 #define RTC_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \ 157 RTC_CIDCFGR_SCID_MASK) 158 159 /* 160 * RIF miscellaneous 161 */ 162 #define RTC_NB_RIF_RESOURCES U(6) 163 164 #define RTC_RIF_FULL_PRIVILEGED U(0x3F) 165 #define RTC_RIF_FULL_SECURED U(0x3F) 166 167 #define RTC_NB_MAX_CID_SUPPORTED U(7) 168 169 /* 170 * Driver miscellaneous 171 */ 172 #define RTC_RES_TIMESTAMP U(3) 173 #define RTC_RES_CALIBRATION U(4) 174 #define RTC_RES_INITIALIZATION U(5) 175 176 #define RTC_FLAGS_READ_TWICE BIT(0) 177 178 #define TIMEOUT_US_RTC_SHADOW U(10000) 179 #define TIMEOUT_US_RTC_GENERIC U(100000) 180 181 #define YEAR_REF ULL(2000) 182 #define YEAR_MAX (YEAR_REF + ULL(99)) 183 184 struct rtc_compat { 185 bool has_seccfgr; 186 bool has_rif_support; 187 }; 188 189 /* 190 * struct rtc_device - RTC device data 191 * @base: RTC IOMEM base address 192 * @compat: RTC compatible data 193 * @pclk: RTC bus clock 194 * @rtc_ck: RTC kernel clock 195 * @conf_data: RTC RIF configuration data, when supported 196 * @nb_res: Number of protectible RTC resources 197 * @ts_lock: Lock used for time stamping events handling 198 * @flags: RTC driver flags 199 * @is_secured: True if the RTC is fully secured 200 * @itr_chip: Interrupt chip 201 * @itr_num: Interrupt number 202 * @itr_handler: Interrupt handler 203 * @notif_id: Notification ID 204 * @wait_alarm_return_status: Status of the wait alarm thread 205 * @rtc: information for OP-TEE RTC device 206 */ 207 struct rtc_device { 208 struct io_pa_va base; 209 const struct rtc_compat *compat; 210 struct clk *pclk; 211 struct clk *rtc_ck; 212 struct rif_conf_data *conf_data; 213 unsigned int nb_res; 214 unsigned int ts_lock; 215 uint8_t flags; 216 bool is_secured; 217 struct itr_chip *itr_chip; 218 size_t itr_num; 219 struct itr_handler *itr_handler; 220 uint32_t notif_id; 221 enum rtc_wait_alarm_status wait_alarm_return_status; 222 struct rtc *rtc; 223 }; 224 225 /* Expect a single RTC instance */ 226 static struct rtc_device rtc_dev; 227 228 static vaddr_t get_base(void) 229 { 230 assert(rtc_dev.base.pa); 231 232 return io_pa_or_va(&rtc_dev.base, 1); 233 } 234 235 static void stm32_rtc_write_unprotect(void) 236 { 237 vaddr_t rtc_base = get_base(); 238 239 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY1); 240 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY2); 241 } 242 243 static void stm32_rtc_write_protect(void) 244 { 245 vaddr_t rtc_base = get_base(); 246 247 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY_LOCK); 248 } 249 250 static bool stm32_rtc_get_bypshad(void) 251 { 252 return io_read32(get_base() + RTC_CR) & RTC_CR_BYPSHAD; 253 } 254 255 /* Get the subsecond value. */ 256 static uint32_t stm32_rtc_get_subsecond(uint32_t ssr) 257 { 258 uint32_t prediv_s = io_read32(get_base() + RTC_PRER) & 259 RTC_PRER_PREDIV_S_MASK; 260 261 return prediv_s - ssr; 262 } 263 264 /* 265 * Get the subsecond scale. 266 * 267 * Number of subseconds in a second is linked to RTC PREDIV_S value. 268 * The higher PREDIV_S is, the more subsecond is precise. 269 */ 270 static uint32_t stm32_rtc_get_subsecond_scale(void) 271 { 272 return (io_read32(get_base() + RTC_PRER) & RTC_PRER_PREDIV_S_MASK) + 1; 273 } 274 275 static bool cid1_has_access(unsigned int resource) 276 { 277 uint32_t cidcfgr = io_read32(get_base() + RTC_CIDCFGR(resource)); 278 279 return !(cidcfgr & _CIDCFGR_CFEN) || 280 get_field_u32(cidcfgr, RTC_CIDCFGR_SCID_MASK) == RIF_CID1; 281 } 282 283 static TEE_Result check_rif_config(void) 284 { 285 if (!cid1_has_access(RTC_RES_TIMESTAMP) || 286 !cid1_has_access(RTC_RES_CALIBRATION) || 287 !cid1_has_access(RTC_RES_INITIALIZATION)) 288 return TEE_ERROR_ACCESS_DENIED; 289 290 return TEE_SUCCESS; 291 } 292 293 static void apply_rif_config(bool is_tdcid) 294 { 295 vaddr_t base = get_base(); 296 unsigned int shifted_values = 0; 297 uint32_t seccfgr = 0; 298 uint32_t privcfgr = 0; 299 uint32_t access_mask_reg = 0; 300 unsigned int i = 0; 301 302 if (!rtc_dev.conf_data) 303 return; 304 305 /* Build access mask for RTC_SECCFGR and RTC_PRIVCFGR */ 306 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 307 if (rtc_dev.conf_data->access_mask[0] & BIT(i)) { 308 if (i <= RTC_RES_TIMESTAMP) 309 access_mask_reg |= BIT(i); 310 else 311 access_mask_reg |= BIT(i) << RTC_SECCFGR_SHIFT; 312 } 313 } 314 315 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 316 if (!(BIT(i) & rtc_dev.conf_data->access_mask[0])) 317 continue; 318 319 /* 320 * When TDCID, OP-TEE should be the one to set the CID filtering 321 * configuration. Clearing previous configuration prevents 322 * undesired events during the only legitimate configuration. 323 */ 324 if (is_tdcid) 325 io_clrbits32(base + RTC_CIDCFGR(i), 326 RTC_CIDCFGR_CONF_MASK); 327 } 328 329 /* Security RIF configuration */ 330 seccfgr = rtc_dev.conf_data->sec_conf[0]; 331 332 /* Check if all resources must be secured */ 333 if (seccfgr == RTC_RIF_FULL_SECURED) { 334 io_setbits32(base + RTC_SECCFGR, RTC_SECCFGR_FULL_SEC); 335 rtc_dev.is_secured = true; 336 337 if (!(io_read32(base + RTC_SECCFGR) & RTC_SECCFGR_FULL_SEC)) 338 panic("Bad RTC seccfgr configuration"); 339 } 340 341 /* Shift some values to align with the register */ 342 shifted_values = SHIFT_U32(seccfgr & RTC_SECCFGR_VALUES_TO_SHIFT, 343 RTC_SECCFGR_SHIFT); 344 seccfgr = (seccfgr & RTC_SECCFGR_VALUES) + shifted_values; 345 346 io_clrsetbits32(base + RTC_SECCFGR, 347 RTC_SECCFGR_MASK & access_mask_reg, seccfgr); 348 349 /* Privilege RIF configuration */ 350 privcfgr = rtc_dev.conf_data->priv_conf[0]; 351 352 /* Check if all resources must be privileged */ 353 if (privcfgr == RTC_RIF_FULL_PRIVILEGED) { 354 io_setbits32(base + RTC_PRIVCFGR, RTC_PRIVCFGR_FULL_PRIV); 355 356 if (!(io_read32(base + RTC_PRIVCFGR) & RTC_PRIVCFGR_FULL_PRIV)) 357 panic("Bad RTC privcfgr configuration"); 358 } 359 360 /* Shift some values to align with the register */ 361 shifted_values = SHIFT_U32(privcfgr & RTC_PRIVCFGR_VALUES_TO_SHIFT, 362 RTC_PRIVCFGR_SHIFT); 363 privcfgr = (privcfgr & RTC_PRIVCFGR_VALUES) + shifted_values; 364 365 io_clrsetbits32(base + RTC_PRIVCFGR, 366 RTC_PRIVCFGR_MASK & access_mask_reg, privcfgr); 367 368 if (!is_tdcid) 369 return; 370 371 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 372 if (!(BIT(i) & rtc_dev.conf_data->access_mask[0])) 373 continue; 374 /* 375 * When at least one resource has CID filtering enabled, 376 * the RTC_PRIVCFGR_FULL_PRIV and RTC_SECCFGR_FULL_SEC bits are 377 * cleared. 378 */ 379 io_clrsetbits32(base + RTC_CIDCFGR(i), 380 RTC_CIDCFGR_CONF_MASK, 381 rtc_dev.conf_data->cid_confs[i]); 382 } 383 } 384 385 static void stm32_rtc_clear_events(uint32_t flags) 386 { 387 io_write32(get_base() + RTC_SCR, flags); 388 } 389 390 static enum itr_return stm32_rtc_it_handler(struct itr_handler *h __unused) 391 { 392 vaddr_t rtc_base = get_base(); 393 uint32_t status = io_read32(rtc_base + RTC_SR); 394 uint32_t cr = io_read32(rtc_base + RTC_CR); 395 396 if ((status & RTC_SR_ALRAF) && (cr & RTC_CR_ALRAIE)) { 397 DMSG("Alarm occurred"); 398 /* Clear event's flags */ 399 stm32_rtc_clear_events(RTC_SCR_CALRAF); 400 /* 401 * Notify the caller of 'stm32_rtc_wait_alarm' to re-schedule 402 * the calling thread. 403 */ 404 notif_send_async(rtc_dev.notif_id, 0); 405 } 406 407 return ITRR_HANDLED; 408 } 409 DECLARE_KEEP_PAGER(stm32_rtc_it_handler); 410 411 static TEE_Result parse_dt(const void *fdt, int node) 412 { 413 TEE_Result res = TEE_ERROR_GENERIC; 414 const fdt32_t *cuint = NULL; 415 size_t reg_size = 0; 416 unsigned int i = 0; 417 int lenp = 0; 418 419 if (fdt_reg_info(fdt, node, &rtc_dev.base.pa, ®_size)) 420 panic(); 421 422 io_pa_or_va(&rtc_dev.base, reg_size); 423 assert(rtc_dev.base.va); 424 425 res = clk_dt_get_by_name(fdt, node, "pclk", &rtc_dev.pclk); 426 if (res) 427 return res; 428 429 res = clk_dt_get_by_name(fdt, node, "rtc_ck", &rtc_dev.rtc_ck); 430 if (res) 431 return res; 432 433 res = interrupt_dt_get(fdt, node, &rtc_dev.itr_chip, 434 &rtc_dev.itr_num); 435 if (res != TEE_SUCCESS && res != TEE_ERROR_ITEM_NOT_FOUND) 436 return res; 437 438 if (fdt_getprop(fdt, node, "wakeup-source", NULL)) { 439 if (res != TEE_ERROR_ITEM_NOT_FOUND && 440 interrupt_can_set_wake(rtc_dev.itr_chip)) 441 rtc_dev.rtc->is_wakeup_source = true; 442 else 443 DMSG("RTC wakeup source ignored"); 444 } 445 446 if (!rtc_dev.compat->has_rif_support) 447 return TEE_SUCCESS; 448 449 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 450 if (!cuint) { 451 DMSG("No RIF configuration available"); 452 return TEE_SUCCESS; 453 } 454 455 rtc_dev.conf_data = calloc(1, sizeof(*rtc_dev.conf_data)); 456 if (!rtc_dev.conf_data) 457 panic(); 458 459 rtc_dev.nb_res = (unsigned int)(lenp / sizeof(uint32_t)); 460 assert(rtc_dev.nb_res <= RTC_NB_RIF_RESOURCES); 461 462 rtc_dev.conf_data->cid_confs = calloc(RTC_NB_RIF_RESOURCES, 463 sizeof(uint32_t)); 464 rtc_dev.conf_data->sec_conf = calloc(1, sizeof(uint32_t)); 465 rtc_dev.conf_data->priv_conf = calloc(1, sizeof(uint32_t)); 466 rtc_dev.conf_data->access_mask = calloc(1, sizeof(uint32_t)); 467 if (!rtc_dev.conf_data->cid_confs || !rtc_dev.conf_data->sec_conf || 468 !rtc_dev.conf_data->priv_conf || !rtc_dev.conf_data->access_mask) 469 panic("Not enough memory capacity for RTC RIF config"); 470 471 for (i = 0; i < rtc_dev.nb_res; i++) 472 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), rtc_dev.conf_data, 473 RTC_NB_RIF_RESOURCES); 474 475 return TEE_SUCCESS; 476 } 477 478 static TEE_Result stm32_rtc_enter_init_mode(void) 479 { 480 vaddr_t base = get_base(); 481 uint32_t icsr = io_read32(base + RTC_ICSR); 482 uint32_t value = 0; 483 484 if (!(icsr & RTC_ICSR_INITF)) { 485 icsr |= RTC_ICSR_INIT; 486 io_write32(base + RTC_ICSR, icsr); 487 488 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, value, 489 value & RTC_ICSR_INITF, 490 10, TIMEOUT_US_RTC_GENERIC)) 491 return TEE_ERROR_BUSY; 492 } 493 494 return TEE_SUCCESS; 495 } 496 497 static TEE_Result stm32_rtc_exit_init_mode(void) 498 { 499 vaddr_t base = get_base(); 500 uint32_t value = 0; 501 502 io_clrbits32(base + RTC_ICSR, RTC_ICSR_INIT); 503 dsb(); 504 505 io_clrbits32(base + RTC_ICSR, RTC_ICSR_RSF); 506 507 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, value, 508 value & RTC_ICSR_RSF, 10, 509 TIMEOUT_US_RTC_GENERIC)) 510 return TEE_ERROR_BUSY; 511 512 return TEE_SUCCESS; 513 } 514 515 static void stm32_rtc_to_tm(uint32_t ssr, uint32_t tr, uint32_t dr, 516 struct optee_rtc_time *tm) 517 { 518 tm->tm_hour = ((tr & RTC_TR_HT_MASK) >> RTC_TR_HT_SHIFT) * 10 + 519 ((tr & RTC_TR_HU_MASK) >> RTC_TR_HU_SHIFT); 520 521 if (tr & RTC_TR_PM) 522 tm->tm_hour += 12; 523 524 tm->tm_ms = (stm32_rtc_get_subsecond(ssr) * MS_PER_SEC) / 525 stm32_rtc_get_subsecond_scale(); 526 527 tm->tm_sec = ((tr & RTC_TR_ST_MASK) >> RTC_TR_ST_SHIFT) * 10 + 528 (tr & RTC_TR_SU_MASK); 529 530 tm->tm_min = ((tr & RTC_TR_MNT_MASK) >> RTC_TR_MNT_SHIFT) * 10 + 531 ((tr & RTC_TR_MNU_MASK) >> RTC_TR_MNU_SHIFT); 532 533 tm->tm_wday = ((dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT) % 7; 534 535 tm->tm_mday = ((dr & RTC_DR_DT_MASK) >> RTC_DR_DT_SHIFT) * 10 + 536 (dr & RTC_DR_DU_MASK); 537 538 tm->tm_mon = ((dr & RTC_DR_MT_MASK) >> RTC_DR_MT_SHIFT) * 10 + 539 ((dr & RTC_DR_MU_MASK) >> RTC_DR_MU_SHIFT) - 1; 540 541 tm->tm_year = ((dr & RTC_DR_YT_MASK) >> RTC_DR_YT_SHIFT) * 10 + 542 ((dr & RTC_DR_YU_MASK) >> RTC_DR_YU_SHIFT) + YEAR_REF; 543 } 544 545 static TEE_Result stm32_rtc_init(void) 546 { 547 uint32_t pred_a_max = RTC_PRER_PREDIV_A_MASK >> RTC_PRER_PREDIV_A_SHIFT; 548 uint32_t pred_s_max = RTC_PRER_PREDIV_S_MASK >> RTC_PRER_PREDIV_S_SHIFT; 549 unsigned long rate = clk_get_rate(rtc_dev.rtc_ck); 550 TEE_Result res = TEE_ERROR_GENERIC; 551 vaddr_t base = get_base(); 552 uint32_t pred_a = 0; 553 uint32_t pred_s = 0; 554 uint32_t prer = io_read32(base + RTC_PRER); 555 uint32_t cr = io_read32(base + RTC_CR); 556 557 if (rate > (pred_a_max + 1) * (pred_s_max + 1)) 558 panic("rtc_ck rate is too high"); 559 560 if (cr & RTC_CR_FMT && !IS_ENABLED(CFG_STM32_RTC_HIGH_ACCURACY)) 561 return TEE_SUCCESS; 562 563 if (IS_ENABLED(CFG_STM32_RTC_HIGH_ACCURACY)) { 564 /* 565 * Compute the prescaler values whom divides the clock in order 566 * to get a * 1 Hz output by maximizing accuracy 567 * (maximizing PREDIV_S). 568 */ 569 for (pred_a = 0; pred_a <= pred_a_max; pred_a++) { 570 pred_s = (rate / (pred_a + 1)) - 1; 571 if (pred_s <= pred_s_max && 572 ((pred_s + 1) * (pred_a + 1)) == rate) 573 break; 574 } 575 576 /* 577 * 1 Hz output not possible, give priority to RTC power 578 * consumption by choosing the higher possible value for 579 * prediv_a 580 */ 581 if (pred_s > pred_s_max || pred_a > pred_a_max) { 582 pred_a = pred_a_max; 583 pred_s = (rate / (pred_a + 1)) - 1; 584 585 DMSG("rtc_ck is %s", 586 (rate < ((pred_a + 1) * (pred_s + 1))) ? 587 "fast" : "slow"); 588 } 589 590 prer &= RTC_PRER_PREDIV_S_MASK | RTC_PRER_PREDIV_A_MASK; 591 pred_s = SHIFT_U32(pred_s, RTC_PRER_PREDIV_S_SHIFT) & 592 RTC_PRER_PREDIV_S_MASK; 593 pred_a = SHIFT_U32(pred_a, RTC_PRER_PREDIV_A_SHIFT) & 594 RTC_PRER_PREDIV_A_MASK; 595 596 /* Return if there is nothing to initialize */ 597 if (cr & RTC_CR_FMT && prer == (pred_s | pred_a)) 598 return TEE_SUCCESS; 599 } 600 601 stm32_rtc_write_unprotect(); 602 603 res = stm32_rtc_enter_init_mode(); 604 if (res) { 605 EMSG("Can't enter init mode. Fail to initialize RTC."); 606 stm32_rtc_write_protect(); 607 return res; 608 } 609 610 if (IS_ENABLED(CFG_STM32_RTC_HIGH_ACCURACY)) { 611 io_write32(base + RTC_PRER, pred_s); 612 io_write32(base + RTC_PRER, pred_a | pred_s); 613 } 614 615 /* Force 24h time format */ 616 cr &= ~RTC_CR_FMT; 617 io_write32(base + RTC_CR, cr); 618 619 res = stm32_rtc_exit_init_mode(); 620 if (res) 621 EMSG("Can't exit init mode. Fail to initialize RTC."); 622 623 stm32_rtc_write_protect(); 624 625 return res; 626 } 627 628 static TEE_Result stm32_rtc_get_time(struct rtc *rtc __unused, 629 struct optee_rtc_time *tm) 630 { 631 vaddr_t base = get_base(); 632 uint32_t ssr = 0; 633 uint32_t dr = 0; 634 uint32_t tr = 0; 635 636 if (!stm32_rtc_get_bypshad()) { 637 uint32_t icsr = 0; 638 639 /* Wait calendar registers are ready */ 640 io_clrbits32(base + RTC_ICSR, RTC_ICSR_RSF); 641 642 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, icsr, 643 icsr & RTC_ICSR_RSF, 0, 644 TIMEOUT_US_RTC_SHADOW)) 645 panic(); 646 } 647 648 /* 649 * In our RTC we start : 650 * - year at 0 651 * - month at 1 652 * - day at 1 653 * - weekday at Monday = 1 654 * Change month value so it becomes 0=January, 1 = February, ... 655 * Change week day value so it becomes 0=Sunday, 1 = Monday, ... 656 */ 657 658 ssr = io_read32(base + RTC_SSR); 659 tr = io_read32(base + RTC_TR); 660 dr = io_read32(base + RTC_DR); 661 662 stm32_rtc_to_tm(ssr, tr, dr, tm); 663 664 return TEE_SUCCESS; 665 } 666 667 static TEE_Result stm32_rtc_set_time(struct rtc *rtc, struct optee_rtc_time *tm) 668 { 669 TEE_Result res = TEE_ERROR_GENERIC; 670 vaddr_t rtc_base = get_base(); 671 uint32_t tr = 0; 672 uint32_t dr = 0; 673 674 /* 675 * In our RTC we start : 676 * - year at 0 677 * - month at 1 678 * - day at 1 679 * - weekday at Monday = 1 680 * Change month value so it becomes 1=January, 2 = February, ... 681 * Change week day value so it becomes 7=Sunday, 1 = Monday, ... 682 */ 683 tr = ((tm->tm_sec % 10) & RTC_TR_SU_MASK) | 684 (SHIFT_U32(tm->tm_sec / 10, RTC_TR_ST_SHIFT) & RTC_TR_ST_MASK) | 685 (SHIFT_U32(tm->tm_min % 10, RTC_TR_MNU_SHIFT) & RTC_TR_MNU_MASK) | 686 (SHIFT_U32(tm->tm_min / 10, RTC_TR_MNT_SHIFT) & RTC_TR_MNT_MASK) | 687 (SHIFT_U32(tm->tm_hour % 10, RTC_TR_HU_SHIFT) & RTC_TR_HU_MASK) | 688 (SHIFT_U32(tm->tm_hour / 10, RTC_TR_HT_SHIFT) & RTC_TR_HT_MASK); 689 690 dr = ((tm->tm_mday % 10) & RTC_DR_DU_MASK) | 691 (SHIFT_U32(tm->tm_mday / 10, RTC_DR_DT_SHIFT) & RTC_DR_DT_MASK) | 692 (SHIFT_U32((tm->tm_mon + 1) % 10, RTC_DR_MU_SHIFT) & 693 RTC_DR_MU_MASK) | 694 (SHIFT_U32((tm->tm_mon + 1) / 10, RTC_DR_MT_SHIFT) & 695 RTC_DR_MT_MASK) | 696 (SHIFT_U32(tm->tm_wday ? tm->tm_wday : 7, RTC_DR_WDU_SHIFT) & 697 RTC_DR_WDU_MASK) | 698 (SHIFT_U32((tm->tm_year - rtc->range_min.tm_year) % 10, 699 RTC_DR_YU_SHIFT) & RTC_DR_YU_MASK) | 700 (SHIFT_U32((tm->tm_year - rtc->range_min.tm_year) / 10, 701 RTC_DR_YT_SHIFT) & RTC_DR_YT_MASK); 702 703 stm32_rtc_write_unprotect(); 704 705 res = stm32_rtc_enter_init_mode(); 706 if (res) 707 goto end; 708 709 io_write32(rtc_base + RTC_TR, tr); 710 io_write32(rtc_base + RTC_DR, dr); 711 712 res = stm32_rtc_exit_init_mode(); 713 end: 714 stm32_rtc_write_protect(); 715 716 return res; 717 } 718 719 TEE_Result stm32_rtc_get_timestamp(struct optee_rtc_time *tm) 720 { 721 vaddr_t base = get_base(); 722 uint32_t exceptions = 0; 723 uint32_t value = 0; 724 uint32_t ssr = 0; 725 uint32_t dr = 0; 726 uint32_t tr = 0; 727 728 exceptions = cpu_spin_lock_xsave(&rtc_dev.ts_lock); 729 730 if (IO_READ32_POLL_TIMEOUT(base + RTC_SR, value, 731 value & RTC_SR_TSF, 732 10, TIMEOUT_US_RTC_GENERIC)) { 733 cpu_spin_unlock_xrestore(&rtc_dev.ts_lock, exceptions); 734 return TEE_ERROR_NO_DATA; 735 } 736 737 ssr = io_read32(base + RTC_TSSSR); 738 tr = io_read32(base + RTC_TSTR); 739 dr = io_read32(base + RTC_TSDR); 740 741 io_setbits32(base + RTC_SCR, RTC_SCR_CTSF); 742 743 /* Tamper event overflow detection */ 744 if (io_read32(base + RTC_SR) & RTC_SR_TSOVF) { 745 io_setbits32(base + RTC_SCR, RTC_SCR_CTSOVF); 746 DMSG("A timestamp event occurred while handling current event"); 747 } 748 749 cpu_spin_unlock_xrestore(&rtc_dev.ts_lock, exceptions); 750 751 stm32_rtc_to_tm(ssr, tr, dr, tm); 752 753 /* No year timestamp available */ 754 tm->tm_year = 0; 755 756 return TEE_SUCCESS; 757 } 758 759 TEE_Result stm32_rtc_set_tamper_timestamp(void) 760 { 761 vaddr_t base = get_base(); 762 763 stm32_rtc_write_unprotect(); 764 765 /* Secure Timestamp bit */ 766 if (!rtc_dev.compat->has_seccfgr) { 767 /* Inverted logic */ 768 io_clrbits32(base + RTC_SMCR, RTC_SMCR_TS_DPROT); 769 } else { 770 io_setbits32(base + RTC_SECCFGR, RTC_SECCFGR_TS_SEC); 771 } 772 773 /* Enable tamper timestamper */ 774 io_setbits32(base + RTC_CR, RTC_CR_TAMPTS); 775 776 stm32_rtc_write_protect(); 777 778 return TEE_SUCCESS; 779 } 780 781 TEE_Result stm32_rtc_is_timestamp_enabled(bool *ret) 782 { 783 *ret = io_read32(get_base() + RTC_CR) & RTC_CR_TAMPTS; 784 785 return TEE_SUCCESS; 786 } 787 788 TEE_Result stm32_rtc_driver_is_initialized(void) 789 { 790 if (rtc_dev.pclk) 791 return TEE_SUCCESS; 792 793 return TEE_ERROR_DEFER_DRIVER_INIT; 794 } 795 796 static TEE_Result stm32_rtc_read_alarm(struct rtc *rtc, 797 struct optee_rtc_alarm *alarm) 798 { 799 struct optee_rtc_time *alarm_tm = NULL; 800 struct optee_rtc_time current_tm = { }; 801 TEE_Result res = TEE_ERROR_GENERIC; 802 vaddr_t rtc_base = get_base(); 803 uint32_t alrmar = io_read32(rtc_base + RTC_ALRMAR); 804 uint32_t cr = io_read32(rtc_base + RTC_CR); 805 uint32_t status = io_read32(rtc_base + RTC_SR); 806 807 alarm_tm = &alarm->time; 808 809 res = stm32_rtc_get_time(rtc, ¤t_tm); 810 if (res) 811 return res; 812 813 alarm_tm->tm_year = current_tm.tm_year; 814 alarm_tm->tm_mon = current_tm.tm_mon; 815 alarm_tm->tm_mday = ((alrmar & RTC_ALRMXR_DATE_UNITS_MASK) >> 816 RTC_ALRMXR_DATE_UNITS_SHIFT) + 817 ((alrmar & RTC_ALRMXR_DATE_TENS_MASK) >> 818 RTC_ALRMXR_DATE_TENS_SHIFT) * 10; 819 alarm_tm->tm_hour = ((alrmar & RTC_ALRMXR_HOUR_UNITS_MASK) >> 820 RTC_ALRMXR_HOUR_UNITS_SHIFT) + 821 ((alrmar & RTC_ALRMXR_HOUR_TENS_MASK) >> 822 RTC_ALRMXR_HOUR_TENS_SHIFT) * 10; 823 alarm_tm->tm_min = ((alrmar & RTC_ALRMXR_MIN_UNITS_MASK) >> 824 RTC_ALRMXR_MIN_UNITS_SHIFT) + 825 ((alrmar & RTC_ALRMXR_MIN_TENS_MASK) >> 826 RTC_ALRMXR_MIN_TENS_SHIFT) * 10; 827 alarm_tm->tm_sec = ((alrmar & RTC_ALRMXR_MIN_UNITS_MASK) >> 828 RTC_ALRMXR_MIN_UNITS_SHIFT) + 829 ((alrmar & RTC_ALRMXR_MIN_TENS_MASK) >> 830 RTC_ALRMXR_MIN_TENS_SHIFT) * 10; 831 832 if (rtc_timecmp(alarm_tm, ¤t_tm) < 0) { 833 if (current_tm.tm_mon == 11) { 834 alarm_tm->tm_mon = 0; 835 alarm_tm->tm_year += 1; 836 } else { 837 alarm_tm->tm_mon += 1; 838 } 839 } 840 841 alarm->enabled = cr & RTC_CR_ALRAE; 842 alarm->pending = status & RTC_SR_ALRAF; 843 844 return TEE_SUCCESS; 845 } 846 847 static TEE_Result stm32_rtc_enable_alarm(struct rtc *rtc __unused, bool enabled) 848 { 849 vaddr_t rtc_base = get_base(); 850 851 stm32_rtc_write_unprotect(); 852 853 if (enabled) 854 io_setbits32(rtc_base + RTC_CR, RTC_CR_ALRAIE | RTC_CR_ALRAE); 855 else 856 io_clrbits32(rtc_base + RTC_CR, RTC_CR_ALRAIE | RTC_CR_ALRAE); 857 858 stm32_rtc_clear_events(RTC_SCR_CALRAF); 859 860 stm32_rtc_write_protect(); 861 862 return TEE_SUCCESS; 863 } 864 865 static void stm32_rtc_add_one_month(struct optee_rtc_time *tm) 866 { 867 tm->tm_mon++; 868 if (tm->tm_mon > 11) { 869 tm->tm_mon = 0; 870 tm->tm_year++; 871 } 872 873 /* Saturate to the next month last day */ 874 tm->tm_mday = MIN(tm->tm_mday, 875 rtc_get_month_days(tm->tm_mon, tm->tm_year)); 876 } 877 878 static TEE_Result stm32_rtc_valid_alarm_time(struct rtc *rtc, 879 struct optee_rtc_time *tm) 880 { 881 struct optee_rtc_time current_tm = { }; 882 TEE_Result res = TEE_ERROR_GENERIC; 883 struct optee_rtc_time *max = NULL; 884 885 /* 886 * Assuming current date is M-D-Y H:M:S. 887 * RTC alarm can't be set on a specific month and year. 888 * So the valid alarm range is: 889 * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S 890 */ 891 892 res = stm32_rtc_get_time(rtc, ¤t_tm); 893 if (res) 894 return res; 895 896 /* Don't allow alarm to be set in the past. */ 897 if (rtc_timecmp(¤t_tm, tm) >= 0) 898 return TEE_ERROR_BAD_PARAMETERS; 899 900 max = ¤t_tm; 901 902 stm32_rtc_add_one_month(max); 903 904 if (rtc_timecmp(max, tm) <= 0) 905 return TEE_ERROR_BAD_PARAMETERS; 906 907 return TEE_SUCCESS; 908 } 909 910 static TEE_Result stm32_rtc_set_alarm(struct rtc *rtc, 911 struct optee_rtc_alarm *alarm) 912 { 913 struct optee_rtc_time *alarm_time = &alarm->time; 914 TEE_Result res = TEE_ERROR_GENERIC; 915 vaddr_t rtc_base = get_base(); 916 uint32_t alrmar = 0; 917 uint32_t cr = io_read32(rtc_base + RTC_CR); 918 uint32_t prer = io_read32(rtc_base + RTC_PRER); 919 uint32_t prediv_s = prer & RTC_PRER_PREDIV_S_MASK; 920 921 /* tm_year and tm_mon are not used because not supported by RTC */ 922 alrmar |= ((alarm_time->tm_mday / 10) << RTC_ALRMXR_DATE_TENS_SHIFT) & 923 RTC_ALRMXR_DATE_TENS_MASK; 924 alrmar |= ((alarm_time->tm_mday % 10) << RTC_ALRMXR_DATE_UNITS_SHIFT) & 925 RTC_ALRMXR_DATE_UNITS_MASK; 926 /* 24-hour format */ 927 alrmar &= ~RTC_ALRMXR_PM; 928 alrmar |= ((alarm_time->tm_hour / 10) << RTC_ALRMXR_HOUR_TENS_SHIFT) & 929 RTC_ALRMXR_HOUR_TENS_MASK; 930 alrmar |= ((alarm_time->tm_hour % 10) << RTC_ALRMXR_HOUR_UNITS_SHIFT) & 931 RTC_ALRMXR_HOUR_UNITS_MASK; 932 alrmar |= ((alarm_time->tm_min / 10) << RTC_ALRMXR_MIN_TENS_SHIFT) & 933 RTC_ALRMXR_MIN_TENS_MASK; 934 alrmar |= ((alarm_time->tm_min % 10) << RTC_ALRMXR_MIN_UNITS_SHIFT) & 935 RTC_ALRMXR_MIN_UNITS_MASK; 936 alrmar |= ((alarm_time->tm_sec / 10) << RTC_ALRMXR_SEC_TENS_SHIFT) & 937 RTC_ALRMXR_SEC_TENS_MASK; 938 alrmar |= ((alarm_time->tm_sec % 10) << RTC_ALRMXR_SEC_UNITS_SHIFT) & 939 RTC_ALRMXR_SEC_UNITS_MASK; 940 941 if ((alrmar & !RTC_ALRMXR_SEC_MASK) && prediv_s < 3) { 942 EMSG("RTC Alarm conditions not met"); 943 return TEE_ERROR_BAD_STATE; 944 } 945 946 stm32_rtc_write_unprotect(); 947 948 res = stm32_rtc_valid_alarm_time(rtc, alarm_time); 949 if (res) { 950 stm32_rtc_write_unprotect(); 951 return res; 952 } 953 954 /* Disable Alarm */ 955 cr &= ~RTC_CR_ALRAE; 956 io_write32(rtc_base + RTC_CR, cr); 957 958 io_write32(rtc_base + RTC_ALRMAR, alrmar); 959 960 stm32_rtc_enable_alarm(rtc, alarm->enabled); 961 962 stm32_rtc_write_protect(); 963 964 return TEE_SUCCESS; 965 } 966 967 static TEE_Result stm32_rtc_cancel_wait_alarm(struct rtc *rtc __unused) 968 { 969 rtc_dev.wait_alarm_return_status = RTC_WAIT_ALARM_CANCELED; 970 notif_send_async(rtc_dev.notif_id, 0); 971 972 return TEE_SUCCESS; 973 } 974 975 static TEE_Result 976 stm32_rtc_wait_alarm(struct rtc *rtc __unused, 977 enum rtc_wait_alarm_status *return_status) 978 { 979 TEE_Result res = TEE_ERROR_GENERIC; 980 981 rtc_dev.wait_alarm_return_status = RTC_WAIT_ALARM_RESET; 982 983 /* Wait until a notification arrives - blocking */ 984 res = notif_wait(rtc_dev.notif_id); 985 if (res) 986 return res; 987 988 if (rtc_dev.wait_alarm_return_status == 989 RTC_WAIT_ALARM_CANCELED) { 990 *return_status = RTC_WAIT_ALARM_CANCELED; 991 stm32_rtc_enable_alarm(rtc, 0); 992 } else { 993 *return_status = RTC_WAIT_ALARM_ALARM_OCCURRED; 994 } 995 996 return TEE_SUCCESS; 997 } 998 999 static TEE_Result stm32_rtc_set_alarm_wakeup_status(struct rtc *rtc __unused, 1000 bool status) 1001 { 1002 if (!rtc_dev.rtc->is_wakeup_source) 1003 return TEE_ERROR_NOT_SUPPORTED; 1004 1005 interrupt_set_wake(rtc_dev.itr_chip, rtc_dev.itr_num, status); 1006 1007 return TEE_SUCCESS; 1008 } 1009 1010 static const struct rtc_ops stm32_rtc_ops = { 1011 .get_time = stm32_rtc_get_time, 1012 .set_time = stm32_rtc_set_time, 1013 .read_alarm = stm32_rtc_read_alarm, 1014 .set_alarm = stm32_rtc_set_alarm, 1015 .enable_alarm = stm32_rtc_enable_alarm, 1016 .wait_alarm = stm32_rtc_wait_alarm, 1017 .cancel_wait = stm32_rtc_cancel_wait_alarm, 1018 .set_alarm_wakeup_status = stm32_rtc_set_alarm_wakeup_status, 1019 }; 1020 1021 static struct rtc stm32_rtc = { 1022 .ops = &stm32_rtc_ops, 1023 .range_min = RTC_TIME(YEAR_REF, 0, 1, 0, 0, 0, 0, 0), 1024 .range_max = RTC_TIME(YEAR_MAX, 11, 31, 4, 23, 59, 59, 999), 1025 }; 1026 1027 static TEE_Result stm32_rtc_probe(const void *fdt, int node, 1028 const void *compat_data) 1029 { 1030 TEE_Result res = TEE_ERROR_GENERIC; 1031 bool is_tdcid = false; 1032 1033 rtc_dev.compat = compat_data; 1034 rtc_dev.rtc = &stm32_rtc; 1035 1036 if (rtc_dev.compat->has_rif_support) { 1037 res = stm32_rifsc_check_tdcid(&is_tdcid); 1038 if (res) 1039 return res; 1040 } 1041 1042 res = parse_dt(fdt, node); 1043 if (res) { 1044 memset(&rtc_dev, 0, sizeof(rtc_dev)); 1045 return res; 1046 } 1047 1048 /* Unbalanced clock enable to ensure RTC core clock is always on */ 1049 res = clk_enable(rtc_dev.rtc_ck); 1050 if (res) 1051 panic("Couldn't enable RTC clock"); 1052 1053 if (clk_get_rate(rtc_dev.pclk) < (clk_get_rate(rtc_dev.rtc_ck) * 7)) 1054 rtc_dev.flags |= RTC_FLAGS_READ_TWICE; 1055 1056 if (rtc_dev.compat->has_rif_support) { 1057 res = clk_enable(rtc_dev.pclk); 1058 if (res) 1059 panic("Could not enable RTC bus clock"); 1060 1061 apply_rif_config(is_tdcid); 1062 1063 /* 1064 * Verify if applied RIF config will not disable 1065 * other functionalities of this driver. 1066 */ 1067 res = check_rif_config(); 1068 if (res) 1069 panic("Incompatible RTC RIF configuration"); 1070 1071 clk_disable(rtc_dev.pclk); 1072 } 1073 1074 res = stm32_rtc_init(); 1075 if (res) 1076 return res; 1077 1078 rtc_register(&stm32_rtc); 1079 1080 if (IS_ENABLED(CFG_RTC_PTA) && IS_ENABLED(CFG_CORE_ASYNC_NOTIF) && 1081 rtc_dev.is_secured && rtc_dev.itr_chip) { 1082 res = notif_alloc_async_value(&rtc_dev.notif_id); 1083 if (res) 1084 return res; 1085 1086 res = interrupt_create_handler(rtc_dev.itr_chip, 1087 rtc_dev.itr_num, 1088 stm32_rtc_it_handler, 1089 &rtc_dev, 0, 1090 &rtc_dev.itr_handler); 1091 if (res) 1092 goto out_rtc_secured_and_itr_chip; 1093 1094 /* Unbalanced clock enable to ensure IRQ interface is alive */ 1095 res = clk_enable(rtc_dev.pclk); 1096 if (res) 1097 goto out_rtc_secured_and_itr_chip; 1098 1099 interrupt_enable(rtc_dev.itr_chip, rtc_dev.itr_num); 1100 1101 return TEE_SUCCESS; 1102 1103 out_rtc_secured_and_itr_chip: 1104 interrupt_remove_handler(rtc_dev.itr_handler); 1105 notif_free_async_value(rtc_dev.notif_id); 1106 return res; 1107 } 1108 1109 return TEE_SUCCESS; 1110 } 1111 1112 static const struct rtc_compat mp25_compat = { 1113 .has_seccfgr = true, 1114 .has_rif_support = true, 1115 }; 1116 1117 static const struct rtc_compat mp15_compat = { 1118 .has_seccfgr = false, 1119 .has_rif_support = false, 1120 }; 1121 1122 static const struct rtc_compat mp13_compat = { 1123 .has_seccfgr = true, 1124 .has_rif_support = false, 1125 }; 1126 1127 static const struct dt_device_match stm32_rtc_match_table[] = { 1128 { 1129 .compatible = "st,stm32mp25-rtc", 1130 .compat_data = &mp25_compat, 1131 }, 1132 { 1133 .compatible = "st,stm32mp1-rtc", 1134 .compat_data = &mp15_compat, 1135 }, 1136 { 1137 .compatible = "st,stm32mp13-rtc", 1138 .compat_data = &mp13_compat, 1139 }, 1140 { } 1141 }; 1142 1143 DEFINE_DT_DRIVER(stm32_rtc_dt_driver) = { 1144 .name = "stm32-rtc", 1145 .match_table = stm32_rtc_match_table, 1146 .probe = stm32_rtc_probe, 1147 }; 1148