1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017-2025 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9#include <dt-bindings/firewall/stm32mp15-etzpc.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a7"; 21 clock-frequency = <650000000>; 22 device_type = "cpu"; 23 reg = <0>; 24 }; 25 }; 26 27 arm-pmu { 28 compatible = "arm,cortex-a7-pmu"; 29 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-affinity = <&cpu0>; 31 interrupt-parent = <&intc>; 32 }; 33 34 psci { 35 compatible = "arm,psci-1.0"; 36 method = "smc"; 37 }; 38 39 intc: interrupt-controller@a0021000 { 40 compatible = "arm,cortex-a7-gic"; 41 #interrupt-cells = <3>; 42 interrupt-controller; 43 reg = <0xa0021000 0x1000>, 44 <0xa0022000 0x2000>; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&intc>; 54 }; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 63 clk_hsi: clk-hsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <64000000>; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 clk_lsi: clk-lsi { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <4000000>; 85 }; 86 }; 87 88 thermal-zones { 89 cpu_thermal: cpu-thermal { 90 polling-delay-passive = <0>; 91 polling-delay = <0>; 92 thermal-sensors = <&dts>; 93 94 trips { 95 cpu_alert1: cpu-alert1 { 96 temperature = <85000>; 97 hysteresis = <0>; 98 type = "passive"; 99 }; 100 101 cpu-crit { 102 temperature = <120000>; 103 hysteresis = <0>; 104 type = "critical"; 105 }; 106 }; 107 108 cooling-maps { 109 }; 110 }; 111 }; 112 113 booster: regulator-booster { 114 compatible = "st,stm32mp1-booster"; 115 st,syscfg = <&syscfg>; 116 status = "disabled"; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges; 125 126 ipcc: mailbox@4c001000 { 127 compatible = "st,stm32mp1-ipcc"; 128 #mbox-cells = <1>; 129 reg = <0x4c001000 0x400>; 130 st,proc-id = <0>; 131 interrupts-extended = 132 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 133 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 134 <&exti 61 1>; 135 interrupt-names = "rx", "tx", "wakeup"; 136 clocks = <&rcc IPCC>; 137 wakeup-source; 138 status = "disabled"; 139 }; 140 141 rcc: rcc@50000000 { 142 compatible = "st,stm32mp1-rcc", "syscon"; 143 reg = <0x50000000 0x1000>; 144 #clock-cells = <1>; 145 #reset-cells = <1>; 146 }; 147 148 pwr_regulators: pwr@50001000 { 149 compatible = "st,stm32mp1,pwr-reg"; 150 reg = <0x50001000 0x10>; 151 152 reg11: reg11 { 153 regulator-name = "reg11"; 154 regulator-min-microvolt = <1100000>; 155 regulator-max-microvolt = <1100000>; 156 }; 157 158 reg18: reg18 { 159 regulator-name = "reg18"; 160 regulator-min-microvolt = <1800000>; 161 regulator-max-microvolt = <1800000>; 162 }; 163 164 usb33: usb33 { 165 regulator-name = "usb33"; 166 regulator-min-microvolt = <3300000>; 167 regulator-max-microvolt = <3300000>; 168 }; 169 }; 170 171 pwr_mcu: pwr_mcu@50001014 { 172 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 173 reg = <0x50001014 0x4>; 174 }; 175 176 exti: interrupt-controller@5000d000 { 177 compatible = "st,stm32mp1-exti"; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 reg = <0x5000d000 0x400>; 181 interrupts-extended = 182 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 183 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 184 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 185 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 186 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 187 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 188 <&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 189 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 190 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 191 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 192 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 193 <&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 194 <&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 195 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 196 <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 197 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 198 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 199 <0>, 200 <0>, 201 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 202 <0>, /* EXTI_20 */ 203 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 204 <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 205 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 206 <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 207 <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 208 <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 209 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 210 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 211 <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 212 <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 213 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 214 <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 215 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 216 <0>, 217 <0>, 218 <0>, 219 <0>, 220 <0>, 221 <0>, 222 <0>, /* EXTI_40 */ 223 <0>, 224 <0>, 225 <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 226 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 227 <0>, 228 <0>, 229 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 230 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 231 <0>, 232 <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 233 <0>, 234 <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 235 <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 236 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 237 <0>, 238 <0>, 239 <0>, 240 <0>, 241 <0>, 242 <0>, /* EXTI_60 */ 243 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 244 <0>, 245 <0>, 246 <0>, 247 <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 248 <0>, 249 <0>, 250 <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 251 <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 252 <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 253 <0>, 254 <0>, 255 <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 256 }; 257 258 syscfg: syscon@50020000 { 259 compatible = "st,stm32mp157-syscfg", "syscon"; 260 reg = <0x50020000 0x400>; 261 clocks = <&rcc SYSCFG>; 262 }; 263 264 dts: thermal@50028000 { 265 compatible = "st,stm32-thermal"; 266 reg = <0x50028000 0x100>; 267 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&rcc TMPSENS>; 269 clock-names = "pclk"; 270 #thermal-sensor-cells = <0>; 271 status = "disabled"; 272 }; 273 274 mdma1: dma-controller@58000000 { 275 compatible = "st,stm32h7-mdma"; 276 reg = <0x58000000 0x1000>; 277 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&rcc MDMA>; 279 resets = <&rcc MDMA_R>; 280 #dma-cells = <5>; 281 dma-channels = <32>; 282 dma-requests = <48>; 283 }; 284 285 sdmmc1: mmc@58005000 { 286 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 287 arm,primecell-periphid = <0x00253180>; 288 reg = <0x58005000 0x1000>; 289 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "cmd_irq"; 291 clocks = <&rcc SDMMC1_K>; 292 clock-names = "apb_pclk"; 293 resets = <&rcc SDMMC1_R>; 294 cap-sd-highspeed; 295 cap-mmc-highspeed; 296 max-frequency = <120000000>; 297 status = "disabled"; 298 }; 299 300 sdmmc2: mmc@58007000 { 301 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 302 arm,primecell-periphid = <0x00253180>; 303 reg = <0x58007000 0x1000>; 304 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 305 interrupt-names = "cmd_irq"; 306 clocks = <&rcc SDMMC2_K>; 307 clock-names = "apb_pclk"; 308 resets = <&rcc SDMMC2_R>; 309 cap-sd-highspeed; 310 cap-mmc-highspeed; 311 max-frequency = <120000000>; 312 status = "disabled"; 313 }; 314 315 crc1: crc@58009000 { 316 compatible = "st,stm32f7-crc"; 317 reg = <0x58009000 0x400>; 318 clocks = <&rcc CRC1>; 319 status = "disabled"; 320 }; 321 322 usbh_ohci: usb@5800c000 { 323 compatible = "generic-ohci"; 324 reg = <0x5800c000 0x1000>; 325 clocks = <&usbphyc>, <&rcc USBH>; 326 resets = <&rcc USBH_R>; 327 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 328 status = "disabled"; 329 }; 330 331 usbh_ehci: usb@5800d000 { 332 compatible = "generic-ehci"; 333 reg = <0x5800d000 0x1000>; 334 clocks = <&usbphyc>, <&rcc USBH>; 335 resets = <&rcc USBH_R>; 336 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 337 companion = <&usbh_ohci>; 338 status = "disabled"; 339 }; 340 341 ltdc: display-controller@5a001000 { 342 compatible = "st,stm32-ltdc"; 343 reg = <0x5a001000 0x400>; 344 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&rcc LTDC_PX>; 347 clock-names = "lcd"; 348 resets = <&rcc LTDC_R>; 349 status = "disabled"; 350 351 port { 352 #address-cells = <1>; 353 #size-cells = <0>; 354 }; 355 }; 356 357 iwdg2: watchdog@5a002000 { 358 compatible = "st,stm32mp1-iwdg"; 359 reg = <0x5a002000 0x400>; 360 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 362 clock-names = "pclk", "lsi"; 363 status = "disabled"; 364 }; 365 366 usbphyc: usbphyc@5a006000 { 367 #address-cells = <1>; 368 #size-cells = <0>; 369 #clock-cells = <0>; 370 compatible = "st,stm32mp1-usbphyc"; 371 reg = <0x5a006000 0x1000>; 372 clocks = <&rcc USBPHY_K>; 373 resets = <&rcc USBPHY_R>; 374 vdda1v1-supply = <®11>; 375 vdda1v8-supply = <®18>; 376 status = "disabled"; 377 378 usbphyc_port0: usb-phy@0 { 379 #phy-cells = <0>; 380 reg = <0>; 381 }; 382 383 usbphyc_port1: usb-phy@1 { 384 #phy-cells = <1>; 385 reg = <1>; 386 }; 387 }; 388 389 rtc: rtc@5c004000 { 390 compatible = "st,stm32mp1-rtc"; 391 reg = <0x5c004000 0x400>; 392 clocks = <&rcc RTCAPB>, <&rcc RTC>; 393 clock-names = "pclk", "rtc_ck"; 394 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 395 status = "disabled"; 396 }; 397 398 bsec: efuse@5c005000 { 399 compatible = "st,stm32mp15-bsec"; 400 reg = <0x5c005000 0x400>; 401 #address-cells = <1>; 402 #size-cells = <1>; 403 404 cfg0_otp: cfg0_otp@0 { 405 reg = <0x0 0x1>; 406 }; 407 part_number_otp: part_number_otp@4 { 408 reg = <0x4 0x1>; 409 }; 410 monotonic_otp: monotonic_otp@10 { 411 reg = <0x10 0x4>; 412 }; 413 nand_otp: nand_otp@24 { 414 reg = <0x24 0x4>; 415 }; 416 uid_otp: uid_otp@34 { 417 reg = <0x34 0xc>; 418 }; 419 package_otp: package_otp@40 { 420 reg = <0x40 0x4>; 421 }; 422 hw2_otp: hw2_otp@48 { 423 reg = <0x48 0x4>; 424 }; 425 ts_cal1: calib@5c { 426 reg = <0x5c 0x2>; 427 }; 428 ts_cal2: calib@5e { 429 reg = <0x5e 0x2>; 430 }; 431 pkh_otp: pkh_otp@60 { 432 reg = <0x60 0x20>; 433 }; 434 ethernet_mac_address: mac@e4 { 435 reg = <0xe4 0x8>; 436 st,non-secure-otp; 437 }; 438 }; 439 440 tamp: tamp@5c00a000 { 441 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 442 reg = <0x5c00a000 0x400>; 443 clocks = <&rcc RTCAPB>; 444 st,backup-zones = <10 5 17>; 445 }; 446 447 /* 448 * Break node order to solve dependency probe issue between 449 * pinctrl and exti. 450 */ 451 pinctrl: pinctrl@50002000 { 452 #address-cells = <1>; 453 #size-cells = <1>; 454 compatible = "st,stm32mp157-pinctrl"; 455 ranges = <0 0x50002000 0xa400>; 456 interrupt-parent = <&exti>; 457 st,syscfg = <&exti 0x60 0xff>; 458 pins-are-numbered; 459 460 gpioa: gpio@50002000 { 461 gpio-controller; 462 #gpio-cells = <2>; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 reg = <0x0 0x400>; 466 clocks = <&rcc GPIOA>; 467 st,bank-name = "GPIOA"; 468 status = "disabled"; 469 }; 470 471 gpiob: gpio@50003000 { 472 gpio-controller; 473 #gpio-cells = <2>; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 reg = <0x1000 0x400>; 477 clocks = <&rcc GPIOB>; 478 st,bank-name = "GPIOB"; 479 status = "disabled"; 480 }; 481 482 gpioc: gpio@50004000 { 483 gpio-controller; 484 #gpio-cells = <2>; 485 interrupt-controller; 486 #interrupt-cells = <2>; 487 reg = <0x2000 0x400>; 488 clocks = <&rcc GPIOC>; 489 st,bank-name = "GPIOC"; 490 status = "disabled"; 491 }; 492 493 gpiod: gpio@50005000 { 494 gpio-controller; 495 #gpio-cells = <2>; 496 interrupt-controller; 497 #interrupt-cells = <2>; 498 reg = <0x3000 0x400>; 499 clocks = <&rcc GPIOD>; 500 st,bank-name = "GPIOD"; 501 status = "disabled"; 502 }; 503 504 gpioe: gpio@50006000 { 505 gpio-controller; 506 #gpio-cells = <2>; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 reg = <0x4000 0x400>; 510 clocks = <&rcc GPIOE>; 511 st,bank-name = "GPIOE"; 512 status = "disabled"; 513 }; 514 515 gpiof: gpio@50007000 { 516 gpio-controller; 517 #gpio-cells = <2>; 518 interrupt-controller; 519 #interrupt-cells = <2>; 520 reg = <0x5000 0x400>; 521 clocks = <&rcc GPIOF>; 522 st,bank-name = "GPIOF"; 523 status = "disabled"; 524 }; 525 526 gpiog: gpio@50008000 { 527 gpio-controller; 528 #gpio-cells = <2>; 529 interrupt-controller; 530 #interrupt-cells = <2>; 531 reg = <0x6000 0x400>; 532 clocks = <&rcc GPIOG>; 533 st,bank-name = "GPIOG"; 534 status = "disabled"; 535 }; 536 537 gpioh: gpio@50009000 { 538 gpio-controller; 539 #gpio-cells = <2>; 540 interrupt-controller; 541 #interrupt-cells = <2>; 542 reg = <0x7000 0x400>; 543 clocks = <&rcc GPIOH>; 544 st,bank-name = "GPIOH"; 545 status = "disabled"; 546 }; 547 548 gpioi: gpio@5000a000 { 549 gpio-controller; 550 #gpio-cells = <2>; 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 reg = <0x8000 0x400>; 554 clocks = <&rcc GPIOI>; 555 st,bank-name = "GPIOI"; 556 status = "disabled"; 557 }; 558 559 gpioj: gpio@5000b000 { 560 gpio-controller; 561 #gpio-cells = <2>; 562 interrupt-controller; 563 #interrupt-cells = <2>; 564 reg = <0x9000 0x400>; 565 clocks = <&rcc GPIOJ>; 566 st,bank-name = "GPIOJ"; 567 status = "disabled"; 568 }; 569 570 gpiok: gpio@5000c000 { 571 gpio-controller; 572 #gpio-cells = <2>; 573 interrupt-controller; 574 #interrupt-cells = <2>; 575 reg = <0xa000 0x400>; 576 clocks = <&rcc GPIOK>; 577 st,bank-name = "GPIOK"; 578 status = "disabled"; 579 }; 580 }; 581 582 pinctrl_z: pinctrl@54004000 { 583 #address-cells = <1>; 584 #size-cells = <1>; 585 compatible = "st,stm32mp157-z-pinctrl"; 586 ranges = <0 0x54004000 0x400>; 587 pins-are-numbered; 588 interrupt-parent = <&exti>; 589 st,syscfg = <&exti 0x60 0xff>; 590 591 gpioz: gpio@54004000 { 592 gpio-controller; 593 #gpio-cells = <2>; 594 interrupt-controller; 595 #interrupt-cells = <2>; 596 #access-controller-cells = <1>; 597 reg = <0 0x400>; 598 clocks = <&rcc GPIOZ>; 599 st,bank-name = "GPIOZ"; 600 st,bank-ioport = <11>; 601 status = "disabled"; 602 }; 603 }; 604 605 tzc400: tzc@5c006000 { 606 compatible = "st,stm32mp1-tzc"; 607 reg = <0x5c006000 0x1000>; 608 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&rcc TZC1>, <&rcc TZC2>; 610 st,mem-map = <0xc0000000 0x40000000>; 611 }; 612 613 etzpc: etzpc@5c007000 { 614 compatible = "st,stm32-etzpc", "simple-bus"; 615 reg = <0x5C007000 0x400>; 616 clocks = <&rcc TZPC>; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 #access-controller-cells = <1>; 620 621 timers2: timer@40000000 { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 compatible = "st,stm32-timers"; 625 reg = <0x40000000 0x400>; 626 clocks = <&rcc TIM2_K>; 627 clock-names = "int"; 628 dmas = <&dmamux1 18 0x400 0x1>, 629 <&dmamux1 19 0x400 0x1>, 630 <&dmamux1 20 0x400 0x1>, 631 <&dmamux1 21 0x400 0x1>, 632 <&dmamux1 22 0x400 0x1>; 633 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 634 access-controllers = <&etzpc STM32MP1_ETZPC_TIM2_ID>; 635 status = "disabled"; 636 637 pwm { 638 compatible = "st,stm32-pwm"; 639 #pwm-cells = <3>; 640 status = "disabled"; 641 }; 642 643 timer@1 { 644 compatible = "st,stm32h7-timer-trigger"; 645 reg = <1>; 646 status = "disabled"; 647 }; 648 649 counter { 650 compatible = "st,stm32-timer-counter"; 651 status = "disabled"; 652 }; 653 }; 654 655 timers3: timer@40001000 { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 compatible = "st,stm32-timers"; 659 reg = <0x40001000 0x400>; 660 clocks = <&rcc TIM3_K>; 661 clock-names = "int"; 662 dmas = <&dmamux1 23 0x400 0x1>, 663 <&dmamux1 24 0x400 0x1>, 664 <&dmamux1 25 0x400 0x1>, 665 <&dmamux1 26 0x400 0x1>, 666 <&dmamux1 27 0x400 0x1>, 667 <&dmamux1 28 0x400 0x1>; 668 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 669 access-controllers = <&etzpc STM32MP1_ETZPC_TIM3_ID>; 670 status = "disabled"; 671 672 pwm { 673 compatible = "st,stm32-pwm"; 674 #pwm-cells = <3>; 675 status = "disabled"; 676 }; 677 678 timer@2 { 679 compatible = "st,stm32h7-timer-trigger"; 680 reg = <2>; 681 status = "disabled"; 682 }; 683 684 counter { 685 compatible = "st,stm32-timer-counter"; 686 status = "disabled"; 687 }; 688 }; 689 690 timers4: timer@40002000 { 691 #address-cells = <1>; 692 #size-cells = <0>; 693 compatible = "st,stm32-timers"; 694 reg = <0x40002000 0x400>; 695 clocks = <&rcc TIM4_K>; 696 clock-names = "int"; 697 dmas = <&dmamux1 29 0x400 0x1>, 698 <&dmamux1 30 0x400 0x1>, 699 <&dmamux1 31 0x400 0x1>, 700 <&dmamux1 32 0x400 0x1>; 701 dma-names = "ch1", "ch2", "ch3", "ch4"; 702 access-controllers = <&etzpc STM32MP1_ETZPC_TIM4_ID>; 703 status = "disabled"; 704 705 pwm { 706 compatible = "st,stm32-pwm"; 707 #pwm-cells = <3>; 708 status = "disabled"; 709 }; 710 711 timer@3 { 712 compatible = "st,stm32h7-timer-trigger"; 713 reg = <3>; 714 status = "disabled"; 715 }; 716 717 counter { 718 compatible = "st,stm32-timer-counter"; 719 status = "disabled"; 720 }; 721 }; 722 723 timers5: timer@40003000 { 724 #address-cells = <1>; 725 #size-cells = <0>; 726 compatible = "st,stm32-timers"; 727 reg = <0x40003000 0x400>; 728 clocks = <&rcc TIM5_K>; 729 clock-names = "int"; 730 dmas = <&dmamux1 55 0x400 0x1>, 731 <&dmamux1 56 0x400 0x1>, 732 <&dmamux1 57 0x400 0x1>, 733 <&dmamux1 58 0x400 0x1>, 734 <&dmamux1 59 0x400 0x1>, 735 <&dmamux1 60 0x400 0x1>; 736 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 737 access-controllers = <&etzpc STM32MP1_ETZPC_TIM5_ID>; 738 status = "disabled"; 739 740 pwm { 741 compatible = "st,stm32-pwm"; 742 #pwm-cells = <3>; 743 status = "disabled"; 744 }; 745 746 timer@4 { 747 compatible = "st,stm32h7-timer-trigger"; 748 reg = <4>; 749 status = "disabled"; 750 }; 751 752 counter { 753 compatible = "st,stm32-timer-counter"; 754 status = "disabled"; 755 }; 756 }; 757 758 timers6: timer@40004000 { 759 #address-cells = <1>; 760 #size-cells = <0>; 761 compatible = "st,stm32-timers"; 762 reg = <0x40004000 0x400>; 763 clocks = <&rcc TIM6_K>; 764 clock-names = "int"; 765 dmas = <&dmamux1 69 0x400 0x1>; 766 dma-names = "up"; 767 access-controllers = <&etzpc STM32MP1_ETZPC_TIM6_ID>; 768 status = "disabled"; 769 770 timer@5 { 771 compatible = "st,stm32h7-timer-trigger"; 772 reg = <5>; 773 status = "disabled"; 774 }; 775 }; 776 777 timers7: timer@40005000 { 778 #address-cells = <1>; 779 #size-cells = <0>; 780 compatible = "st,stm32-timers"; 781 reg = <0x40005000 0x400>; 782 clocks = <&rcc TIM7_K>; 783 clock-names = "int"; 784 dmas = <&dmamux1 70 0x400 0x1>; 785 dma-names = "up"; 786 access-controllers = <&etzpc STM32MP1_ETZPC_TIM7_ID>; 787 status = "disabled"; 788 789 timer@6 { 790 compatible = "st,stm32h7-timer-trigger"; 791 reg = <6>; 792 status = "disabled"; 793 }; 794 }; 795 796 timers12: timer@40006000 { 797 #address-cells = <1>; 798 #size-cells = <0>; 799 compatible = "st,stm32-timers"; 800 reg = <0x40006000 0x400>; 801 clocks = <&rcc TIM12_K>; 802 clock-names = "int"; 803 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 804 status = "disabled"; 805 806 pwm { 807 compatible = "st,stm32-pwm"; 808 #pwm-cells = <3>; 809 status = "disabled"; 810 }; 811 812 timer@11 { 813 compatible = "st,stm32h7-timer-trigger"; 814 reg = <11>; 815 status = "disabled"; 816 }; 817 }; 818 819 timers13: timer@40007000 { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 compatible = "st,stm32-timers"; 823 reg = <0x40007000 0x400>; 824 clocks = <&rcc TIM13_K>; 825 clock-names = "int"; 826 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 827 status = "disabled"; 828 829 pwm { 830 compatible = "st,stm32-pwm"; 831 #pwm-cells = <3>; 832 status = "disabled"; 833 }; 834 835 timer@12 { 836 compatible = "st,stm32h7-timer-trigger"; 837 reg = <12>; 838 status = "disabled"; 839 }; 840 }; 841 842 timers14: timer@40008000 { 843 #address-cells = <1>; 844 #size-cells = <0>; 845 compatible = "st,stm32-timers"; 846 reg = <0x40008000 0x400>; 847 clocks = <&rcc TIM14_K>; 848 clock-names = "int"; 849 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 850 status = "disabled"; 851 852 pwm { 853 compatible = "st,stm32-pwm"; 854 #pwm-cells = <3>; 855 status = "disabled"; 856 }; 857 858 timer@13 { 859 compatible = "st,stm32h7-timer-trigger"; 860 reg = <13>; 861 status = "disabled"; 862 }; 863 }; 864 865 lptimer1: timer@40009000 { 866 #address-cells = <1>; 867 #size-cells = <0>; 868 compatible = "st,stm32-lptimer"; 869 reg = <0x40009000 0x400>; 870 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&rcc LPTIM1_K>; 872 clock-names = "mux"; 873 wakeup-source; 874 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM1_ID>; 875 status = "disabled"; 876 877 pwm { 878 compatible = "st,stm32-pwm-lp"; 879 #pwm-cells = <3>; 880 status = "disabled"; 881 }; 882 883 trigger@0 { 884 compatible = "st,stm32-lptimer-trigger"; 885 reg = <0>; 886 status = "disabled"; 887 }; 888 889 counter { 890 compatible = "st,stm32-lptimer-counter"; 891 status = "disabled"; 892 }; 893 }; 894 895 spi2: spi@4000b000 { 896 #address-cells = <1>; 897 #size-cells = <0>; 898 compatible = "st,stm32h7-spi"; 899 reg = <0x4000b000 0x400>; 900 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&rcc SPI2_K>; 902 resets = <&rcc SPI2_R>; 903 dmas = <&dmamux1 39 0x400 0x05>, 904 <&dmamux1 40 0x400 0x05>; 905 dma-names = "rx", "tx"; 906 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 907 status = "disabled"; 908 }; 909 910 i2s2: audio-controller@4000b000 { 911 compatible = "st,stm32h7-i2s"; 912 #sound-dai-cells = <0>; 913 reg = <0x4000b000 0x400>; 914 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 915 dmas = <&dmamux1 39 0x400 0x01>, 916 <&dmamux1 40 0x400 0x01>; 917 dma-names = "rx", "tx"; 918 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 919 status = "disabled"; 920 }; 921 922 spi3: spi@4000c000 { 923 #address-cells = <1>; 924 #size-cells = <0>; 925 compatible = "st,stm32h7-spi"; 926 reg = <0x4000c000 0x400>; 927 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&rcc SPI3_K>; 929 resets = <&rcc SPI3_R>; 930 dmas = <&dmamux1 61 0x400 0x05>, 931 <&dmamux1 62 0x400 0x05>; 932 dma-names = "rx", "tx"; 933 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 934 status = "disabled"; 935 }; 936 937 i2s3: audio-controller@4000c000 { 938 compatible = "st,stm32h7-i2s"; 939 #sound-dai-cells = <0>; 940 reg = <0x4000c000 0x400>; 941 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 942 dmas = <&dmamux1 61 0x400 0x01>, 943 <&dmamux1 62 0x400 0x01>; 944 dma-names = "rx", "tx"; 945 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 946 status = "disabled"; 947 }; 948 949 spdifrx: audio-controller@4000d000 { 950 compatible = "st,stm32h7-spdifrx"; 951 #sound-dai-cells = <0>; 952 reg = <0x4000d000 0x400>; 953 clocks = <&rcc SPDIF_K>; 954 clock-names = "kclk"; 955 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 956 dmas = <&dmamux1 93 0x400 0x01>, 957 <&dmamux1 94 0x400 0x01>; 958 dma-names = "rx", "rx-ctrl"; 959 access-controllers = <&etzpc STM32MP1_ETZPC_SPDIFRX_ID>; 960 status = "disabled"; 961 }; 962 963 usart2: serial@4000e000 { 964 compatible = "st,stm32h7-uart"; 965 reg = <0x4000e000 0x400>; 966 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&rcc USART2_K>; 968 wakeup-source; 969 dmas = <&dmamux1 43 0x400 0x15>, 970 <&dmamux1 44 0x400 0x11>; 971 dma-names = "rx", "tx"; 972 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 973 status = "disabled"; 974 }; 975 976 usart3: serial@4000f000 { 977 compatible = "st,stm32h7-uart"; 978 reg = <0x4000f000 0x400>; 979 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&rcc USART3_K>; 981 wakeup-source; 982 dmas = <&dmamux1 45 0x400 0x15>, 983 <&dmamux1 46 0x400 0x11>; 984 dma-names = "rx", "tx"; 985 access-controllers = <&etzpc STM32MP1_ETZPC_USART3_ID>; 986 status = "disabled"; 987 }; 988 989 uart4: serial@40010000 { 990 compatible = "st,stm32h7-uart"; 991 reg = <0x40010000 0x400>; 992 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&rcc UART4_K>; 994 wakeup-source; 995 dmas = <&dmamux1 63 0x400 0x15>, 996 <&dmamux1 64 0x400 0x11>; 997 dma-names = "rx", "tx"; 998 access-controllers = <&etzpc STM32MP1_ETZPC_UART4_ID>; 999 status = "disabled"; 1000 }; 1001 1002 uart5: serial@40011000 { 1003 compatible = "st,stm32h7-uart"; 1004 reg = <0x40011000 0x400>; 1005 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&rcc UART5_K>; 1007 wakeup-source; 1008 dmas = <&dmamux1 65 0x400 0x15>, 1009 <&dmamux1 66 0x400 0x11>; 1010 dma-names = "rx", "tx"; 1011 access-controllers = <&etzpc STM32MP1_ETZPC_UART5_ID>; 1012 status = "disabled"; 1013 }; 1014 1015 i2c1: i2c@40012000 { 1016 compatible = "st,stm32mp15-i2c"; 1017 reg = <0x40012000 0x400>; 1018 interrupt-names = "event", "error"; 1019 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&rcc I2C1_K>; 1022 resets = <&rcc I2C1_R>; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 st,syscfg-fmp = <&syscfg 0x4 0x1>; 1026 wakeup-source; 1027 i2c-analog-filter; 1028 access-controllers = <&etzpc STM32MP1_ETZPC_I2C1_ID>; 1029 status = "disabled"; 1030 }; 1031 1032 i2c2: i2c@40013000 { 1033 compatible = "st,stm32mp15-i2c"; 1034 reg = <0x40013000 0x400>; 1035 interrupt-names = "event", "error"; 1036 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&rcc I2C2_K>; 1039 resets = <&rcc I2C2_R>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 st,syscfg-fmp = <&syscfg 0x4 0x2>; 1043 wakeup-source; 1044 i2c-analog-filter; 1045 access-controllers = <&etzpc STM32MP1_ETZPC_I2C2_ID>; 1046 status = "disabled"; 1047 }; 1048 1049 i2c3: i2c@40014000 { 1050 compatible = "st,stm32mp15-i2c"; 1051 reg = <0x40014000 0x400>; 1052 interrupt-names = "event", "error"; 1053 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&rcc I2C3_K>; 1056 resets = <&rcc I2C3_R>; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 st,syscfg-fmp = <&syscfg 0x4 0x4>; 1060 wakeup-source; 1061 i2c-analog-filter; 1062 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 1063 status = "disabled"; 1064 }; 1065 1066 i2c5: i2c@40015000 { 1067 compatible = "st,stm32mp15-i2c"; 1068 reg = <0x40015000 0x400>; 1069 interrupt-names = "event", "error"; 1070 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&rcc I2C5_K>; 1073 resets = <&rcc I2C5_R>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1077 wakeup-source; 1078 i2c-analog-filter; 1079 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 1080 status = "disabled"; 1081 }; 1082 1083 cec: cec@40016000 { 1084 compatible = "st,stm32-cec"; 1085 reg = <0x40016000 0x400>; 1086 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1087 clocks = <&rcc CEC_K>, <&rcc CEC>; 1088 clock-names = "cec", "hdmi-cec"; 1089 access-controllers = <&etzpc STM32MP1_ETZPC_CEC_ID>; 1090 status = "disabled"; 1091 }; 1092 1093 dac: dac@40017000 { 1094 compatible = "st,stm32h7-dac-core"; 1095 reg = <0x40017000 0x400>; 1096 clocks = <&rcc DAC12>; 1097 clock-names = "pclk"; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 access-controllers = <&etzpc STM32MP1_ETZPC_DAC_ID>; 1101 status = "disabled"; 1102 1103 dac1: dac@1 { 1104 compatible = "st,stm32-dac"; 1105 #io-channel-cells = <1>; 1106 reg = <1>; 1107 status = "disabled"; 1108 }; 1109 1110 dac2: dac@2 { 1111 compatible = "st,stm32-dac"; 1112 #io-channel-cells = <1>; 1113 reg = <2>; 1114 status = "disabled"; 1115 }; 1116 }; 1117 1118 uart7: serial@40018000 { 1119 compatible = "st,stm32h7-uart"; 1120 reg = <0x40018000 0x400>; 1121 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&rcc UART7_K>; 1123 wakeup-source; 1124 dmas = <&dmamux1 79 0x400 0x15>, 1125 <&dmamux1 80 0x400 0x11>; 1126 dma-names = "rx", "tx"; 1127 access-controllers = <&etzpc STM32MP1_ETZPC_UART7_ID>; 1128 status = "disabled"; 1129 }; 1130 1131 uart8: serial@40019000 { 1132 compatible = "st,stm32h7-uart"; 1133 reg = <0x40019000 0x400>; 1134 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&rcc UART8_K>; 1136 wakeup-source; 1137 dmas = <&dmamux1 81 0x400 0x15>, 1138 <&dmamux1 82 0x400 0x11>; 1139 dma-names = "rx", "tx"; 1140 access-controllers = <&etzpc STM32MP1_ETZPC_UART8_ID>; 1141 status = "disabled"; 1142 }; 1143 1144 timers1: timer@44000000 { 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 compatible = "st,stm32-timers"; 1148 reg = <0x44000000 0x400>; 1149 clocks = <&rcc TIM1_K>; 1150 clock-names = "int"; 1151 dmas = <&dmamux1 11 0x400 0x1>, 1152 <&dmamux1 12 0x400 0x1>, 1153 <&dmamux1 13 0x400 0x1>, 1154 <&dmamux1 14 0x400 0x1>, 1155 <&dmamux1 15 0x400 0x1>, 1156 <&dmamux1 16 0x400 0x1>, 1157 <&dmamux1 17 0x400 0x1>; 1158 dma-names = "ch1", "ch2", "ch3", "ch4", 1159 "up", "trig", "com"; 1160 access-controllers = <&etzpc STM32MP1_ETZPC_TIM1_ID>; 1161 status = "disabled"; 1162 1163 pwm { 1164 compatible = "st,stm32-pwm"; 1165 #pwm-cells = <3>; 1166 status = "disabled"; 1167 }; 1168 1169 timer@0 { 1170 compatible = "st,stm32h7-timer-trigger"; 1171 reg = <0>; 1172 status = "disabled"; 1173 }; 1174 1175 counter { 1176 compatible = "st,stm32-timer-counter"; 1177 status = "disabled"; 1178 }; 1179 }; 1180 1181 timers8: timer@44001000 { 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 compatible = "st,stm32-timers"; 1185 reg = <0x44001000 0x400>; 1186 clocks = <&rcc TIM8_K>; 1187 clock-names = "int"; 1188 dmas = <&dmamux1 47 0x400 0x1>, 1189 <&dmamux1 48 0x400 0x1>, 1190 <&dmamux1 49 0x400 0x1>, 1191 <&dmamux1 50 0x400 0x1>, 1192 <&dmamux1 51 0x400 0x1>, 1193 <&dmamux1 52 0x400 0x1>, 1194 <&dmamux1 53 0x400 0x1>; 1195 dma-names = "ch1", "ch2", "ch3", "ch4", 1196 "up", "trig", "com"; 1197 access-controllers = <&etzpc STM32MP1_ETZPC_TIM8_ID>; 1198 status = "disabled"; 1199 1200 pwm { 1201 compatible = "st,stm32-pwm"; 1202 #pwm-cells = <3>; 1203 status = "disabled"; 1204 }; 1205 1206 timer@7 { 1207 compatible = "st,stm32h7-timer-trigger"; 1208 reg = <7>; 1209 status = "disabled"; 1210 }; 1211 1212 counter { 1213 compatible = "st,stm32-timer-counter"; 1214 status = "disabled"; 1215 }; 1216 }; 1217 1218 usart6: serial@44003000 { 1219 compatible = "st,stm32h7-uart"; 1220 reg = <0x44003000 0x400>; 1221 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&rcc USART6_K>; 1223 wakeup-source; 1224 dmas = <&dmamux1 71 0x400 0x15>, 1225 <&dmamux1 72 0x400 0x11>; 1226 dma-names = "rx", "tx"; 1227 access-controllers = <&etzpc STM32MP1_ETZPC_USART6_ID>; 1228 status = "disabled"; 1229 }; 1230 1231 spi1: spi@44004000 { 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 compatible = "st,stm32h7-spi"; 1235 reg = <0x44004000 0x400>; 1236 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1237 clocks = <&rcc SPI1_K>; 1238 resets = <&rcc SPI1_R>; 1239 dmas = <&dmamux1 37 0x400 0x05>, 1240 <&dmamux1 38 0x400 0x05>; 1241 dma-names = "rx", "tx"; 1242 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1243 status = "disabled"; 1244 }; 1245 1246 i2s1: audio-controller@44004000 { 1247 compatible = "st,stm32h7-i2s"; 1248 #sound-dai-cells = <0>; 1249 reg = <0x44004000 0x400>; 1250 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1251 dmas = <&dmamux1 37 0x400 0x01>, 1252 <&dmamux1 38 0x400 0x01>; 1253 dma-names = "rx", "tx"; 1254 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1255 status = "disabled"; 1256 }; 1257 1258 spi4: spi@44005000 { 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 compatible = "st,stm32h7-spi"; 1262 reg = <0x44005000 0x400>; 1263 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&rcc SPI4_K>; 1265 resets = <&rcc SPI4_R>; 1266 dmas = <&dmamux1 83 0x400 0x05>, 1267 <&dmamux1 84 0x400 0x05>; 1268 dma-names = "rx", "tx"; 1269 access-controllers = <&etzpc STM32MP1_ETZPC_SPI4_ID>; 1270 status = "disabled"; 1271 }; 1272 1273 timers15: timer@44006000 { 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 compatible = "st,stm32-timers"; 1277 reg = <0x44006000 0x400>; 1278 clocks = <&rcc TIM15_K>; 1279 clock-names = "int"; 1280 dmas = <&dmamux1 105 0x400 0x1>, 1281 <&dmamux1 106 0x400 0x1>, 1282 <&dmamux1 107 0x400 0x1>, 1283 <&dmamux1 108 0x400 0x1>; 1284 dma-names = "ch1", "up", "trig", "com"; 1285 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 1286 status = "disabled"; 1287 1288 pwm { 1289 compatible = "st,stm32-pwm"; 1290 #pwm-cells = <3>; 1291 status = "disabled"; 1292 }; 1293 1294 timer@14 { 1295 compatible = "st,stm32h7-timer-trigger"; 1296 reg = <14>; 1297 status = "disabled"; 1298 }; 1299 }; 1300 1301 timers16: timer@44007000 { 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 compatible = "st,stm32-timers"; 1305 reg = <0x44007000 0x400>; 1306 clocks = <&rcc TIM16_K>; 1307 clock-names = "int"; 1308 dmas = <&dmamux1 109 0x400 0x1>, 1309 <&dmamux1 110 0x400 0x1>; 1310 dma-names = "ch1", "up"; 1311 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 1312 status = "disabled"; 1313 1314 pwm { 1315 compatible = "st,stm32-pwm"; 1316 #pwm-cells = <3>; 1317 status = "disabled"; 1318 }; 1319 timer@15 { 1320 compatible = "st,stm32h7-timer-trigger"; 1321 reg = <15>; 1322 status = "disabled"; 1323 }; 1324 }; 1325 1326 timers17: timer@44008000 { 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 compatible = "st,stm32-timers"; 1330 reg = <0x44008000 0x400>; 1331 clocks = <&rcc TIM17_K>; 1332 clock-names = "int"; 1333 dmas = <&dmamux1 111 0x400 0x1>, 1334 <&dmamux1 112 0x400 0x1>; 1335 dma-names = "ch1", "up"; 1336 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 1337 status = "disabled"; 1338 1339 pwm { 1340 compatible = "st,stm32-pwm"; 1341 #pwm-cells = <3>; 1342 status = "disabled"; 1343 }; 1344 1345 timer@16 { 1346 compatible = "st,stm32h7-timer-trigger"; 1347 reg = <16>; 1348 status = "disabled"; 1349 }; 1350 }; 1351 1352 spi5: spi@44009000 { 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 compatible = "st,stm32h7-spi"; 1356 reg = <0x44009000 0x400>; 1357 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1358 clocks = <&rcc SPI5_K>; 1359 resets = <&rcc SPI5_R>; 1360 dmas = <&dmamux1 85 0x400 0x05>, 1361 <&dmamux1 86 0x400 0x05>; 1362 dma-names = "rx", "tx"; 1363 access-controllers = <&etzpc STM32MP1_ETZPC_SPI5_ID>; 1364 status = "disabled"; 1365 }; 1366 1367 sai1: sai@4400a000 { 1368 compatible = "st,stm32h7-sai"; 1369 #address-cells = <1>; 1370 #size-cells = <1>; 1371 ranges = <0 0x4400a000 0x400>; 1372 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1373 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1374 resets = <&rcc SAI1_R>; 1375 access-controllers = <&etzpc STM32MP1_ETZPC_SAI1_ID>; 1376 status = "disabled"; 1377 1378 sai1a: audio-controller@4400a004 { 1379 #sound-dai-cells = <0>; 1380 1381 compatible = "st,stm32-sai-sub-a"; 1382 reg = <0x4 0x20>; 1383 clocks = <&rcc SAI1_K>; 1384 clock-names = "sai_ck"; 1385 dmas = <&dmamux1 87 0x400 0x01>; 1386 status = "disabled"; 1387 }; 1388 1389 sai1b: audio-controller@4400a024 { 1390 #sound-dai-cells = <0>; 1391 compatible = "st,stm32-sai-sub-b"; 1392 reg = <0x24 0x20>; 1393 clocks = <&rcc SAI1_K>; 1394 clock-names = "sai_ck"; 1395 dmas = <&dmamux1 88 0x400 0x01>; 1396 status = "disabled"; 1397 }; 1398 }; 1399 1400 sai2: sai@4400b000 { 1401 compatible = "st,stm32h7-sai"; 1402 #address-cells = <1>; 1403 #size-cells = <1>; 1404 ranges = <0 0x4400b000 0x400>; 1405 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1406 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1407 resets = <&rcc SAI2_R>; 1408 access-controllers = <&etzpc STM32MP1_ETZPC_SAI2_ID>; 1409 status = "disabled"; 1410 1411 sai2a: audio-controller@4400b004 { 1412 #sound-dai-cells = <0>; 1413 compatible = "st,stm32-sai-sub-a"; 1414 reg = <0x4 0x20>; 1415 clocks = <&rcc SAI2_K>; 1416 clock-names = "sai_ck"; 1417 dmas = <&dmamux1 89 0x400 0x01>; 1418 status = "disabled"; 1419 }; 1420 1421 sai2b: audio-controller@4400b024 { 1422 #sound-dai-cells = <0>; 1423 compatible = "st,stm32-sai-sub-b"; 1424 reg = <0x24 0x20>; 1425 clocks = <&rcc SAI2_K>; 1426 clock-names = "sai_ck"; 1427 dmas = <&dmamux1 90 0x400 0x01>; 1428 status = "disabled"; 1429 }; 1430 }; 1431 1432 sai3: sai@4400c000 { 1433 compatible = "st,stm32h7-sai"; 1434 #address-cells = <1>; 1435 #size-cells = <1>; 1436 ranges = <0 0x4400c000 0x400>; 1437 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1438 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1439 resets = <&rcc SAI3_R>; 1440 access-controllers = <&etzpc STM32MP1_ETZPC_SAI3_ID>; 1441 status = "disabled"; 1442 1443 sai3a: audio-controller@4400c004 { 1444 #sound-dai-cells = <0>; 1445 compatible = "st,stm32-sai-sub-a"; 1446 reg = <0x04 0x20>; 1447 clocks = <&rcc SAI3_K>; 1448 clock-names = "sai_ck"; 1449 dmas = <&dmamux1 113 0x400 0x01>; 1450 status = "disabled"; 1451 }; 1452 1453 sai3b: audio-controller@4400c024 { 1454 #sound-dai-cells = <0>; 1455 compatible = "st,stm32-sai-sub-b"; 1456 reg = <0x24 0x20>; 1457 clocks = <&rcc SAI3_K>; 1458 clock-names = "sai_ck"; 1459 dmas = <&dmamux1 114 0x400 0x01>; 1460 status = "disabled"; 1461 }; 1462 }; 1463 1464 dfsdm: dfsdm@4400d000 { 1465 compatible = "st,stm32mp1-dfsdm"; 1466 reg = <0x4400d000 0x800>; 1467 clocks = <&rcc DFSDM_K>; 1468 clock-names = "dfsdm"; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 access-controllers = <&etzpc STM32MP1_ETZPC_DFSDM_ID>; 1472 status = "disabled"; 1473 1474 dfsdm0: filter@0 { 1475 compatible = "st,stm32-dfsdm-adc"; 1476 #io-channel-cells = <1>; 1477 reg = <0>; 1478 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1479 dmas = <&dmamux1 101 0x400 0x01>; 1480 dma-names = "rx"; 1481 status = "disabled"; 1482 }; 1483 1484 dfsdm1: filter@1 { 1485 compatible = "st,stm32-dfsdm-adc"; 1486 #io-channel-cells = <1>; 1487 reg = <1>; 1488 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1489 dmas = <&dmamux1 102 0x400 0x01>; 1490 dma-names = "rx"; 1491 status = "disabled"; 1492 }; 1493 1494 dfsdm2: filter@2 { 1495 compatible = "st,stm32-dfsdm-adc"; 1496 #io-channel-cells = <1>; 1497 reg = <2>; 1498 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1499 dmas = <&dmamux1 103 0x400 0x01>; 1500 dma-names = "rx"; 1501 status = "disabled"; 1502 }; 1503 1504 dfsdm3: filter@3 { 1505 compatible = "st,stm32-dfsdm-adc"; 1506 #io-channel-cells = <1>; 1507 reg = <3>; 1508 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1509 dmas = <&dmamux1 104 0x400 0x01>; 1510 dma-names = "rx"; 1511 status = "disabled"; 1512 }; 1513 1514 dfsdm4: filter@4 { 1515 compatible = "st,stm32-dfsdm-adc"; 1516 #io-channel-cells = <1>; 1517 reg = <4>; 1518 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1519 dmas = <&dmamux1 91 0x400 0x01>; 1520 dma-names = "rx"; 1521 status = "disabled"; 1522 }; 1523 1524 dfsdm5: filter@5 { 1525 compatible = "st,stm32-dfsdm-adc"; 1526 #io-channel-cells = <1>; 1527 reg = <5>; 1528 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1529 dmas = <&dmamux1 92 0x400 0x01>; 1530 dma-names = "rx"; 1531 status = "disabled"; 1532 }; 1533 }; 1534 1535 dma1: dma-controller@48000000 { 1536 compatible = "st,stm32-dma"; 1537 reg = <0x48000000 0x400>; 1538 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1546 clocks = <&rcc DMA1>; 1547 resets = <&rcc DMA1_R>; 1548 #dma-cells = <4>; 1549 st,mem2mem; 1550 dma-requests = <8>; 1551 access-controllers = <&etzpc STM32MP1_ETZPC_DMA1_ID>; 1552 status = "disabled"; 1553 }; 1554 1555 dma2: dma-controller@48001000 { 1556 compatible = "st,stm32-dma"; 1557 reg = <0x48001000 0x400>; 1558 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1566 clocks = <&rcc DMA2>; 1567 resets = <&rcc DMA2_R>; 1568 #dma-cells = <4>; 1569 st,mem2mem; 1570 dma-requests = <8>; 1571 access-controllers = <&etzpc STM32MP1_ETZPC_DMA2_ID>; 1572 status = "disabled"; 1573 }; 1574 1575 dmamux1: dma-router@48002000 { 1576 compatible = "st,stm32h7-dmamux"; 1577 reg = <0x48002000 0x40>; 1578 #dma-cells = <3>; 1579 dma-requests = <128>; 1580 dma-masters = <&dma1 &dma2>; 1581 dma-channels = <16>; 1582 clocks = <&rcc DMAMUX>; 1583 resets = <&rcc DMAMUX_R>; 1584 access-controllers = <&etzpc STM32MP1_ETZPC_DMAMUX_ID>; 1585 status = "disabled"; 1586 }; 1587 1588 adc: adc@48003000 { 1589 compatible = "st,stm32mp1-adc-core"; 1590 reg = <0x48003000 0x400>; 1591 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1593 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1594 clock-names = "bus", "adc"; 1595 interrupt-controller; 1596 st,syscfg = <&syscfg>; 1597 #interrupt-cells = <1>; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 access-controllers = <&etzpc STM32MP1_ETZPC_ADC_ID>; 1601 status = "disabled"; 1602 1603 adc1: adc@0 { 1604 compatible = "st,stm32mp1-adc"; 1605 #io-channel-cells = <1>; 1606 reg = <0x0>; 1607 interrupt-parent = <&adc>; 1608 interrupts = <0>; 1609 dmas = <&dmamux1 9 0x400 0x01>; 1610 dma-names = "rx"; 1611 status = "disabled"; 1612 }; 1613 1614 adc2: adc@100 { 1615 compatible = "st,stm32mp1-adc"; 1616 #io-channel-cells = <1>; 1617 reg = <0x100>; 1618 interrupt-parent = <&adc>; 1619 interrupts = <1>; 1620 dmas = <&dmamux1 10 0x400 0x01>; 1621 dma-names = "rx"; 1622 status = "disabled"; 1623 }; 1624 }; 1625 1626 sdmmc3: mmc@48004000 { 1627 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1628 arm,primecell-periphid = <0x00253180>; 1629 reg = <0x48004000 0x400>; 1630 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1631 interrupt-names = "cmd_irq"; 1632 clocks = <&rcc SDMMC3_K>; 1633 clock-names = "apb_pclk"; 1634 resets = <&rcc SDMMC3_R>; 1635 cap-sd-highspeed; 1636 cap-mmc-highspeed; 1637 max-frequency = <120000000>; 1638 access-controllers = <&etzpc STM32MP1_ETZPC_SDMMC3_ID>; 1639 status = "disabled"; 1640 }; 1641 1642 usbotg_hs: usb-otg@49000000 { 1643 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1644 reg = <0x49000000 0x10000>; 1645 clocks = <&rcc USBO_K>; 1646 clock-names = "otg"; 1647 resets = <&rcc USBO_R>; 1648 reset-names = "dwc2"; 1649 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1650 g-rx-fifo-size = <512>; 1651 g-np-tx-fifo-size = <32>; 1652 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1653 dr_mode = "otg"; 1654 otg-rev = <0x200>; 1655 usb33d-supply = <&usb33>; 1656 access-controllers = <&etzpc STM32MP1_ETZPC_OTG_ID>; 1657 status = "disabled"; 1658 }; 1659 1660 dcmi: dcmi@4c006000 { 1661 compatible = "st,stm32-dcmi"; 1662 reg = <0x4c006000 0x400>; 1663 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1664 resets = <&rcc CAMITF_R>; 1665 clocks = <&rcc DCMI>; 1666 clock-names = "mclk"; 1667 dmas = <&dmamux1 75 0x400 0x01>; 1668 dma-names = "tx"; 1669 access-controllers = <&etzpc STM32MP1_ETZPC_DCMI_ID>; 1670 status = "disabled"; 1671 }; 1672 1673 lptimer2: timer@50021000 { 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 compatible = "st,stm32-lptimer"; 1677 reg = <0x50021000 0x400>; 1678 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1679 clocks = <&rcc LPTIM2_K>; 1680 clock-names = "mux"; 1681 wakeup-source; 1682 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 1683 status = "disabled"; 1684 1685 pwm { 1686 compatible = "st,stm32-pwm-lp"; 1687 #pwm-cells = <3>; 1688 status = "disabled"; 1689 }; 1690 1691 trigger@1 { 1692 compatible = "st,stm32-lptimer-trigger"; 1693 reg = <1>; 1694 status = "disabled"; 1695 }; 1696 1697 counter { 1698 compatible = "st,stm32-lptimer-counter"; 1699 status = "disabled"; 1700 }; 1701 }; 1702 1703 lptimer3: timer@50022000 { 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 compatible = "st,stm32-lptimer"; 1707 reg = <0x50022000 0x400>; 1708 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1709 clocks = <&rcc LPTIM3_K>; 1710 clock-names = "mux"; 1711 wakeup-source; 1712 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 1713 status = "disabled"; 1714 1715 pwm { 1716 compatible = "st,stm32-pwm-lp"; 1717 #pwm-cells = <3>; 1718 status = "disabled"; 1719 }; 1720 1721 trigger@2 { 1722 compatible = "st,stm32-lptimer-trigger"; 1723 reg = <2>; 1724 status = "disabled"; 1725 }; 1726 }; 1727 1728 lptimer4: timer@50023000 { 1729 compatible = "st,stm32-lptimer"; 1730 reg = <0x50023000 0x400>; 1731 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1732 clocks = <&rcc LPTIM4_K>; 1733 clock-names = "mux"; 1734 wakeup-source; 1735 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM4_ID>; 1736 status = "disabled"; 1737 1738 pwm { 1739 compatible = "st,stm32-pwm-lp"; 1740 #pwm-cells = <3>; 1741 status = "disabled"; 1742 }; 1743 }; 1744 1745 lptimer5: timer@50024000 { 1746 compatible = "st,stm32-lptimer"; 1747 reg = <0x50024000 0x400>; 1748 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1749 clocks = <&rcc LPTIM5_K>; 1750 clock-names = "mux"; 1751 wakeup-source; 1752 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM5_ID>; 1753 status = "disabled"; 1754 1755 pwm { 1756 compatible = "st,stm32-pwm-lp"; 1757 #pwm-cells = <3>; 1758 status = "disabled"; 1759 }; 1760 }; 1761 1762 vrefbuf: vrefbuf@50025000 { 1763 compatible = "st,stm32-vrefbuf"; 1764 reg = <0x50025000 0x8>; 1765 regulator-min-microvolt = <1500000>; 1766 regulator-max-microvolt = <2500000>; 1767 clocks = <&rcc VREF>; 1768 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 1769 status = "disabled"; 1770 }; 1771 1772 sai4: sai@50027000 { 1773 compatible = "st,stm32h7-sai"; 1774 #address-cells = <1>; 1775 #size-cells = <1>; 1776 ranges = <0 0x50027000 0x400>; 1777 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1778 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1779 resets = <&rcc SAI4_R>; 1780 access-controllers = <&etzpc STM32MP1_ETZPC_SAI4_ID>; 1781 status = "disabled"; 1782 1783 sai4a: audio-controller@50027004 { 1784 #sound-dai-cells = <0>; 1785 compatible = "st,stm32-sai-sub-a"; 1786 reg = <0x04 0x20>; 1787 clocks = <&rcc SAI4_K>; 1788 clock-names = "sai_ck"; 1789 dmas = <&dmamux1 99 0x400 0x01>; 1790 status = "disabled"; 1791 }; 1792 1793 sai4b: audio-controller@50027024 { 1794 #sound-dai-cells = <0>; 1795 compatible = "st,stm32-sai-sub-b"; 1796 reg = <0x24 0x20>; 1797 clocks = <&rcc SAI4_K>; 1798 clock-names = "sai_ck"; 1799 dmas = <&dmamux1 100 0x400 0x01>; 1800 status = "disabled"; 1801 }; 1802 }; 1803 1804 hash1: hash@54002000 { 1805 compatible = "st,stm32f756-hash"; 1806 reg = <0x54002000 0x400>; 1807 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1808 clocks = <&rcc HASH1>; 1809 resets = <&rcc HASH1_R>; 1810 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1811 dma-names = "in"; 1812 dma-maxburst = <2>; 1813 access-controllers = <&etzpc STM32MP1_ETZPC_HASH1_ID>; 1814 status = "disabled"; 1815 }; 1816 1817 rng1: rng@54003000 { 1818 compatible = "st,stm32-rng"; 1819 reg = <0x54003000 0x400>; 1820 clocks = <&rcc RNG1_K>; 1821 resets = <&rcc RNG1_R>; 1822 access-controllers = <&etzpc STM32MP1_ETZPC_RNG1_ID>; 1823 status = "disabled"; 1824 }; 1825 1826 fmc: memory-controller@58002000 { 1827 #address-cells = <2>; 1828 #size-cells = <1>; 1829 compatible = "st,stm32mp1-fmc2-ebi"; 1830 reg = <0x58002000 0x1000>; 1831 clocks = <&rcc FMC_K>; 1832 resets = <&rcc FMC_R>; 1833 access-controllers = <&etzpc STM32MP1_ETZPC_FMC_ID>; 1834 status = "disabled"; 1835 1836 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1837 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1838 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1839 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1840 <4 0 0x80000000 0x10000000>; /* NAND */ 1841 1842 nand-controller@4,0 { 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 compatible = "st,stm32mp1-fmc2-nfc"; 1846 reg = <4 0x00000000 0x1000>, 1847 <4 0x08010000 0x1000>, 1848 <4 0x08020000 0x1000>, 1849 <4 0x01000000 0x1000>, 1850 <4 0x09010000 0x1000>, 1851 <4 0x09020000 0x1000>; 1852 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1853 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1854 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1855 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1856 dma-names = "tx", "rx", "ecc"; 1857 status = "disabled"; 1858 }; 1859 }; 1860 1861 qspi: spi@58003000 { 1862 compatible = "st,stm32f469-qspi"; 1863 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1864 reg-names = "qspi", "qspi_mm"; 1865 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1866 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1867 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1868 dma-names = "tx", "rx"; 1869 clocks = <&rcc QSPI_K>; 1870 resets = <&rcc QSPI_R>; 1871 #address-cells = <1>; 1872 #size-cells = <0>; 1873 access-controllers = <&etzpc STM32MP1_ETZPC_QSPI_ID>; 1874 status = "disabled"; 1875 }; 1876 1877 ethernet0: ethernet@5800a000 { 1878 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1879 reg = <0x5800a000 0x2000>; 1880 reg-names = "stmmaceth"; 1881 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1882 interrupt-names = "macirq"; 1883 clock-names = "stmmaceth", 1884 "mac-clk-tx", 1885 "mac-clk-rx", 1886 "eth-ck", 1887 "ptp_ref", 1888 "ethstp"; 1889 clocks = <&rcc ETHMAC>, 1890 <&rcc ETHTX>, 1891 <&rcc ETHRX>, 1892 <&rcc ETHCK_K>, 1893 <&rcc ETHPTP_K>, 1894 <&rcc ETHSTP>; 1895 st,syscon = <&syscfg 0x4>; 1896 snps,mixed-burst; 1897 snps,pbl = <2>; 1898 snps,en-tx-lpi-clockgating; 1899 snps,axi-config = <&stmmac_axi_config_0>; 1900 snps,tso; 1901 access-controllers = <&etzpc STM32MP1_ETZPC_ETH_ID>; 1902 status = "disabled"; 1903 1904 stmmac_axi_config_0: stmmac-axi-config { 1905 snps,wr_osr_lmt = <0x7>; 1906 snps,rd_osr_lmt = <0x7>; 1907 snps,blen = <0 0 0 0 16 8 4>; 1908 }; 1909 }; 1910 1911 usart1: serial@5c000000 { 1912 compatible = "st,stm32h7-uart"; 1913 reg = <0x5c000000 0x400>; 1914 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1915 clocks = <&rcc USART1_K>; 1916 wakeup-source; 1917 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 1918 status = "disabled"; 1919 }; 1920 1921 spi6: spi@5c001000 { 1922 #address-cells = <1>; 1923 #size-cells = <0>; 1924 compatible = "st,stm32h7-spi"; 1925 reg = <0x5c001000 0x400>; 1926 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1927 clocks = <&rcc SPI6_K>; 1928 resets = <&rcc SPI6_R>; 1929 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1930 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1931 dma-names = "rx", "tx"; 1932 access-controllers = <&etzpc STM32MP1_ETZPC_SPI6_ID>; 1933 status = "disabled"; 1934 }; 1935 1936 i2c4: i2c@5c002000 { 1937 compatible = "st,stm32mp15-i2c"; 1938 reg = <0x5c002000 0x400>; 1939 interrupt-names = "event", "error"; 1940 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1942 clocks = <&rcc I2C4_K>; 1943 resets = <&rcc I2C4_R>; 1944 #address-cells = <1>; 1945 #size-cells = <0>; 1946 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1947 wakeup-source; 1948 i2c-analog-filter; 1949 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 1950 status = "disabled"; 1951 }; 1952 1953 iwdg1: watchdog@5c003000 { 1954 compatible = "st,stm32mp1-iwdg"; 1955 reg = <0x5C003000 0x400>; 1956 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1957 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 1958 clock-names = "pclk", "lsi"; 1959 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 1960 status = "disabled"; 1961 }; 1962 1963 i2c6: i2c@5c009000 { 1964 compatible = "st,stm32mp15-i2c"; 1965 reg = <0x5c009000 0x400>; 1966 interrupt-names = "event", "error"; 1967 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1969 clocks = <&rcc I2C6_K>; 1970 resets = <&rcc I2C6_R>; 1971 #address-cells = <1>; 1972 #size-cells = <0>; 1973 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1974 wakeup-source; 1975 i2c-analog-filter; 1976 access-controllers = <&etzpc STM32MP1_ETZPC_I2C6_ID>; 1977 status = "disabled"; 1978 }; 1979 }; 1980 }; 1981 1982 mlahb: ahb { 1983 compatible = "st,mlahb", "simple-bus"; 1984 #address-cells = <1>; 1985 #size-cells = <1>; 1986 ranges; 1987 dma-ranges = <0x00000000 0x38000000 0x10000>, 1988 <0x10000000 0x10000000 0x60000>, 1989 <0x30000000 0x30000000 0x60000>; 1990 1991 m4_rproc: m4@10000000 { 1992 compatible = "st,stm32mp1-m4"; 1993 reg = <0x10000000 0x40000>, 1994 <0x30000000 0x40000>, 1995 <0x38000000 0x10000>; 1996 resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; 1997 reset-names = "mcu_rst", "hold_boot"; 1998 st,syscfg-tz = <&rcc 0x000 0x1>; 1999 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 2000 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 2001 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 2002 status = "disabled"; 2003 }; 2004 }; 2005}; 2006