1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2018-2025, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <drivers/clk.h> 7 #include <drivers/clk_dt.h> 8 #include <drivers/rtc.h> 9 #include <drivers/stm32_rif.h> 10 #include <drivers/stm32_rtc.h> 11 #include <io.h> 12 #include <kernel/dt.h> 13 #include <kernel/dt_driver.h> 14 #include <kernel/panic.h> 15 #include <kernel/spinlock.h> 16 #include <libfdt.h> 17 #include <mm/core_memprot.h> 18 19 /* 20 * Registers 21 */ 22 #define RTC_TR U(0x00) 23 #define RTC_DR U(0x04) 24 #define RTC_SSR U(0x08) 25 #define RTC_ICSR U(0x0C) 26 #define RTC_PRER U(0x10) 27 #define RTC_WUTR U(0x14) 28 #define RTC_CR U(0x18) 29 #define RTC_PRIVCFGR U(0x1C) 30 /* RTC_SMCR is linked to RTC3v1_2 */ 31 #define RTC_SMCR U(0x20) 32 /* RTC_SECCFGR is linked to RTC3v3_2 and above */ 33 #define RTC_SECCFGR U(0x20) 34 #define RTC_WPR U(0x24) 35 #define RTC_CALR U(0x28) 36 #define RTC_SHIFTR U(0x2C) 37 #define RTC_TSTR U(0x30) 38 #define RTC_TSDR U(0x34) 39 #define RTC_TSSSR U(0x38) 40 #define RTC_ALRMAR U(0x40) 41 #define RTC_ALRMASSR U(0x44) 42 #define RTC_ALRMBR U(0x48) 43 #define RTC_ALRMBSSR U(0x4C) 44 #define RTC_SR U(0x50) 45 #define RTC_SCR U(0x5C) 46 #define RTC_OR U(0x60) 47 #define RTC_CIDCFGR(x) (U(0x80) + U(0x4) * (x)) 48 49 #define RTC_TR_SU_MASK GENMASK_32(3, 0) 50 #define RTC_TR_ST_MASK GENMASK_32(6, 4) 51 #define RTC_TR_ST_SHIFT U(4) 52 #define RTC_TR_MNU_MASK GENMASK_32(11, 8) 53 #define RTC_TR_MNU_SHIFT U(8) 54 #define RTC_TR_MNT_MASK GENMASK_32(14, 12) 55 #define RTC_TR_MNT_SHIFT U(12) 56 #define RTC_TR_HU_MASK GENMASK_32(19, 16) 57 #define RTC_TR_HU_SHIFT U(16) 58 #define RTC_TR_HT_MASK GENMASK_32(21, 20) 59 #define RTC_TR_HT_SHIFT U(20) 60 #define RTC_TR_PM BIT(22) 61 62 #define RTC_DR_DU_MASK GENMASK_32(3, 0) 63 #define RTC_DR_DT_MASK GENMASK_32(5, 4) 64 #define RTC_DR_DT_SHIFT U(4) 65 #define RTC_DR_MU_MASK GENMASK_32(11, 8) 66 #define RTC_DR_MU_SHIFT U(8) 67 #define RTC_DR_MT_MASK BIT(12) 68 #define RTC_DR_MT_SHIFT U(12) 69 #define RTC_DR_WDU_MASK GENMASK_32(15, 13) 70 #define RTC_DR_WDU_SHIFT U(13) 71 #define RTC_DR_YU_MASK GENMASK_32(19, 16) 72 #define RTC_DR_YU_SHIFT U(16) 73 #define RTC_DR_YT_MASK GENMASK_32(23, 20) 74 #define RTC_DR_YT_SHIFT U(20) 75 76 #define RTC_SSR_SS_MASK GENMASK_32(15, 0) 77 78 #define RTC_ICSR_RSF BIT(5) 79 #define RTC_ICSR_INITF BIT(6) 80 #define RTC_ICSR_INIT BIT(7) 81 82 #define RTC_PRER_PREDIV_S_SHIFT U(0) 83 #define RTC_PRER_PREDIV_S_MASK GENMASK_32(14, 0) 84 #define RTC_PRER_PREDIV_A_SHIFT U(16) 85 #define RTC_PRER_PREDIV_A_MASK GENMASK_32(22, 16) 86 87 #define RTC_CR_BYPSHAD BIT(5) 88 #define RTC_CR_BYPSHAD_SHIFT U(5) 89 #define RTC_CR_FMT BIT(6) 90 #define RTC_CR_TAMPTS BIT(25) 91 92 #define RTC_PRIVCFGR_VALUES GENMASK_32(3, 0) 93 #define RTC_PRIVCFGR_VALUES_TO_SHIFT GENMASK_32(5, 4) 94 #define RTC_PRIVCFGR_SHIFT U(9) 95 #define RTC_PRIVCFGR_MASK (GENMASK_32(14, 13) | GENMASK_32(3, 0)) 96 #define RTC_PRIVCFGR_FULL_PRIV BIT(15) 97 98 #define RTC_SMCR_TS_DPROT BIT(3) 99 100 #define RTC_SECCFGR_VALUES GENMASK_32(3, 0) 101 #define RTC_SECCFGR_TS_SEC BIT(3) 102 #define RTC_SECCFGR_VALUES_TO_SHIFT GENMASK_32(5, 4) 103 #define RTC_SECCFGR_SHIFT U(9) 104 #define RTC_SECCFGR_MASK (GENMASK_32(14, 13) | GENMASK_32(3, 0)) 105 #define RTC_SECCFGR_FULL_SEC BIT(15) 106 107 #define RTC_WPR_KEY1 U(0xCA) 108 #define RTC_WPR_KEY2 U(0x53) 109 #define RTC_WPR_KEY_LOCK U(0xFF) 110 111 #define RTC_TSDR_MU_MASK GENMASK_32(11, 8) 112 #define RTC_TSDR_MU_SHIFT U(8) 113 #define RTC_TSDR_DT_MASK GENMASK_32(5, 4) 114 #define RTC_TSDR_DT_SHIFT U(4) 115 #define RTC_TSDR_DU_MASK GENMASK_32(3, 0) 116 #define RTC_TSDR_DU_SHIFT U(0) 117 118 #define RTC_SR_TSF BIT(3) 119 #define RTC_SR_TSOVF BIT(4) 120 121 #define RTC_SCR_CTSF BIT(3) 122 #define RTC_SCR_CTSOVF BIT(4) 123 124 #define RTC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 125 #define RTC_CIDCFGR_SCID_MASK_SHIFT U(4) 126 #define RTC_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \ 127 RTC_CIDCFGR_SCID_MASK) 128 129 /* 130 * RIF miscellaneous 131 */ 132 #define RTC_NB_RIF_RESOURCES U(6) 133 134 #define RTC_RIF_FULL_PRIVILEGED U(0x3F) 135 #define RTC_RIF_FULL_SECURED U(0x3F) 136 137 #define RTC_NB_MAX_CID_SUPPORTED U(7) 138 139 /* 140 * Driver miscellaneous 141 */ 142 #define RTC_RES_TIMESTAMP U(3) 143 #define RTC_RES_CALIBRATION U(4) 144 #define RTC_RES_INITIALIZATION U(5) 145 146 #define RTC_FLAGS_READ_TWICE BIT(0) 147 148 #define TIMEOUT_US_RTC_SHADOW U(10000) 149 #define TIMEOUT_US_RTC_GENERIC U(100000) 150 151 #define YEAR_REF ULL(2000) 152 #define YEAR_MAX (YEAR_REF + ULL(99)) 153 154 struct rtc_compat { 155 bool has_seccfgr; 156 bool has_rif_support; 157 }; 158 159 /* 160 * struct rtc_device - RTC device data 161 * @base: RTC IOMEM base address 162 * @compat: RTC compatible data 163 * @pclk: RTC bus clock 164 * @rtc_ck: RTC kernel clock 165 * @conf_data: RTC RIF configuration data, when supported 166 * @nb_res: Number of protectible RTC resources 167 * @ts_lock: Lock used for time stamping events handling 168 * @flags: RTC driver flags 169 * @is_secured: True if the RTC is fully secured 170 */ 171 struct rtc_device { 172 struct io_pa_va base; 173 const struct rtc_compat *compat; 174 struct clk *pclk; 175 struct clk *rtc_ck; 176 struct rif_conf_data *conf_data; 177 unsigned int nb_res; 178 unsigned int ts_lock; 179 uint8_t flags; 180 bool is_secured; 181 }; 182 183 /* Expect a single RTC instance */ 184 static struct rtc_device rtc_dev; 185 186 static vaddr_t get_base(void) 187 { 188 assert(rtc_dev.base.pa); 189 190 return io_pa_or_va(&rtc_dev.base, 1); 191 } 192 193 static void stm32_rtc_write_unprotect(void) 194 { 195 vaddr_t rtc_base = get_base(); 196 197 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY1); 198 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY2); 199 } 200 201 static void stm32_rtc_write_protect(void) 202 { 203 vaddr_t rtc_base = get_base(); 204 205 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY_LOCK); 206 } 207 208 static bool stm32_rtc_get_bypshad(void) 209 { 210 return io_read32(get_base() + RTC_CR) & RTC_CR_BYPSHAD; 211 } 212 213 /* Get the subsecond value. */ 214 static uint32_t stm32_rtc_get_subsecond(uint32_t ssr) 215 { 216 uint32_t prediv_s = io_read32(get_base() + RTC_PRER) & 217 RTC_PRER_PREDIV_S_MASK; 218 219 return prediv_s - ssr; 220 } 221 222 /* 223 * Get the subsecond scale. 224 * 225 * Number of subseconds in a second is linked to RTC PREDIV_S value. 226 * The higher PREDIV_S is, the more subsecond is precise. 227 */ 228 static uint32_t stm32_rtc_get_subsecond_scale(void) 229 { 230 return (io_read32(get_base() + RTC_PRER) & RTC_PRER_PREDIV_S_MASK) + 1; 231 } 232 233 static bool cid1_has_access(unsigned int resource) 234 { 235 uint32_t cidcfgr = io_read32(get_base() + RTC_CIDCFGR(resource)); 236 237 return !(cidcfgr & _CIDCFGR_CFEN) || 238 get_field_u32(cidcfgr, RTC_CIDCFGR_SCID_MASK) == RIF_CID1; 239 } 240 241 static TEE_Result check_rif_config(void) 242 { 243 if (!cid1_has_access(RTC_RES_TIMESTAMP) || 244 !cid1_has_access(RTC_RES_CALIBRATION) || 245 !cid1_has_access(RTC_RES_INITIALIZATION)) 246 return TEE_ERROR_ACCESS_DENIED; 247 248 return TEE_SUCCESS; 249 } 250 251 static void apply_rif_config(bool is_tdcid) 252 { 253 vaddr_t base = get_base(); 254 unsigned int shifted_values = 0; 255 uint32_t seccfgr = 0; 256 uint32_t privcfgr = 0; 257 uint32_t access_mask_reg = 0; 258 unsigned int i = 0; 259 260 if (!rtc_dev.conf_data) 261 return; 262 263 /* Build access mask for RTC_SECCFGR and RTC_PRIVCFGR */ 264 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 265 if (rtc_dev.conf_data->access_mask[0] & BIT(i)) { 266 if (i <= RTC_RES_TIMESTAMP) 267 access_mask_reg |= BIT(i); 268 else 269 access_mask_reg |= BIT(i) << RTC_SECCFGR_SHIFT; 270 } 271 } 272 273 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 274 if (!(BIT(i) & rtc_dev.conf_data->access_mask[0])) 275 continue; 276 277 /* 278 * When TDCID, OP-TEE should be the one to set the CID filtering 279 * configuration. Clearing previous configuration prevents 280 * undesired events during the only legitimate configuration. 281 */ 282 if (is_tdcid) 283 io_clrbits32(base + RTC_CIDCFGR(i), 284 RTC_CIDCFGR_CONF_MASK); 285 } 286 287 /* Security RIF configuration */ 288 seccfgr = rtc_dev.conf_data->sec_conf[0]; 289 290 /* Check if all resources must be secured */ 291 if (seccfgr == RTC_RIF_FULL_SECURED) { 292 io_setbits32(base + RTC_SECCFGR, RTC_SECCFGR_FULL_SEC); 293 rtc_dev.is_secured = true; 294 295 if (!(io_read32(base + RTC_SECCFGR) & RTC_SECCFGR_FULL_SEC)) 296 panic("Bad RTC seccfgr configuration"); 297 } 298 299 /* Shift some values to align with the register */ 300 shifted_values = SHIFT_U32(seccfgr & RTC_SECCFGR_VALUES_TO_SHIFT, 301 RTC_SECCFGR_SHIFT); 302 seccfgr = (seccfgr & RTC_SECCFGR_VALUES) + shifted_values; 303 304 io_clrsetbits32(base + RTC_SECCFGR, 305 RTC_SECCFGR_MASK & access_mask_reg, seccfgr); 306 307 /* Privilege RIF configuration */ 308 privcfgr = rtc_dev.conf_data->priv_conf[0]; 309 310 /* Check if all resources must be privileged */ 311 if (privcfgr == RTC_RIF_FULL_PRIVILEGED) { 312 io_setbits32(base + RTC_PRIVCFGR, RTC_PRIVCFGR_FULL_PRIV); 313 314 if (!(io_read32(base + RTC_PRIVCFGR) & RTC_PRIVCFGR_FULL_PRIV)) 315 panic("Bad RTC privcfgr configuration"); 316 } 317 318 /* Shift some values to align with the register */ 319 shifted_values = SHIFT_U32(privcfgr & RTC_PRIVCFGR_VALUES_TO_SHIFT, 320 RTC_PRIVCFGR_SHIFT); 321 privcfgr = (privcfgr & RTC_PRIVCFGR_VALUES) + shifted_values; 322 323 io_clrsetbits32(base + RTC_PRIVCFGR, 324 RTC_PRIVCFGR_MASK & access_mask_reg, privcfgr); 325 326 if (!is_tdcid) 327 return; 328 329 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 330 if (!(BIT(i) & rtc_dev.conf_data->access_mask[0])) 331 continue; 332 /* 333 * When at least one resource has CID filtering enabled, 334 * the RTC_PRIVCFGR_FULL_PRIV and RTC_SECCFGR_FULL_SEC bits are 335 * cleared. 336 */ 337 io_clrsetbits32(base + RTC_CIDCFGR(i), 338 RTC_CIDCFGR_CONF_MASK, 339 rtc_dev.conf_data->cid_confs[i]); 340 } 341 } 342 343 static TEE_Result parse_dt(const void *fdt, int node) 344 { 345 TEE_Result res = TEE_ERROR_GENERIC; 346 const fdt32_t *cuint = NULL; 347 size_t reg_size = 0; 348 unsigned int i = 0; 349 int lenp = 0; 350 351 if (fdt_reg_info(fdt, node, &rtc_dev.base.pa, ®_size)) 352 panic(); 353 354 io_pa_or_va(&rtc_dev.base, reg_size); 355 assert(rtc_dev.base.va); 356 357 res = clk_dt_get_by_name(fdt, node, "pclk", &rtc_dev.pclk); 358 if (res) 359 return res; 360 361 res = clk_dt_get_by_name(fdt, node, "rtc_ck", &rtc_dev.rtc_ck); 362 if (res) 363 return res; 364 365 if (!rtc_dev.compat->has_rif_support) 366 return TEE_SUCCESS; 367 368 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 369 if (!cuint) { 370 DMSG("No RIF configuration available"); 371 return TEE_SUCCESS; 372 } 373 374 rtc_dev.conf_data = calloc(1, sizeof(*rtc_dev.conf_data)); 375 if (!rtc_dev.conf_data) 376 panic(); 377 378 rtc_dev.nb_res = (unsigned int)(lenp / sizeof(uint32_t)); 379 assert(rtc_dev.nb_res <= RTC_NB_RIF_RESOURCES); 380 381 rtc_dev.conf_data->cid_confs = calloc(RTC_NB_RIF_RESOURCES, 382 sizeof(uint32_t)); 383 rtc_dev.conf_data->sec_conf = calloc(1, sizeof(uint32_t)); 384 rtc_dev.conf_data->priv_conf = calloc(1, sizeof(uint32_t)); 385 rtc_dev.conf_data->access_mask = calloc(1, sizeof(uint32_t)); 386 if (!rtc_dev.conf_data->cid_confs || !rtc_dev.conf_data->sec_conf || 387 !rtc_dev.conf_data->priv_conf || !rtc_dev.conf_data->access_mask) 388 panic("Not enough memory capacity for RTC RIF config"); 389 390 for (i = 0; i < rtc_dev.nb_res; i++) 391 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), rtc_dev.conf_data, 392 RTC_NB_RIF_RESOURCES); 393 394 return TEE_SUCCESS; 395 } 396 397 static TEE_Result stm32_rtc_enter_init_mode(void) 398 { 399 vaddr_t base = get_base(); 400 uint32_t icsr = io_read32(base + RTC_ICSR); 401 uint32_t value = 0; 402 403 if (!(icsr & RTC_ICSR_INITF)) { 404 icsr |= RTC_ICSR_INIT; 405 io_write32(base + RTC_ICSR, icsr); 406 407 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, value, 408 value & RTC_ICSR_INITF, 409 10, TIMEOUT_US_RTC_GENERIC)) 410 return TEE_ERROR_BUSY; 411 } 412 413 return TEE_SUCCESS; 414 } 415 416 static TEE_Result stm32_rtc_exit_init_mode(void) 417 { 418 vaddr_t base = get_base(); 419 uint32_t value = 0; 420 421 io_clrbits32(base + RTC_ICSR, RTC_ICSR_INIT); 422 dsb(); 423 424 io_clrbits32(base + RTC_ICSR, RTC_ICSR_RSF); 425 426 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, value, 427 value & RTC_ICSR_RSF, 10, 428 TIMEOUT_US_RTC_GENERIC)) 429 return TEE_ERROR_BUSY; 430 431 return TEE_SUCCESS; 432 } 433 434 static void stm32_rtc_to_tm(uint32_t ssr, uint32_t tr, uint32_t dr, 435 struct optee_rtc_time *tm) 436 { 437 tm->tm_hour = ((tr & RTC_TR_HT_MASK) >> RTC_TR_HT_SHIFT) * 10 + 438 ((tr & RTC_TR_HU_MASK) >> RTC_TR_HU_SHIFT); 439 440 if (tr & RTC_TR_PM) 441 tm->tm_hour += 12; 442 443 tm->tm_ms = (stm32_rtc_get_subsecond(ssr) * MS_PER_SEC) / 444 stm32_rtc_get_subsecond_scale(); 445 446 tm->tm_sec = ((tr & RTC_TR_ST_MASK) >> RTC_TR_ST_SHIFT) * 10 + 447 (tr & RTC_TR_SU_MASK); 448 449 tm->tm_min = ((tr & RTC_TR_MNT_MASK) >> RTC_TR_MNT_SHIFT) * 10 + 450 ((tr & RTC_TR_MNU_MASK) >> RTC_TR_MNU_SHIFT); 451 452 tm->tm_wday = ((dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT) % 7; 453 454 tm->tm_mday = ((dr & RTC_DR_DT_MASK) >> RTC_DR_DT_SHIFT) * 10 + 455 (dr & RTC_DR_DU_MASK); 456 457 tm->tm_mon = ((dr & RTC_DR_MT_MASK) >> RTC_DR_MT_SHIFT) * 10 + 458 ((dr & RTC_DR_MU_MASK) >> RTC_DR_MU_SHIFT) - 1; 459 460 tm->tm_year = ((dr & RTC_DR_YT_MASK) >> RTC_DR_YT_SHIFT) * 10 + 461 ((dr & RTC_DR_YU_MASK) >> RTC_DR_YU_SHIFT) + YEAR_REF; 462 } 463 464 static TEE_Result stm32_rtc_init(void) 465 { 466 uint32_t pred_a_max = RTC_PRER_PREDIV_A_MASK >> RTC_PRER_PREDIV_A_SHIFT; 467 uint32_t pred_s_max = RTC_PRER_PREDIV_S_MASK >> RTC_PRER_PREDIV_S_SHIFT; 468 unsigned long rate = clk_get_rate(rtc_dev.rtc_ck); 469 TEE_Result res = TEE_ERROR_GENERIC; 470 vaddr_t base = get_base(); 471 uint32_t pred_a = 0; 472 uint32_t pred_s = 0; 473 uint32_t prer = io_read32(base + RTC_PRER); 474 uint32_t cr = io_read32(base + RTC_CR); 475 476 if (rate > (pred_a_max + 1) * (pred_s_max + 1)) 477 panic("rtc_ck rate is too high"); 478 479 if (cr & RTC_CR_FMT && !IS_ENABLED(CFG_STM32_RTC_HIGH_ACCURACY)) 480 return TEE_SUCCESS; 481 482 if (IS_ENABLED(CFG_STM32_RTC_HIGH_ACCURACY)) { 483 /* 484 * Compute the prescaler values whom divides the clock in order 485 * to get a * 1 Hz output by maximizing accuracy 486 * (maximizing PREDIV_S). 487 */ 488 for (pred_a = 0; pred_a <= pred_a_max; pred_a++) { 489 pred_s = (rate / (pred_a + 1)) - 1; 490 if (pred_s <= pred_s_max && 491 ((pred_s + 1) * (pred_a + 1)) == rate) 492 break; 493 } 494 495 /* 496 * 1 Hz output not possible, give priority to RTC power 497 * consumption by choosing the higher possible value for 498 * prediv_a 499 */ 500 if (pred_s > pred_s_max || pred_a > pred_a_max) { 501 pred_a = pred_a_max; 502 pred_s = (rate / (pred_a + 1)) - 1; 503 504 DMSG("rtc_ck is %s", 505 (rate < ((pred_a + 1) * (pred_s + 1))) ? 506 "fast" : "slow"); 507 } 508 509 prer &= RTC_PRER_PREDIV_S_MASK | RTC_PRER_PREDIV_A_MASK; 510 pred_s = SHIFT_U32(pred_s, RTC_PRER_PREDIV_S_SHIFT) & 511 RTC_PRER_PREDIV_S_MASK; 512 pred_a = SHIFT_U32(pred_a, RTC_PRER_PREDIV_A_SHIFT) & 513 RTC_PRER_PREDIV_A_MASK; 514 515 /* Return if there is nothing to initialize */ 516 if (cr & RTC_CR_FMT && prer == (pred_s | pred_a)) 517 return TEE_SUCCESS; 518 } 519 520 stm32_rtc_write_unprotect(); 521 522 res = stm32_rtc_enter_init_mode(); 523 if (res) { 524 EMSG("Can't enter init mode. Fail to initialize RTC."); 525 stm32_rtc_write_protect(); 526 return res; 527 } 528 529 if (IS_ENABLED(CFG_STM32_RTC_HIGH_ACCURACY)) { 530 io_write32(base + RTC_PRER, pred_s); 531 io_write32(base + RTC_PRER, pred_a | pred_s); 532 } 533 534 /* Force 24h time format */ 535 cr &= ~RTC_CR_FMT; 536 io_write32(base + RTC_CR, cr); 537 538 res = stm32_rtc_exit_init_mode(); 539 if (res) 540 EMSG("Can't exit init mode. Fail to initialize RTC."); 541 542 stm32_rtc_write_protect(); 543 544 return res; 545 } 546 547 static TEE_Result stm32_rtc_get_time(struct rtc *rtc __unused, 548 struct optee_rtc_time *tm) 549 { 550 vaddr_t base = get_base(); 551 uint32_t ssr = 0; 552 uint32_t dr = 0; 553 uint32_t tr = 0; 554 555 if (!stm32_rtc_get_bypshad()) { 556 uint32_t icsr = 0; 557 558 /* Wait calendar registers are ready */ 559 io_clrbits32(base + RTC_ICSR, RTC_ICSR_RSF); 560 561 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, icsr, 562 icsr & RTC_ICSR_RSF, 0, 563 TIMEOUT_US_RTC_SHADOW)) 564 panic(); 565 } 566 567 /* 568 * In our RTC we start : 569 * - year at 0 570 * - month at 1 571 * - day at 1 572 * - weekday at Monday = 1 573 * Change month value so it becomes 0=January, 1 = February, ... 574 * Change week day value so it becomes 0=Sunday, 1 = Monday, ... 575 */ 576 577 ssr = io_read32(base + RTC_SSR); 578 tr = io_read32(base + RTC_TR); 579 dr = io_read32(base + RTC_DR); 580 581 stm32_rtc_to_tm(ssr, tr, dr, tm); 582 583 return TEE_SUCCESS; 584 } 585 586 static TEE_Result stm32_rtc_set_time(struct rtc *rtc, struct optee_rtc_time *tm) 587 { 588 TEE_Result res = TEE_ERROR_GENERIC; 589 vaddr_t rtc_base = get_base(); 590 uint32_t tr = 0; 591 uint32_t dr = 0; 592 593 /* 594 * In our RTC we start : 595 * - year at 0 596 * - month at 1 597 * - day at 1 598 * - weekday at Monday = 1 599 * Change month value so it becomes 1=January, 2 = February, ... 600 * Change week day value so it becomes 7=Sunday, 1 = Monday, ... 601 */ 602 tr = ((tm->tm_sec % 10) & RTC_TR_SU_MASK) | 603 (SHIFT_U32(tm->tm_sec / 10, RTC_TR_ST_SHIFT) & RTC_TR_ST_MASK) | 604 (SHIFT_U32(tm->tm_min % 10, RTC_TR_MNU_SHIFT) & RTC_TR_MNU_MASK) | 605 (SHIFT_U32(tm->tm_min / 10, RTC_TR_MNT_SHIFT) & RTC_TR_MNT_MASK) | 606 (SHIFT_U32(tm->tm_hour % 10, RTC_TR_HU_SHIFT) & RTC_TR_HU_MASK) | 607 (SHIFT_U32(tm->tm_hour / 10, RTC_TR_HT_SHIFT) & RTC_TR_HT_MASK); 608 609 dr = ((tm->tm_mday % 10) & RTC_DR_DU_MASK) | 610 (SHIFT_U32(tm->tm_mday / 10, RTC_DR_DT_SHIFT) & RTC_DR_DT_MASK) | 611 (SHIFT_U32((tm->tm_mon + 1) % 10, RTC_DR_MU_SHIFT) & 612 RTC_DR_MU_MASK) | 613 (SHIFT_U32((tm->tm_mon + 1) / 10, RTC_DR_MT_SHIFT) & 614 RTC_DR_MT_MASK) | 615 (SHIFT_U32(tm->tm_wday ? tm->tm_wday : 7, RTC_DR_WDU_SHIFT) & 616 RTC_DR_WDU_MASK) | 617 (SHIFT_U32((tm->tm_year - rtc->range_min.tm_year) % 10, 618 RTC_DR_YU_SHIFT) & RTC_DR_YU_MASK) | 619 (SHIFT_U32((tm->tm_year - rtc->range_min.tm_year) / 10, 620 RTC_DR_YT_SHIFT) & RTC_DR_YT_MASK); 621 622 stm32_rtc_write_unprotect(); 623 624 res = stm32_rtc_enter_init_mode(); 625 if (res) 626 goto end; 627 628 io_write32(rtc_base + RTC_TR, tr); 629 io_write32(rtc_base + RTC_DR, dr); 630 631 res = stm32_rtc_exit_init_mode(); 632 end: 633 stm32_rtc_write_protect(); 634 635 return res; 636 } 637 638 TEE_Result stm32_rtc_get_timestamp(struct optee_rtc_time *tm) 639 { 640 vaddr_t base = get_base(); 641 uint32_t exceptions = 0; 642 uint32_t value = 0; 643 uint32_t ssr = 0; 644 uint32_t dr = 0; 645 uint32_t tr = 0; 646 647 exceptions = cpu_spin_lock_xsave(&rtc_dev.ts_lock); 648 649 if (IO_READ32_POLL_TIMEOUT(base + RTC_SR, value, 650 value & RTC_SR_TSF, 651 10, TIMEOUT_US_RTC_GENERIC)) { 652 cpu_spin_unlock_xrestore(&rtc_dev.ts_lock, exceptions); 653 return TEE_ERROR_NO_DATA; 654 } 655 656 ssr = io_read32(base + RTC_TSSSR); 657 tr = io_read32(base + RTC_TSTR); 658 dr = io_read32(base + RTC_TSDR); 659 660 io_setbits32(base + RTC_SCR, RTC_SCR_CTSF); 661 662 /* Tamper event overflow detection */ 663 if (io_read32(base + RTC_SR) & RTC_SR_TSOVF) { 664 io_setbits32(base + RTC_SCR, RTC_SCR_CTSOVF); 665 DMSG("A timestamp event occurred while handling current event"); 666 } 667 668 cpu_spin_unlock_xrestore(&rtc_dev.ts_lock, exceptions); 669 670 stm32_rtc_to_tm(ssr, tr, dr, tm); 671 672 /* No year timestamp available */ 673 tm->tm_year = 0; 674 675 return TEE_SUCCESS; 676 } 677 678 TEE_Result stm32_rtc_set_tamper_timestamp(void) 679 { 680 vaddr_t base = get_base(); 681 682 stm32_rtc_write_unprotect(); 683 684 /* Secure Timestamp bit */ 685 if (!rtc_dev.compat->has_seccfgr) { 686 /* Inverted logic */ 687 io_clrbits32(base + RTC_SMCR, RTC_SMCR_TS_DPROT); 688 } else { 689 io_setbits32(base + RTC_SECCFGR, RTC_SECCFGR_TS_SEC); 690 } 691 692 /* Enable tamper timestamper */ 693 io_setbits32(base + RTC_CR, RTC_CR_TAMPTS); 694 695 stm32_rtc_write_protect(); 696 697 return TEE_SUCCESS; 698 } 699 700 TEE_Result stm32_rtc_is_timestamp_enabled(bool *ret) 701 { 702 *ret = io_read32(get_base() + RTC_CR) & RTC_CR_TAMPTS; 703 704 return TEE_SUCCESS; 705 } 706 707 TEE_Result stm32_rtc_driver_is_initialized(void) 708 { 709 if (rtc_dev.pclk) 710 return TEE_SUCCESS; 711 712 return TEE_ERROR_DEFER_DRIVER_INIT; 713 } 714 715 static const struct rtc_ops stm32_rtc_ops = { 716 .get_time = stm32_rtc_get_time, 717 .set_time = stm32_rtc_set_time, 718 }; 719 720 static struct rtc stm32_rtc = { 721 .ops = &stm32_rtc_ops, 722 .range_min = RTC_TIME(YEAR_REF, 0, 1, 0, 0, 0, 0, 0), 723 .range_max = RTC_TIME(YEAR_MAX, 11, 31, 4, 23, 59, 59, 999), 724 }; 725 726 static TEE_Result stm32_rtc_probe(const void *fdt, int node, 727 const void *compat_data) 728 { 729 TEE_Result res = TEE_ERROR_GENERIC; 730 bool is_tdcid = false; 731 732 rtc_dev.compat = compat_data; 733 734 if (rtc_dev.compat->has_rif_support) { 735 res = stm32_rifsc_check_tdcid(&is_tdcid); 736 if (res) 737 return res; 738 } 739 740 res = parse_dt(fdt, node); 741 if (res) { 742 memset(&rtc_dev, 0, sizeof(rtc_dev)); 743 return res; 744 } 745 746 /* Unbalanced clock enable to ensure RTC core clock is always on */ 747 res = clk_enable(rtc_dev.rtc_ck); 748 if (res) 749 panic("Couldn't enable RTC clock"); 750 751 if (clk_get_rate(rtc_dev.pclk) < (clk_get_rate(rtc_dev.rtc_ck) * 7)) 752 rtc_dev.flags |= RTC_FLAGS_READ_TWICE; 753 754 if (rtc_dev.compat->has_rif_support) { 755 res = clk_enable(rtc_dev.pclk); 756 if (res) 757 panic("Could not enable RTC bus clock"); 758 759 apply_rif_config(is_tdcid); 760 761 /* 762 * Verify if applied RIF config will not disable 763 * other functionalities of this driver. 764 */ 765 res = check_rif_config(); 766 if (res) 767 panic("Incompatible RTC RIF configuration"); 768 769 clk_disable(rtc_dev.pclk); 770 } 771 772 res = stm32_rtc_init(); 773 if (res) 774 return res; 775 rtc_register(&stm32_rtc); 776 777 return res; 778 } 779 780 static const struct rtc_compat mp25_compat = { 781 .has_seccfgr = true, 782 .has_rif_support = true, 783 }; 784 785 static const struct rtc_compat mp15_compat = { 786 .has_seccfgr = false, 787 .has_rif_support = false, 788 }; 789 790 static const struct rtc_compat mp13_compat = { 791 .has_seccfgr = true, 792 .has_rif_support = false, 793 }; 794 795 static const struct dt_device_match stm32_rtc_match_table[] = { 796 { 797 .compatible = "st,stm32mp25-rtc", 798 .compat_data = &mp25_compat, 799 }, 800 { 801 .compatible = "st,stm32mp1-rtc", 802 .compat_data = &mp15_compat, 803 }, 804 { 805 .compatible = "st,stm32mp13-rtc", 806 .compat_data = &mp13_compat, 807 }, 808 { } 809 }; 810 811 DEFINE_DT_DRIVER(stm32_rtc_dt_driver) = { 812 .name = "stm32-rtc", 813 .match_table = stm32_rtc_match_table, 814 .probe = stm32_rtc_probe, 815 }; 816