| faaa1735 | 02-Feb-2022 |
Nicolas Toromanoff <nicolas.toromanoff@foss.st.com> |
plat-stm32mp1: add new API to erase SRAM3
Add new API TEE_Result stm32mp_syscfg_erase_sram3(void);
to be able to erase SRAM3 by hardware request.
Signed-off-by: Nicolas Toromanoff <nicolas.toromano
plat-stm32mp1: add new API to erase SRAM3
Add new API TEE_Result stm32mp_syscfg_erase_sram3(void);
to be able to erase SRAM3 by hardware request.
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| fd6434ee | 11-May-2023 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
plat-stm32mp1: syscfg: add dsb in syscfg driver
Add dsb in syscfg driver to guarantee that the request operations
are performed in SYSCFG register when the external API are called
and before to retu
plat-stm32mp1: syscfg: add dsb in syscfg driver
Add dsb in syscfg driver to guarantee that the request operations
are performed in SYSCFG register when the external API are called
and before to return to caller:
- stm32mp1_iocomp() in init sequence
- stm32mp_set_vddsd_comp_state() and stm32mp_set_hslv_state()
called by PWR driver
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 161f5876 | 13-Feb-2025 |
Thomas Bourgoin <thomas.bourgoin@foss.st.com> |
plat-stm32mp1: syscfg: set SYSCFG_CMPCR_READY_TIMEOUT_US to 10ms
CHange timeout to 10 ms instead of 1 ms.
On stm32mp13 we measure 1.5ms delay to have CMPCR_READY equal to 1.
Use 10 ms to be aligned
plat-stm32mp1: syscfg: set SYSCFG_CMPCR_READY_TIMEOUT_US to 10ms
CHange timeout to 10 ms instead of 1 ms.
On stm32mp13 we measure 1.5ms delay to have CMPCR_READY equal to 1.
Use 10 ms to be aligned with TF-A timeout.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| e29eb9dd | 17-Jun-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp1: implement do_reset() API to force a system reset
Implement the do_reset() API that traps all cores if the SoC has multiple
cores, then prints a message and forces a system reset.
Sig
plat-stm32mp1: implement do_reset() API to force a system reset
Implement the do_reset() API that traps all cores if the SoC has multiple
cores, then prints a message and forces a system reset.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 7653887e | 18-Jun-2025 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
core: panic: allow core halting on SGI in other cases than panic()
There may be cases where we want to halt several cores outside of a
panic() sequence.
Therefore, add CFG_MULTI_CORE_HALTING switch
core: panic: allow core halting on SGI in other cases than panic()
There may be cases where we want to halt several cores outside of a
panic() sequence.
Therefore, add CFG_MULTI_CORE_HALTING switch that allows to register
an interrupt handler for the CFG_HALT_CORES_SGI that is dedicated to
halt other cores.
This reduces the scope of CFG_HALT_CORES_ON_PANIC that is now used only
for halting other cores in a panic() sequence.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 446da993 | 27-Jun-2025 |
Clément Le Goffic <clement.legoffic@foss.st.com> |
drivers: stm32_rtc: add init configuration function
The init function aims to contains init configurations of the RTC
peripheral such as prescalers, config or calibration registers.
Add "CFG_STM32_H
drivers: stm32_rtc: add init configuration function
The init function aims to contains init configurations of the RTC
peripheral such as prescalers, config or calibration registers.
Add "CFG_STM32_HIGH_ACCURACY" (default to no) config to enable the
high accuracy mode which allow the highest refresh rate of the subsecond
register.
Also merge the functions `stm32_rtc_wait_sync()` with
`stm32_exit_init_mode()` as every stm32 exit init mode was followed
by a wait sync.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 9b745e16 | 04-Mar-2024 |
Clément Le Goffic <clement.legoffic@foss.st.com> |
plat-stm32mp1: add support for RTC PTA
Compile the RTC PTA and the RTC driver if the RTC driver for stm32 is
enabled.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Et
plat-stm32mp1: add support for RTC PTA
Compile the RTC PTA and the RTC driver if the RTC driver for stm32 is
enabled.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 0d7276ac | 10-Apr-2024 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
plat-stm32mp1: stm32mp1_pwr: fix compatible
Remove the unexpected comma in compatible name "st,stm32mp1,pwr-reg"
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas
plat-stm32mp1: stm32mp1_pwr: fix compatible
Remove the unexpected comma in compatible name "st,stm32mp1,pwr-reg"
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 80b012ce | 26-May-2025 |
Antonio Borneo <antonio.borneo@foss.st.com> |
plat-stm32mp1: conf: default enable CFG_STM32_EXTI
Enable the driver stm32_exti on stm32mp1xx.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carr
plat-stm32mp1: conf: default enable CFG_STM32_EXTI
Enable the driver stm32_exti on stm32mp1xx.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| c501c3e1 | 18-Dec-2023 |
Lionel Debieve <lionel.debieve@foss.st.com> |
drivers: stm32_iwdg: remove OTP access in driver
Now we know if the watchdog is running by reading the hardware,
there is no need to read the OTP fuses related to the watchdog.
This allows removing
drivers: stm32_iwdg: remove OTP access in driver
Now we know if the watchdog is running by reading the hardware,
there is no need to read the OTP fuses related to the watchdog.
This allows removing platform function stm32_get_iwdg_otp_config()
and consequently stm32_iwdg.h header file.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| bace849d | 16-Dec-2024 |
Pascal Paillet <p.paillet@foss.st.com> |
plat-stm32mp1: conf: enable SCMI PERF for stm32mp13
Enable CFG_SCMI_MSG_PERF_DOMAIN for STM32MP13 that is used
to provide CPU OPP to linux.
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Rev
plat-stm32mp1: conf: enable SCMI PERF for stm32mp13
Enable CFG_SCMI_MSG_PERF_DOMAIN for STM32MP13 that is used
to provide CPU OPP to linux.
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 0cffa1df | 25-Nov-2024 |
Pascal Paillet <p.paillet@foss.st.com> |
plat-stm32mp1: SCMI performance domain for CPU DVFS
Implement scmi-msg perf protocol platform handlers to drive CPU
voltage/frequency scaling support.
Co-developed-by: Etienne Carriere <etienne.car
plat-stm32mp1: SCMI performance domain for CPU DVFS
Implement scmi-msg perf protocol platform handlers to drive CPU
voltage/frequency scaling support.
Co-developed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
show more ...
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| d8aa45cc | 09-Dec-2024 |
Pascal Paillet <p.paillet@foss.st.com> |
plat-stm32mp1: chip and STM32MP15 platform identification
New platform function to get the chip identification using
DBGMCU SoC register.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
plat-stm32mp1: chip and STM32MP15 platform identification
New platform function to get the chip identification using
DBGMCU SoC register.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 61491a0c | 21-Nov-2024 |
Pascal Paillet <p.paillet@foss.st.com> |
plat-stm32mp1: retrieve chip id from syscfg
Chip ID is read from SYSCFG. Add the associated read
function and new CHIP IDs.
Use the chip id to dynamically detect the CRYPTO hardware
support, the se
plat-stm32mp1: retrieve chip id from syscfg
Chip ID is read from SYSCFG. Add the associated read
function and new CHIP IDs.
Use the chip id to dynamically detect the CRYPTO hardware
support, the second CPU core, and CPU OPP.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 54f13dcc | 28-Nov-2024 |
Pascal Paillet <p.paillet@foss.st.com> |
plat-stm32mp1: default enable CFG_STM32_CPU_OPP for STM32MP13
Enable CFG_STM32_CPU_OPP for STM32MP13 and increase
CFG_STM32MP_OPP_COUNT to 3 OPP.
Signed-off-by: Pascal Paillet <p.paillet@foss.st.co
plat-stm32mp1: default enable CFG_STM32_CPU_OPP for STM32MP13
Enable CFG_STM32_CPU_OPP for STM32MP13 and increase
CFG_STM32MP_OPP_COUNT to 3 OPP.
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 155ebf23 | 21-Nov-2024 |
Pascal Paillet <p.paillet@foss.st.com> |
drivers: add stm32 CPU DVFS driver
drivers/cpu_opp.c implements dynamic voltage and frequency
scaling for the CPU.
It is used at boot time to set an higher operating point than
the one used to boot.
drivers: add stm32 CPU DVFS driver
drivers/cpu_opp.c implements dynamic voltage and frequency
scaling for the CPU.
It is used at boot time to set an higher operating point than
the one used to boot.
It will be used by the SCMI performance service.
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 0e385ea6 | 20-Feb-2024 |
Thomas Bourgoin <thomas.bourgoin@foss.st.com> |
plat-stm32mp1: conf: default enable HASH
Default enable HASH compilation.
Enable CFG_STM32_CRYPTO_DRIVERS if any crypto IP is compiled.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
plat-stm32mp1: conf: default enable HASH
Default enable HASH compilation.
Enable CFG_STM32_CRYPTO_DRIVERS if any crypto IP is compiled.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 7d9d593d | 05-Feb-2025 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: firewall: stm32_etzpc: remove header file
Remove stm32_etzpc.h header file that is not required since the
declared and defined resources are used internally in stm32_etzpc.c
By the way, al
drivers: firewall: stm32_etzpc: remove header file
Remove stm32_etzpc.h header file that is not required since the
declared and defined resources are used internally in stm32_etzpc.c
By the way, also remove inclusion of stm32mp15-etzpc.h DT bindings
header file from stm32_rng.c where it is not needed.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 1f2e5a0d | 22-Feb-2024 |
Thomas Bourgoin <thomas.bourgoin@foss.st.com> |
plat-stm32mp1: conf: default enable PKA
Default enable PKA compilation.
Enable the STM32_CRYPTO_DRIVERS if PKA is compiled.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by:
plat-stm32mp1: conf: default enable PKA
Default enable PKA compilation.
Enable the STM32_CRYPTO_DRIVERS if PKA is compiled.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| ded20780 | 23-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: stm32_i2c: use compatible st,stm32mp15-i2c-non-secure
Change STM32 I2C driver to rely on the compatible DT property of the
node to store whether the bus is expected assigned to secure or
no
drivers: stm32_i2c: use compatible st,stm32mp15-i2c-non-secure
Change STM32 I2C driver to rely on the compatible DT property of the
node to store whether the bus is expected assigned to secure or
non-secure world. Using a non-secure I2C bus in OP-TEE on stm32mp1
platforms is something expected only on STM32MP15 variant for
compatibility with platform already supported in upstream Linux/U-Boot
components, as defined by st,stm32mp15-i2c-non-secure specific
compatible string ID.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 29ee70d6 | 12-Dec-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp1: enable RTC framework if CFG_DRIVERS_RTC is set
If CFG_DRIVERS_RTC is enabled, force the compilation of the file
core/drivers/rtc/rtc.c in order to share the generic functions.
Signed
plat-stm32mp1: enable RTC framework if CFG_DRIVERS_RTC is set
If CFG_DRIVERS_RTC is enabled, force the compilation of the file
core/drivers/rtc/rtc.c in order to share the generic functions.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 5eb947b3 | 16-Dec-2024 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp1: conf: default enable the RTC driver
Default enable the RTC driver support on stm32mp1 platforms.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne
plat-stm32mp1: conf: default enable the RTC driver
Default enable the RTC driver support on stm32mp1 platforms.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| ccb65ffa | 18-Dec-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: remove incr_refcnt()/decr_refcnt()
Remove platform specific refcount helper functions incr_refcnt()
and decr_refcnt() and related that are no more used since commit
f63f11bd1763 ("dri
plat-stm32mp1: remove incr_refcnt()/decr_refcnt()
Remove platform specific refcount helper functions incr_refcnt()
and decr_refcnt() and related that are no more used since commit
f63f11bd1763 ("drivers: stm32_rng: keep rng enable from initialization")
merged in OP-TEE tag 3.21.0.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 7fac2ff8 | 17-Dec-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: stm32_util.h: remove unused include files
Remove inclusion of header files no more needed in
plat-stm32mp1/stm32_util.h.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com
plat-stm32mp1: stm32_util.h: remove unused include files
Remove inclusion of header files no more needed in
plat-stm32mp1/stm32_util.h.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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| 1d4d2421 | 22-Oct-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: remove deprecated shared_resource driver
Remove stm32mp1 platform shared_resources.c driver that is no more used.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked
plat-stm32mp1: remove deprecated shared_resource driver
Remove stm32mp1 platform shared_resources.c driver that is no more used.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
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