xref: /optee_os/core/arch/arm/plat-stm32mp1/stm32_util.h (revision 7fac2ff87116d50330fbbd35eca0c3d20095b6cc)
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3  * Copyright (c) 2018-2022, STMicroelectronics
4  */
5 
6 #ifndef __STM32_UTIL_H__
7 #define __STM32_UTIL_H__
8 
9 #include <assert.h>
10 #include <drivers/clk.h>
11 #include <kernel/panic.h>
12 #include <stdint.h>
13 #include <tee_api_types.h>
14 #include <types_ext.h>
15 
16 /* Backup registers and RAM utils */
17 vaddr_t stm32mp_bkpreg(unsigned int idx);
18 
19 /* Platform util for the RCC drivers */
20 vaddr_t stm32_rcc_base(void);
21 
22 /* Platform util for the GIC */
23 vaddr_t get_gicd_base(void);
24 
25 /* Platform util for PMIC support */
26 bool stm32mp_with_pmic(void);
27 
28 /* Power management service */
29 #ifdef CFG_PSCI_ARM32
30 void stm32mp_register_online_cpu(void);
31 #else
32 static inline void stm32mp_register_online_cpu(void)
33 {
34 }
35 #endif
36 
37 /*
38  * Generic spinlock function that bypass spinlock if MMU is disabled or
39  * lock is NULL.
40  */
41 uint32_t may_spin_lock(unsigned int *lock);
42 void may_spin_unlock(unsigned int *lock, uint32_t exceptions);
43 
44 /* Helper from platform RCC clock driver */
45 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id);
46 
47 extern const struct clk_ops stm32mp1_clk_ops;
48 
49 /* Return rstctrl instance related to RCC reset controller DT binding ID */
50 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id);
51 
52 /*
53  * Structure and API function for BSEC driver to get some platform data.
54  *
55  * @base: BSEC interface registers physical base address
56  * @upper_start: Base ID for the BSEC upper words in the platform
57  * @max_id: Max value for BSEC word ID for the platform
58  */
59 struct stm32_bsec_static_cfg {
60 	paddr_t base;
61 	unsigned int upper_start;
62 	unsigned int max_id;
63 };
64 
65 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg);
66 
67 /*
68  * Shared reference counter: increments by 2 on secure increment
69  * request, decrements by 2 on secure decrement request. Bit #0
70  * is set to 1 on non-secure increment request and reset to 0 on
71  * non-secure decrement request. These counters initialize to
72  * either 0, 1 or 2 upon their expect default state.
73  * Counters saturate to UINT_MAX / 2.
74  */
75 #define SHREFCNT_NONSECURE_FLAG		0x1ul
76 #define SHREFCNT_SECURE_STEP		0x2ul
77 #define SHREFCNT_MAX			(UINT_MAX / 2)
78 
79 /* Return 1 if refcnt increments from 0, else return 0 */
80 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure)
81 {
82 	int rc = !*refcnt;
83 
84 	if (secure) {
85 		if (*refcnt < SHREFCNT_MAX) {
86 			*refcnt += SHREFCNT_SECURE_STEP;
87 			assert(*refcnt < SHREFCNT_MAX);
88 		}
89 	} else {
90 		*refcnt |= SHREFCNT_NONSECURE_FLAG;
91 	}
92 
93 	return rc;
94 }
95 
96 /* Return 1 if refcnt decrements to 0, else return 0 */
97 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure)
98 {
99 	int  rc = 0;
100 
101 	if (secure) {
102 		if (*refcnt < SHREFCNT_MAX) {
103 			if (*refcnt < SHREFCNT_SECURE_STEP)
104 				panic();
105 
106 			*refcnt -= SHREFCNT_SECURE_STEP;
107 			rc = !*refcnt;
108 		}
109 	} else {
110 		rc = (*refcnt == SHREFCNT_NONSECURE_FLAG);
111 		*refcnt &= ~SHREFCNT_NONSECURE_FLAG;
112 	}
113 
114 	return rc;
115 }
116 
117 static inline int incr_refcnt(unsigned int *refcnt)
118 {
119 	return incr_shrefcnt(refcnt, true);
120 }
121 
122 static inline int decr_refcnt(unsigned int *refcnt)
123 {
124 	return decr_shrefcnt(refcnt, true);
125 }
126 
127 bool stm32mp_allow_probe_shared_device(const void *fdt, int node);
128 
129 #if defined(CFG_STM32MP15) && defined(CFG_WITH_PAGER)
130 /*
131  * Return the SRAM alias physical address related to @pa when applicable or
132  * @pa if it does not relate to an SRAMx non-aliased memory address.
133  */
134 paddr_t stm32mp1_pa_or_sram_alias_pa(paddr_t pa);
135 
136 /* Return whether or not the physical address range intersec pager secure RAM */
137 bool stm32mp1_ram_intersect_pager_ram(paddr_t base, size_t size);
138 #else
139 static inline paddr_t stm32mp1_pa_or_sram_alias_pa(paddr_t pa)
140 {
141 	return pa;
142 }
143 
144 static inline bool stm32mp1_ram_intersect_pager_ram(paddr_t base __unused,
145 						    size_t size __unused)
146 {
147 	return false;
148 }
149 #endif /*CFG_STM32MP15 && CFG_WITH_PAGER*/
150 #endif /*__STM32_UTIL_H__*/
151