1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/clock/stm32mp13-clksrc.h> 9#include <dt-bindings/firewall/stm32mp13-etzpc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 12#include <dt-bindings/reset/stm32mp13-resets.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a7"; 24 device_type = "cpu"; 25 reg = <0>; 26 clocks = <&rcc CK_MPU>; 27 clock-names = "cpu"; 28 operating-points-v2 = <&cpu0_opp_table>; 29 }; 30 }; 31 32 cpu0_opp_table: cpu0-opp-table { 33 compatible = "operating-points-v2"; 34 35 /* Non‑overdrive OPP mission profile */ 36 opp-650000000 { 37 opp-hz = /bits/ 64 <650000000>; 38 opp-microvolt = <1250000>; 39 st,opp-default; 40 }; 41 42 /* Overdrive OPP: 10‑year life activity @100% activity rate */ 43 opp-900000000 { 44 opp-hz = /bits/ 64 <900000000>; 45 opp-microvolt = <1350000>; 46 st,opp-default; 47 }; 48 49 /* Overdrive OPP: 10‑year life activity @25% activity rate */ 50 opp-1000000000 { 51 opp-hz = /bits/ 64 <1000000000>; 52 opp-microvolt = <1350000>; 53 }; 54 }; 55 56 hse_monitor: hse-monitor { 57 compatible = "st,freq-monitor"; 58 counter = <&lptimer3 1 1 0 0>; 59 status = "disabled"; 60 }; 61 62 intc: interrupt-controller@a0021000 { 63 compatible = "arm,cortex-a7-gic"; 64 #interrupt-cells = <3>; 65 interrupt-controller; 66 reg = <0xa0021000 0x1000>, 67 <0xa0022000 0x2000>; 68 }; 69 70 psci { 71 compatible = "arm,psci-1.0"; 72 method = "smc"; 73 }; 74 75 clocks { 76 clk_hse: clk-hse { 77 #clock-cells = <0>; 78 compatible = "fixed-clock"; 79 clock-frequency = <24000000>; 80 }; 81 82 clk_hsi: clk-hsi { 83 #clock-cells = <0>; 84 compatible = "fixed-clock"; 85 clock-frequency = <64000000>; 86 }; 87 88 clk_lse: clk-lse { 89 #clock-cells = <0>; 90 compatible = "fixed-clock"; 91 clock-frequency = <32768>; 92 }; 93 94 clk_lsi: clk-lsi { 95 #clock-cells = <0>; 96 compatible = "fixed-clock"; 97 clock-frequency = <32000>; 98 }; 99 100 clk_csi: clk-csi { 101 #clock-cells = <0>; 102 compatible = "fixed-clock"; 103 clock-frequency = <4000000>; 104 }; 105 106 clk_i2sin: clk-i2sin { 107 #clock-cells = <0>; 108 compatible = "fixed-clock"; 109 clock-frequency = <19000000>; 110 }; 111 112 }; 113 114 sdmmc1_io: sdmmc1_io { 115 compatible = "st,stm32mp13-iod"; 116 regulator-name = "sdmmc1_io"; 117 regulator-always-on; 118 }; 119 120 sdmmc2_io: sdmmc2_io { 121 compatible = "st,stm32mp13-iod"; 122 regulator-name = "sdmmc2_io"; 123 regulator-always-on; 124 }; 125 126 soc { 127 compatible = "simple-bus"; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 interrupt-parent = <&intc>; 131 ranges; 132 133 usart3: serial@4000f000 { 134 compatible = "st,stm32h7-uart"; 135 reg = <0x4000f000 0x400>; 136 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&rcc USART3_K>; 138 resets = <&rcc USART3_R>; 139 status = "disabled"; 140 }; 141 142 uart4: serial@40010000 { 143 compatible = "st,stm32h7-uart"; 144 reg = <0x40010000 0x400>; 145 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&rcc UART4_K>; 147 resets = <&rcc UART4_R>; 148 status = "disabled"; 149 }; 150 151 uart5: serial@40011000 { 152 compatible = "st,stm32h7-uart"; 153 reg = <0x40011000 0x400>; 154 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&rcc UART5_K>; 156 resets = <&rcc UART5_R>; 157 status = "disabled"; 158 }; 159 160 uart7: serial@40018000 { 161 compatible = "st,stm32h7-uart"; 162 reg = <0x40018000 0x400>; 163 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&rcc UART7_K>; 165 resets = <&rcc UART7_R>; 166 status = "disabled"; 167 }; 168 169 uart8: serial@40019000 { 170 compatible = "st,stm32h7-uart"; 171 reg = <0x40019000 0x400>; 172 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 173 clocks = <&rcc UART8_K>; 174 resets = <&rcc UART8_R>; 175 status = "disabled"; 176 }; 177 178 usart6: serial@44003000 { 179 compatible = "st,stm32h7-uart"; 180 reg = <0x44003000 0x400>; 181 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&rcc USART6_K>; 183 resets = <&rcc USART6_R>; 184 status = "disabled"; 185 }; 186 187 rcc: rcc@50000000 { 188 compatible = "st,stm32mp13-rcc", "syscon"; 189 reg = <0x50000000 0x1000>; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 #clock-cells = <1>; 193 #reset-cells = <1>; 194 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>; 195 clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin"; 196 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 197 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 198 secure-interrupt-names = "wakeup"; 199 }; 200 201 pwr_regulators: pwr@50001000 { 202 compatible = "st,stm32mp1,pwr-reg"; 203 reg = <0x50001000 0x10>; 204 205 reg11: reg11 { 206 regulator-name = "reg11"; 207 regulator-min-microvolt = <1100000>; 208 regulator-max-microvolt = <1100000>; 209 }; 210 211 reg18: reg18 { 212 regulator-name = "reg18"; 213 regulator-min-microvolt = <1800000>; 214 regulator-max-microvolt = <1800000>; 215 }; 216 217 usb33: usb33 { 218 regulator-name = "usb33"; 219 regulator-min-microvolt = <3300000>; 220 regulator-max-microvolt = <3300000>; 221 }; 222 }; 223 224 pwr_irq: pwr@50001010 { 225 compatible = "st,stm32mp1,pwr-irq"; 226 status = "disabled"; 227 }; 228 229 syscfg: syscon@50020000 { 230 compatible = "st,stm32mp157-syscfg", "syscon"; 231 reg = <0x50020000 0x400>; 232 }; 233 234 iwdg2: watchdog@5a002000 { 235 compatible = "st,stm32mp1-iwdg"; 236 reg = <0x5a002000 0x400>; 237 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 239 clock-names = "pclk", "lsi"; 240 status = "disabled"; 241 }; 242 243 rtc: rtc@5c004000 { 244 compatible = "st,stm32mp13-rtc"; 245 reg = <0x5c004000 0x400>; 246 clocks = <&rcc RTCAPB>, <&rcc RTC>; 247 clock-names = "pclk", "rtc_ck"; 248 status = "disabled"; 249 }; 250 251 bsec: efuse@5c005000 { 252 compatible = "st,stm32mp13-bsec"; 253 reg = <0x5c005000 0x400>; 254 #address-cells = <1>; 255 #size-cells = <1>; 256 257 cfg0_otp: cfg0_otp@0 { 258 reg = <0x0 0x2>; 259 }; 260 part_number_otp: part_number_otp@4 { 261 reg = <0x4 0x2>; 262 bits = <0 12>; 263 }; 264 monotonic_otp: monotonic_otp@10 { 265 reg = <0x10 0x4>; 266 }; 267 nand_otp: cfg9_otp@24 { 268 reg = <0x24 0x4>; 269 }; 270 uid_otp: uid_otp@34 { 271 reg = <0x34 0xc>; 272 }; 273 hw2_otp: hw2_otp@48 { 274 reg = <0x48 0x4>; 275 }; 276 ts_cal1: calib@5c { 277 reg = <0x5c 0x2>; 278 }; 279 ts_cal2: calib@5e { 280 reg = <0x5e 0x2>; 281 }; 282 pkh_otp: pkh_otp@60 { 283 reg = <0x60 0x20>; 284 }; 285 ethernet_mac1_address: mac1@e4 { 286 reg = <0xe4 0xc>; 287 st,non-secure-otp; 288 }; 289 oem_enc_key: oem_enc_key@170 { 290 reg = <0x170 0x10>; 291 }; 292 }; 293 294 tzc400: tzc@5c006000 { 295 compatible = "st,stm32mp1-tzc"; 296 reg = <0x5c006000 0x1000>; 297 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 298 st,mem-map = <0xc0000000 0x40000000>; 299 clocks = <&rcc TZC>; 300 }; 301 302 tamp: tamp@5c00a000 { 303 compatible = "st,stm32mp13-tamp"; 304 reg = <0x5c00a000 0x400>; 305 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&rcc RTCAPB>; 307 st,backup-zones = <10 5 17>; 308 }; 309 310 pinctrl: pin-controller@50002000 { 311 #address-cells = <1>; 312 #size-cells = <1>; 313 compatible = "st,stm32mp135-pinctrl"; 314 ranges = <0 0x50002000 0x8400>; 315 pins-are-numbered; 316 317 gpioa: gpio@50002000 { 318 gpio-controller; 319 #gpio-cells = <2>; 320 interrupt-controller; 321 #interrupt-cells = <2>; 322 #access-controller-cells = <1>; 323 clocks = <&rcc GPIOA>; 324 reg = <0x0 0x400>; 325 st,bank-name = "GPIOA"; 326 ngpios = <16>; 327 gpio-ranges = <&pinctrl 0 0 16>; 328 }; 329 330 gpiob: gpio@50003000 { 331 gpio-controller; 332 #gpio-cells = <2>; 333 interrupt-controller; 334 #interrupt-cells = <2>; 335 #access-controller-cells = <1>; 336 clocks = <&rcc GPIOB>; 337 reg = <0x1000 0x400>; 338 st,bank-name = "GPIOB"; 339 ngpios = <16>; 340 gpio-ranges = <&pinctrl 0 16 16>; 341 }; 342 343 gpioc: gpio@50004000 { 344 gpio-controller; 345 #gpio-cells = <2>; 346 interrupt-controller; 347 #interrupt-cells = <2>; 348 #access-controller-cells = <1>; 349 clocks = <&rcc GPIOC>; 350 reg = <0x2000 0x400>; 351 st,bank-name = "GPIOC"; 352 ngpios = <16>; 353 gpio-ranges = <&pinctrl 0 32 16>; 354 }; 355 356 gpiod: gpio@50005000 { 357 gpio-controller; 358 #gpio-cells = <2>; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 #access-controller-cells = <1>; 362 clocks = <&rcc GPIOD>; 363 reg = <0x3000 0x400>; 364 st,bank-name = "GPIOD"; 365 ngpios = <16>; 366 gpio-ranges = <&pinctrl 0 48 16>; 367 }; 368 369 gpioe: gpio@50006000 { 370 gpio-controller; 371 #gpio-cells = <2>; 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 #access-controller-cells = <1>; 375 clocks = <&rcc GPIOE>; 376 reg = <0x4000 0x400>; 377 st,bank-name = "GPIOE"; 378 ngpios = <16>; 379 gpio-ranges = <&pinctrl 0 64 16>; 380 }; 381 382 gpiof: gpio@50007000 { 383 gpio-controller; 384 #gpio-cells = <2>; 385 interrupt-controller; 386 #interrupt-cells = <2>; 387 #access-controller-cells = <1>; 388 clocks = <&rcc GPIOF>; 389 reg = <0x5000 0x400>; 390 st,bank-name = "GPIOF"; 391 ngpios = <16>; 392 gpio-ranges = <&pinctrl 0 80 16>; 393 }; 394 395 gpiog: gpio@50008000 { 396 gpio-controller; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 #access-controller-cells = <1>; 401 clocks = <&rcc GPIOG>; 402 reg = <0x6000 0x400>; 403 st,bank-name = "GPIOG"; 404 ngpios = <16>; 405 gpio-ranges = <&pinctrl 0 96 16>; 406 }; 407 408 gpioh: gpio@50009000 { 409 gpio-controller; 410 #gpio-cells = <2>; 411 interrupt-controller; 412 #interrupt-cells = <2>; 413 #access-controller-cells = <1>; 414 clocks = <&rcc GPIOH>; 415 reg = <0x7000 0x400>; 416 st,bank-name = "GPIOH"; 417 ngpios = <15>; 418 gpio-ranges = <&pinctrl 0 112 15>; 419 }; 420 421 gpioi: gpio@5000a000 { 422 gpio-controller; 423 #gpio-cells = <2>; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 #access-controller-cells = <1>; 427 clocks = <&rcc GPIOI>; 428 reg = <0x8000 0x400>; 429 st,bank-name = "GPIOI"; 430 ngpios = <8>; 431 gpio-ranges = <&pinctrl 0 128 8>; 432 }; 433 }; 434 435 etzpc: etzpc@5c007000 { 436 compatible = "st,stm32-etzpc", "simple-bus"; 437 reg = <0x5C007000 0x400>; 438 clocks = <&rcc TZPC>; 439 #address-cells = <1>; 440 #size-cells = <1>; 441 #access-controller-cells = <1>; 442 443 adc_2: adc@48004000 { 444 reg = <0x48004000 0x400>; 445 compatible = "st,stm32mp13-adc-core"; 446 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 448 clock-names = "bus", "adc"; 449 interrupt-controller; 450 #interrupt-cells = <1>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 access-controllers = <&etzpc STM32MP1_ETZPC_ADC2_ID>; 454 status = "disabled"; 455 456 adc2: adc@0 { 457 compatible = "st,stm32mp13-adc"; 458 reg = <0x0>; 459 #io-channel-cells = <1>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 interrupt-parent = <&adc_2>; 463 interrupts = <0>; 464 status = "disabled"; 465 466 channel@13 { 467 reg = <13>; 468 label = "vrefint"; 469 }; 470 471 channel@14 { 472 reg = <14>; 473 label = "vddcore"; 474 }; 475 476 channel@16 { 477 reg = <16>; 478 label = "vddcpu"; 479 }; 480 481 channel@17 { 482 reg = <17>; 483 label = "vddq_ddr"; 484 }; 485 }; 486 }; 487 488 usart1: serial@4c000000 { 489 compatible = "st,stm32h7-uart"; 490 reg = <0x4c000000 0x400>; 491 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&rcc USART1_K>; 493 resets = <&rcc USART1_R>; 494 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 495 status = "disabled"; 496 }; 497 498 usart2: serial@4c001000 { 499 compatible = "st,stm32h7-uart"; 500 reg = <0x4c001000 0x400>; 501 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&rcc USART2_K>; 503 resets = <&rcc USART2_R>; 504 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 505 status = "disabled"; 506 }; 507 508 i2c3: i2c@4c004000 { 509 compatible = "st,stm32mp13-i2c"; 510 reg = <0x4c004000 0x400>; 511 clocks = <&rcc I2C3_K>; 512 resets = <&rcc I2C3_R>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 st,syscfg-fmp = <&syscfg 0x4 0x4>; 516 i2c-analog-filter; 517 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 518 status = "disabled"; 519 }; 520 521 i2c4: i2c@4c005000 { 522 compatible = "st,stm32mp13-i2c"; 523 reg = <0x4c005000 0x400>; 524 clocks = <&rcc I2C4_K>; 525 resets = <&rcc I2C4_R>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 st,syscfg-fmp = <&syscfg 0x4 0x8>; 529 i2c-analog-filter; 530 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 531 status = "disabled"; 532 }; 533 534 i2c5: i2c@4c006000 { 535 compatible = "st,stm32mp13-i2c"; 536 reg = <0x4c006000 0x400>; 537 clocks = <&rcc I2C5_K>; 538 resets = <&rcc I2C5_R>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 st,syscfg-fmp = <&syscfg 0x4 0x10>; 542 i2c-analog-filter; 543 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 544 status = "disabled"; 545 }; 546 547 timers12: timer@4c007000 { 548 #address-cells = <1>; 549 #size-cells = <0>; 550 compatible = "st,stm32-timers"; 551 reg = <0x4c007000 0x400>; 552 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&rcc TIM12_K>; 554 clock-names = "int"; 555 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 556 status = "disabled"; 557 558 counter { 559 compatible = "st,stm32-timer-counter"; 560 status = "disabled"; 561 }; 562 }; 563 564 timers13: timer@4c008000 { 565 #address-cells = <1>; 566 #size-cells = <0>; 567 compatible = "st,stm32-timers"; 568 reg = <0x4c008000 0x400>; 569 clocks = <&rcc TIM13_K>; 570 clock-names = "int"; 571 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 572 status = "disabled"; 573 }; 574 575 timers14: timer@4c009000 { 576 #address-cells = <1>; 577 #size-cells = <0>; 578 compatible = "st,stm32-timers"; 579 reg = <0x4c009000 0x400>; 580 clocks = <&rcc TIM14_K>; 581 clock-names = "int"; 582 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 583 status = "disabled"; 584 }; 585 586 timers15: timer@4c00a000 { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 compatible = "st,stm32-timers"; 590 reg = <0x4c00a000 0x400>; 591 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&rcc TIM15_K>; 593 clock-names = "int"; 594 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 595 status = "disabled"; 596 597 counter { 598 compatible = "st,stm32-timer-counter"; 599 status = "disabled"; 600 }; 601 }; 602 603 timers16: timer@4c00b000 { 604 #address-cells = <1>; 605 #size-cells = <0>; 606 compatible = "st,stm32-timers"; 607 reg = <0x4c00b000 0x400>; 608 clocks = <&rcc TIM16_K>; 609 clock-names = "int"; 610 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 611 status = "disabled"; 612 }; 613 614 timers17: timer@4c00c000 { 615 #address-cells = <1>; 616 #size-cells = <0>; 617 compatible = "st,stm32-timers"; 618 reg = <0x4c00c000 0x400>; 619 clocks = <&rcc TIM17_K>; 620 clock-names = "int"; 621 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 622 status = "disabled"; 623 }; 624 625 lptimer2: timer@50021000 { 626 #address-cells = <1>; 627 #size-cells = <0>; 628 compatible = "st,stm32-lptimer"; 629 reg = <0x50021000 0x400>; 630 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&rcc LPTIM2_K>; 632 clock-names = "mux"; 633 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 634 status = "disabled"; 635 }; 636 637 lptimer3: timer@50022000 { 638 #address-cells = <1>; 639 #size-cells = <0>; 640 compatible = "st,stm32-lptimer"; 641 reg = <0x50022000 0x400>; 642 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&rcc LPTIM3_K>; 644 clock-names = "mux"; 645 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 646 status = "disabled"; 647 648 counter { 649 compatible = "st,stm32-lptimer-counter"; 650 status = "disabled"; 651 }; 652 }; 653 654 vrefbuf: vrefbuf@50025000 { 655 compatible = "st,stm32mp13-vrefbuf"; 656 reg = <0x50025000 0x8>; 657 regulator-name = "vrefbuf"; 658 regulator-min-microvolt = <1650000>; 659 regulator-max-microvolt = <2500000>; 660 clocks = <&rcc VREF>; 661 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 662 status = "disabled"; 663 }; 664 665 hash: hash@54003000 { 666 compatible = "st,stm32mp13-hash"; 667 reg = <0x54003000 0x400>; 668 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&rcc HASH1>; 670 resets = <&rcc HASH1_R>; 671 access-controllers = <&etzpc STM32MP1_ETZPC_HASH_ID>; 672 status = "disabled"; 673 }; 674 675 rng: rng@54004000 { 676 compatible = "st,stm32mp13-rng"; 677 reg = <0x54004000 0x400>; 678 clocks = <&rcc RNG1_K>; 679 resets = <&rcc RNG1_R>; 680 access-controllers = <&etzpc STM32MP1_ETZPC_RNG_ID>; 681 status = "disabled"; 682 }; 683 684 iwdg1: watchdog@5c003000 { 685 compatible = "st,stm32mp1-iwdg"; 686 reg = <0x5C003000 0x400>; 687 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 689 clock-names = "pclk", "lsi"; 690 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 691 status = "disabled"; 692 }; 693 694 stgen: stgen@5c008000 { 695 compatible = "st,stm32-stgen"; 696 reg = <0x5C008000 0x1000>; 697 access-controllers = <&etzpc STM32MP1_ETZPC_STGENC_ID>; 698 }; 699 }; 700 }; 701}; 702