Home
last modified time | relevance | path

Searched refs:ubSYNSet (Results 1 – 6 of 6) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/
H A DhalHDMITx.c3048 MS_U32 ubSYNSet = 0; in MHal_HDMITx_EnableSSC()
3061 ubSYNSet = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02); in MHal_HDMITx_EnableSSC()
3062 ubSYNSet |= ( (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0xFF) << 16); in MHal_HDMITx_EnableSSC()
3064 if(ubSYNSet != 0) in MHal_HDMITx_EnableSSC()
3065 dSYNCLK = ((ub432MHz*ub2x19times)/ubSYNSet); in MHal_HDMITx_EnableSSC()
3071 …dSSC_Step = (((ubSYNSet/ dSSC_Span)/HDMITX_SSC_DEVIATION_DIVIDER) * dSSc_Deviation) ; //Step = SYN… in MHal_HDMITx_EnableSSC()
3073 …printf("ubSYNSet=%x, dSYNCLK=%d, dSSC_Span=%d, dSSC_Step=%d\r\n", ubSYNSet, dSYNCLK, dSSC_Span, dS… in MHal_HDMITx_EnableSSC()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/
H A DhalHDMITx.c3010 MS_U32 ubSYNSet = 0; in MHal_HDMITx_EnableSSC()
3023 ubSYNSet = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02); in MHal_HDMITx_EnableSSC()
3024 ubSYNSet |= ( (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0xFF) << 16); in MHal_HDMITx_EnableSSC()
3026 if(ubSYNSet != 0) in MHal_HDMITx_EnableSSC()
3027 dSYNCLK = ((ub432MHz*ub2x19times)/ubSYNSet); in MHal_HDMITx_EnableSSC()
3033 …dSSC_Step = (((ubSYNSet/ dSSC_Span)/HDMITX_SSC_DEVIATION_DIVIDER) * dSSc_Deviation) ; //Step = SYN… in MHal_HDMITx_EnableSSC()
3035 …printf("ubSYNSet=%x, dSYNCLK=%d, dSSC_Span=%d, dSSC_Step=%d\r\n", ubSYNSet, dSYNCLK, dSSC_Span, dS… in MHal_HDMITx_EnableSSC()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/
H A DhalHDMITx.c3449 MS_U32 ubSYNSet = 0; in MHal_HDMITx_EnableSSC()
3462 ubSYNSet = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02); in MHal_HDMITx_EnableSSC()
3463 ubSYNSet |= ( (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0xFF) << 16); in MHal_HDMITx_EnableSSC()
3465 if(ubSYNSet != 0) in MHal_HDMITx_EnableSSC()
3466 dSYNCLK = ((ub432MHz*ub2x19times)/ubSYNSet); in MHal_HDMITx_EnableSSC()
3472 …dSSC_Step = (((ubSYNSet/ dSSC_Span)/HDMITX_SSC_DEVIATION_DIVIDER) * dSSc_Deviation) ; //Step = SYN… in MHal_HDMITx_EnableSSC()
3474 …printf("ubSYNSet=%x, dSYNCLK=%d, dSSC_Span=%d, dSSC_Step=%d\r\n", ubSYNSet, dSYNCLK, dSSC_Span, dS… in MHal_HDMITx_EnableSSC()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/
H A DhalHDMITx.c2960 MS_U32 ubSYNSet = 0; in MHal_HDMITx_EnableSSC() local
2974 ubSYNSet = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02); in MHal_HDMITx_EnableSSC()
2975 ubSYNSet |= ( (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0xFF) << 16); in MHal_HDMITx_EnableSSC()
2977 dSYNCLK = (double) ((ub432MHz*ub2x19times)/ubSYNSet); in MHal_HDMITx_EnableSSC()
2980 dSSC_Step = ubSYNSet * dSSc_Deviation / dSSC_Span; //Step = SYN_SET * deviation / Span in MHal_HDMITx_EnableSSC()
2982 …printf("ubSYNSet=%x, dSYNCLK=%f, dSSC_Span=%f, dSSC_Step=%f\r\n", ubSYNSet, dSYNCLK, dSSC_Span, dS… in MHal_HDMITx_EnableSSC()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/
H A DhalHDMITx.c2945 MS_U32 ubSYNSet = 0; in MHal_HDMITx_EnableSSC()
2959 ubSYNSet = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02); in MHal_HDMITx_EnableSSC()
2960 ubSYNSet |= ( (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0xFF) << 16); in MHal_HDMITx_EnableSSC()
2962 dSYNCLK = (double) ((ub432MHz*ub2x19times)/ubSYNSet); in MHal_HDMITx_EnableSSC()
2965 dSSC_Step = ubSYNSet * dSSc_Deviation / dSSC_Span; //Step = SYN_SET * deviation / Span in MHal_HDMITx_EnableSSC()
2967 …printf("ubSYNSet=%x, dSYNCLK=%f, dSSC_Span=%f, dSSC_Step=%f\r\n", ubSYNSet, dSYNCLK, dSSC_Span, dS… in MHal_HDMITx_EnableSSC()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/
H A DhalHDMITx.c3333 MS_U32 ubSYNSet = 0; in MHal_HDMITx_EnableSSC()
3347 ubSYNSet = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02); in MHal_HDMITx_EnableSSC()
3348 ubSYNSet |= ( (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0xFF) << 16); in MHal_HDMITx_EnableSSC()
3350 dSYNCLK = (double) ((ub432MHz*ub2x19times)/ubSYNSet); in MHal_HDMITx_EnableSSC()
3353 dSSC_Step = ubSYNSet * dSSc_Deviation / dSSC_Span; //Step = SYN_SET * deviation / Span in MHal_HDMITx_EnableSSC()
3355 …printf("ubSYNSet=%x, dSYNCLK=%f, dSSC_Span=%f, dSSC_Step=%f\r\n", ubSYNSet, dSYNCLK, dSSC_Span, dS… in MHal_HDMITx_EnableSSC()