Searched refs:_gHPDGpioPin (Results 1 – 6 of 6) sorted by relevance
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/ |
| H A D | halHDMITx.c | 527 MS_U8 _gHPDGpioPin = 0; variable
630 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Disable()
632 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Disable()
655 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Enable()
657 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Enable()
660 …MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_P… in MHal_HDMITx_Int_Enable()
680 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Clear()
682 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Clear()
706 if(_gHPDGpioPin != 0xC4) // HPD = I2S_GPIO4 in MHal_HDMITx_Int_Status()
708 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Status()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/ |
| H A D | halHDMITx.c | 555 MS_U8 _gHPDGpioPin = 0; variable
653 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Disable()
655 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Disable()
678 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Enable()
680 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Enable()
683 …MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_P… in MHal_HDMITx_Int_Enable()
703 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Clear()
705 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Clear()
729 if(_gHPDGpioPin != 0xC4) // HPD = I2S_GPIO4 in MHal_HDMITx_Int_Status()
731 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Status()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/ |
| H A D | halHDMITx.c | 576 MS_U8 _gHPDGpioPin = 0; variable
679 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Disable()
681 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Disable()
704 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Enable()
706 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Enable()
709 …MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_P… in MHal_HDMITx_Int_Enable()
729 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Clear()
731 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Clear()
755 if(_gHPDGpioPin != 0xC4) // HPD = I2S_GPIO4 in MHal_HDMITx_Int_Status()
757 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Status()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/ |
| H A D | halHDMITx.c | 564 MS_U8 _gHPDGpioPin = 0; variable
667 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Disable()
669 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Disable()
692 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Enable()
694 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Enable()
697 …MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_P… in MHal_HDMITx_Int_Enable()
717 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Clear()
719 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Clear()
743 if(_gHPDGpioPin != 0xC4) // HPD = I2S_GPIO4 in MHal_HDMITx_Int_Status()
745 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Status()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/ |
| H A D | halHDMITx.c | 703 MS_U8 _gHPDGpioPin = 0; variable
801 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Disable()
803 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Disable()
826 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Enable()
828 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Enable()
831 …MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_P… in MHal_HDMITx_Int_Enable()
851 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Clear()
853 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Clear()
877 if(_gHPDGpioPin != 0xC4) // HPD = I2S_GPIO4 in MHal_HDMITx_Int_Status()
879 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Status()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/ |
| H A D | halHDMITx.c | 753 MS_U8 _gHPDGpioPin = 0; variable
856 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Disable()
858 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Disable()
881 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Enable()
883 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Enable()
886 …MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_P… in MHal_HDMITx_Int_Enable()
906 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4 in MHal_HDMITx_Int_Clear()
908 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Clear()
932 if(_gHPDGpioPin != 0xC4) // HPD = I2S_GPIO4 in MHal_HDMITx_Int_Status()
934 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin); in MHal_HDMITx_Int_Status()
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