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Searched refs:TOP_CKG_VP8_240MHZ (Results 1 – 25 of 40) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/hvd_ex/
H A DhalHVD_EX.c2581 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2591 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2601 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2611 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2651 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h455 #define TOP_CKG_VP8_240MHZ BITS(11:10, 3) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/hvd_ex/
H A DhalHVD_EX.c2581 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2591 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2601 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2611 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2651 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h455 #define TOP_CKG_VP8_240MHZ BITS(11:10, 3) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/hvd_ex/
H A DhalHVD_EX.c2581 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2591 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2601 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2611 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2651 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h455 #define TOP_CKG_VP8_240MHZ BITS(11:10, 3) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/hvd_ex/
H A DhalHVD_EX.c2581 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2591 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2601 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2611 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2651 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h455 #define TOP_CKG_VP8_240MHZ BITS(11:10, 3) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/hvd_ex/
H A DhalHVD_EX.c2581 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2591 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2601 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2611 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2651 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h455 #define TOP_CKG_VP8_240MHZ BITS(11:10, 3) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/hvd_ex/
H A DhalHVD_EX.c2581 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2591 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2601 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2611 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2651 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h455 #define TOP_CKG_VP8_240MHZ BITS(11:10, 3) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/hvd_ex/
H A DhalHVD_EX.c2581 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2591 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2601 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2611 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2651 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h455 #define TOP_CKG_VP8_240MHZ BITS(11:10, 3) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/hvd_ex/
H A DhalHVD_EX.c2581 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2591 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2601 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2611 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2651 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h455 #define TOP_CKG_VP8_240MHZ BITS(11:10, 3) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h503 #define TOP_CKG_VP8_240MHZ BITS(11:10, 1) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h504 #define TOP_CKG_VP8_240MHZ BITS(11:10, 1) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DregHVD_EX.h520 #define TOP_CKG_VP8_240MHZ BITS(11:10, 1) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h504 #define TOP_CKG_VP8_240MHZ BITS(11:10, 1) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h505 #define TOP_CKG_VP8_240MHZ BITS(11:10, 1) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h503 #define TOP_CKG_VP8_240MHZ BITS(11:10, 1) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DregHVD_EX.h520 #define TOP_CKG_VP8_240MHZ BITS(11:10, 1) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DregHVD_EX.h504 #define TOP_CKG_VP8_240MHZ BITS(11:10, 1) macro
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h631 #define TOP_CKG_VP8_240MHZ BITS(3:2, 1) macro

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