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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regHVD.h 98 /// @brief HVD Module Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_HVD_H_ 103 #define _REG_HVD_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 115 //***************************************************************************** 116 // RIU macro 117 #define HVD_MACRO_START do { 118 #define HVD_MACRO_END } while (0) 119 #define HVD_RIU_BASE (u32HVDRegOSBase) 120 121 #define HVD_HIGHBYTE(u16) ((MS_U8)((u16) >> 8)) 122 #define HVD_LOWBYTE(u16) ((MS_U8)(u16)) 123 #define HVD_RIU_READ_BYTE(addr) ( READ_BYTE( HVD_RIU_BASE + (addr) ) ) 124 #define HVD_RIU_READ_WORD(addr) ( READ_WORD( HVD_RIU_BASE + (addr) ) ) 125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } 126 #define HVD_RIU_WRITE_WORD(addr, val) { WRITE_WORD( HVD_RIU_BASE+(addr), val); } 127 128 129 #define _HVD_ReadByte( u32Reg ) HVD_RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1)) 130 131 #define _HVD_Read2Byte( u32Reg ) (HVD_RIU_READ_WORD((u32Reg)<<1)) 132 133 #define _HVD_Read4Byte( u32Reg ) ( (MS_U32)HVD_RIU_READ_WORD((u32Reg)<<1) | ((MS_U32)HVD_RIU_READ_WORD(((u32Reg)+2)<<1)<<16 ) ) 134 135 #define _HVD_ReadRegBit( u32Reg, u8Mask ) (HVD_RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask)) 136 137 #define _HVD_ReadWordBit( u32Reg, u16Mask ) (_HVD_Read2Byte( u32Reg ) & (u16Mask)) 138 139 #define _HVD_WriteRegBit( u32Reg, bEnable, u8Mask ) \ 140 HVD_MACRO_START \ 141 HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \ 142 (HVD_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \ 143 HVD_MACRO_END 144 145 #define _HVD_WriteByte( u32Reg, u8Val ) \ 146 HVD_MACRO_START \ 147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \ 148 HVD_MACRO_END 149 150 #define _HVD_Write2Byte( u32Reg, u16Val ) \ 151 HVD_MACRO_START \ 152 if ( ((u32Reg) & 0x01) ) \ 153 { \ 154 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \ 155 HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \ 156 } \ 157 else \ 158 { \ 159 HVD_RIU_WRITE_WORD( ((u32Reg)<<1) , u16Val); \ 160 } \ 161 HVD_MACRO_END 162 163 #define _HVD_Write3Byte( u32Reg, u32Val ) \ 164 if ((u32Reg) & 0x01) \ 165 { \ 166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \ 167 HVD_RIU_WRITE_WORD( (u32Reg + 1)<<1 , ((u32Val) >> 8)); \ 168 } \ 169 else \ 170 { \ 171 HVD_RIU_WRITE_WORD( (u32Reg) << 1, u32Val); \ 172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \ 173 } 174 175 #define _HVD_Write4Byte( u32Reg, u32Val ) \ 176 HVD_MACRO_START \ 177 if ((u32Reg) & 0x01) \ 178 { \ 179 HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \ 180 HVD_RIU_WRITE_WORD( ((u32Reg) + 1)<<1 , ( (u32Val) >> 8)); \ 181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \ 182 } \ 183 else \ 184 { \ 185 HVD_RIU_WRITE_WORD( (u32Reg) <<1 , u32Val); \ 186 HVD_RIU_WRITE_WORD( ((u32Reg) + 2)<<1 , ((u32Val) >> 16)); \ 187 } \ 188 HVD_MACRO_END 189 190 #define _HVD_WriteByteMask( u32Reg, u8Val, u8Msk ) \ 191 HVD_MACRO_START \ 192 HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ 193 HVD_MACRO_END 194 195 #define _HVD_WriteWordMask( u32Reg, u16Val , u16Msk) \ 196 HVD_MACRO_START \ 197 if ( ((u32Reg) & 0x01) ) \ 198 { \ 199 _HVD_WriteByteMask( ((u32Reg)+1) , (((u16Val) & 0xff00)>>8) , (((u16Msk)&0xff00)>>8) ); \ 200 _HVD_WriteByteMask( (u32Reg) , ((u16Val) & 0x00ff) , ((u16Msk)&0x00ff) ); \ 201 } \ 202 else \ 203 { \ 204 HVD_RIU_WRITE_WORD( ((u32Reg)<<1) , (((u16Val) & (u16Msk)) | (_HVD_Read2Byte( u32Reg ) & (~( u16Msk )))) ); \ 205 } \ 206 HVD_MACRO_END 207 208 //------------------------------------------------------------------------------ 209 // MVD Reg 210 //------------------------------------------------------------------------------ 211 #define REG_MVD_BASE (0x1100) 212 213 #define MVD_REG_STAT_CTRL (REG_MVD_BASE) 214 #define MVD_REG_CTRL_RST BIT(0) 215 #define MVD_REG_CTRL_INIT BIT(2) 216 #define MVD_REG_DISCONNECT_MIU BIT(6) 217 218 //------------------------------------------------------------------------------ 219 // HVD Reg 220 //------------------------------------------------------------------------------ 221 #define REG_HVD_BASE (0x1B00) 222 #define REG_EVD_BASE (0x60B00) 223 224 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1)) 225 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1)) 226 #define HVD_REG_RESET_SWRST BIT(0) 227 #define HVD_REG_RESET_SWRST_FIN BIT(2) 228 #define HVD_REG_RESET_STOP_BBU BIT(3) 229 #define HVD_REG_RESET_MIU_RDY BIT(4) 230 #define HVD_REG_RESET_HK_AVS_MODE BIT(8) 231 #define HVD_REG_RESET_HK_RM_MODE BIT(9) 232 #define HVD_REG_RESET_HK_RV9_DEC_MODE BIT(10) 233 #define HVD_REG_RESET_MIU_128 BIT(11) 234 #define HVD_REG_RESET_CPUIF_SEL BIT(12) 235 #define HVD_REG_RESET_ALL_SRAM_SD_EN BIT(13) 236 #define HVD_REG_RESET_BOND_HD BIT(15) 237 238 #define HVD_REG_ESB_ST_ADDR_L(reg_base) (reg_base + ((0x0002) << 1)) 239 #define HVD_REG_ESB_ST_ADDR_H(reg_base) (reg_base + ((0x0003) << 1)) 240 241 #define HVD_REG_ESB_LENGTH_L(reg_base) (reg_base + ((0x0004) << 1)) 242 #define HVD_REG_ESB_LENGTH_H(reg_base) (reg_base + ((0x0005) << 1)) 243 244 #define HVD_REG_ESB_RPTR(reg_base) (reg_base + ((0x0006) << 1)) 245 #define HVD_REG_ESB_RPTR_POLL BIT(0) 246 247 #define HVD_REG_ESB_RPTR_H(reg_base) (reg_base + ((0x0007) << 1)) 248 249 #define HVD_REG_MIF_BBU(reg_base) (reg_base + ((0x0008) << 1)) 250 #define HVD_REG_MIF_OFFSET_L_BITS 7 251 #define HVD_REG_MIF_OFFSET_H BIT(12) 252 #define HVD_REG_BBU_TSP_INPUT BIT(8) 253 #define HVD_REG_BBU_PASER_MASK (BIT(10) | BIT(9)) 254 #define HVD_REG_BBU_PASER_DISABLE 0 255 #define HVD_REG_BBU_PASER_ENABLE_ALL BIT(9) 256 #define HVD_REG_BBU_PASER_ENABLE_03 (BIT(9) | BIT(10)) 257 #define HVD_REG_BBU_AUTO_NAL_TAB BIT(11) 258 259 #define HVD_REG_NAL_TBL_ST_ADDR_L(reg_base) (reg_base + ((0x0009) << 1)) 260 #define HVD_REG_NAL_TBL_ST_ADDR_H(reg_base) (reg_base + ((0x000A) << 1)) 261 262 #define HVD_REG_HI_MBOX0_L(reg_base) (reg_base + ((0x000B) << 1)) 263 #define HVD_REG_HI_MBOX0_H(reg_base) (reg_base + ((0x000C) << 1)) 264 #define HVD_REG_HI_MBOX1_L(reg_base) (reg_base + ((0x000D) << 1)) 265 #define HVD_REG_HI_MBOX1_H(reg_base) (reg_base + ((0x000E) << 1)) 266 #define HVD_REG_HI_MBOX_SET(reg_base) (reg_base + ((0x000F) << 1)) 267 #define HVD_REG_HI_MBOX0_SET BIT(0) 268 #define HVD_REG_HI_MBOX1_SET BIT(8) 269 270 #define HVD_REG_RISC_MBOX_CLR(reg_base) (reg_base + ((0x0010) << 1)) 271 #define HVD_REG_RISC_MBOX0_CLR BIT(0) 272 #define HVD_REG_RISC_MBOX1_CLR BIT(1) 273 #define HVD_REG_RISC_ISR_CLR BIT(2) 274 #define HVD_REG_NAL_WPTR_SYNC BIT(3) 275 #define HVD_REG_RISC_ISR_MSK BIT(6) 276 #define HVD_REG_RISC_ISR_FORCE BIT(10) 277 278 #define HVD_REG_RISC_MBOX_RDY(reg_base) (reg_base + ((0x0011) << 1)) 279 #define HVD_REG_RISC_MBOX0_RDY BIT(0) 280 #define HVD_REG_RISC_MBOX1_RDY BIT(4) 281 #define HVD_REG_RISC_ISR_VALID BIT(8) 282 283 #define HVD_REG_HI_MBOX_RDY(reg_base) (reg_base + ((0x0012) << 1)) 284 #define HVD_REG_HI_MBOX0_RDY BIT(0) 285 #define HVD_REG_HI_MBOX1_RDY BIT(8) 286 287 #define HVD_REG_RISC_MBOX0_L(reg_base) (reg_base + ((0x0013) << 1)) 288 #define HVD_REG_RISC_MBOX0_H(reg_base) (reg_base + ((0x0014) << 1)) 289 #define HVD_REG_RISC_MBOX1_L(reg_base) (reg_base + ((0x0015) << 1)) 290 #define HVD_REG_RISC_MBOX1_H(reg_base) (reg_base + ((0x0016) << 1)) 291 292 #define HVD_REG_POLL_NAL_RPTR(reg_base) (reg_base + ((0x0017) << 1)) 293 #define HVD_REG_POLL_NAL_RPTR_BIT BIT(0) 294 #define HVD_REG_NAL_RPTR_HI(reg_base) (reg_base + ((0x0018) << 1)) 295 #define HVD_REG_NAL_WPTR_HI(reg_base) (reg_base + ((0x0019) << 1)) 296 #define HVD_REG_NAL_TAB_LEN(reg_base) (reg_base + ((0x0020) << 1)) 297 298 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1)) 299 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1)) 300 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1)) 301 302 /* Second bitstream registers definition */ 303 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1)) 304 #define HVD_REG_MODE_HK_AVS_MODE_BS2 BIT(8) 305 #define HVD_REG_MODE_HK_RM_MODE_BS2 BIT(9) 306 #define HVD_REG_MODE_HK_RV9_DEC_MODE_BS2 BIT(10) 307 308 #define HVD_REG_ESB_ST_ADDR_L_BS2 (REG_HVD_BASE + ((0x0032) << 1)) 309 #define HVD_REG_ESB_ST_ADDR_H_BS2 (REG_HVD_BASE + ((0x0033) << 1)) 310 311 #define HVD_REG_ESB_LENGTH_L_BS2 (REG_HVD_BASE + ((0x0034) << 1)) 312 #define HVD_REG_ESB_LENGTH_H_BS2 (REG_HVD_BASE + ((0x0035) << 1)) 313 314 #define HVD_REG_ESB_RPTR_L_BS2 (REG_HVD_BASE + ((0x0036) << 1)) 315 316 #define HVD_REG_ESB_RPTR_H_BS2 (REG_HVD_BASE + ((0x0037) << 1)) 317 318 #define HVD_REG_MIF_BBU_BS2 (REG_HVD_BASE + ((0x0038) << 1)) 319 #define HVD_REG_MIF_OFFSET_L_BITS_BS2 7 320 #define HVD_REG_MIF_OFFSET_H_BS2 BIT(12) 321 #define HVD_REG_BBU_TSP_INPUT_BS2 BIT(8) 322 #define HVD_REG_BBU_PASER_ENABLE_ALL_BS2 BIT(9) 323 #define HVD_REG_BBU_PASER_ENABLE_03_BS2 (BIT(9) | BIT(10)) 324 #define HVD_REG_BBU_AUTO_NAL_TAB_BS2 BIT(11) 325 #define HVD_REG_BBU_PASER_DISABLE_BS2 0 326 #define HVD_REG_BBU_PASER_MASK_BS2 (BIT(10) | BIT(9)) 327 328 #define HVD_REG_NAL_TBL_ST_ADDR_L_BS2 (REG_HVD_BASE + ((0x0039) << 1)) 329 #define HVD_REG_NAL_TBL_ST_ADDR_H_BS2 (REG_HVD_BASE + ((0x003A) << 1)) 330 331 #define HVD_REG_NAL_RPTR_HI_BS2 (REG_HVD_BASE + ((0x003B) << 1)) 332 #define HVD_REG_NAL_WPTR_HI_BS2 (REG_HVD_BASE + ((0x003C) << 1)) 333 #define HVD_REG_NAL_TAB_LEN_BS2 (REG_HVD_BASE + ((0x003D) << 1)) 334 335 /* VP8 Registers */ 336 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1)) 337 #define HVD_REG_HK_VP8_DEC_MODE BIT(0) 338 #define HVD_REG_HK_PLAYER_FM BIT(1) 339 340 #define HVD_REG_ESB_ST_ADR_L_BS34 (REG_HVD_BASE + ((0x0042) << 1)) 341 #define HVD_REG_ESB_ST_ADR_H_BS34 (REG_HVD_BASE + ((0x0043) << 1)) 342 #define HVD_REG_ESB_LENGTH_L_BS34 (REG_HVD_BASE + ((0x0044) << 1)) 343 #define HVD_REG_ESB_LENGTH_H_BS34 (REG_HVD_BASE + ((0x0045) << 1)) 344 345 #define HVD_REG_MIF_BS34 (REG_HVD_BASE + ((0x0048) << 1)) 346 #define HVD_REG_BS34_MIF_OFFSET_L_BITS 7 347 #define HVD_REG_BS34_MIF_OFFSET_H BIT(12) 348 #define HVD_REG_BS34_TSP_INPUT BIT(8) 349 #define HVD_REG_BS34_PASER_MASK (BIT(10) | BIT(9)) 350 #define HVD_REG_BS34_PASER_DISABLE 0 351 #define HVD_REG_BS34_PASER_ENABLE_ALL BIT(9) 352 #define HVD_REG_BS34_PASER_ENABLE_03 (BIT(9) | BIT(10)) 353 #define HVD_REG_BS34_AUTO_NAL_TAB BIT(11) 354 #define HVD_REG_BS34_NAL_BUF_SKIP BIT(13) 355 #define HVD_REG_BS34_NAL_BUF_SKIP_RDY BIT(14) 356 357 #define HVD_REG_NAL_TAB_ST_L_BS3 (REG_HVD_BASE + ((0x0049) << 1)) 358 #define HVD_REG_NAL_TAB_ST_H_BS3 (REG_HVD_BASE + ((0x004A) << 1)) 359 #define HVD_REG_NAL_RPTR_HI_BS3 (REG_HVD_BASE + ((0x004B) << 1)) 360 #define HVD_REG_NAL_WPTR_HI_BS3 (REG_HVD_BASE + ((0x004C) << 1)) 361 #define HVD_REG_NAL_TAB_LEN_BS3 (REG_HVD_BASE + ((0x004D) << 1)) 362 #define HVD_REG_NAL_TAB_ST_L_BS4 (REG_HVD_BASE + ((0x0059) << 1)) 363 #define HVD_REG_NAL_TAB_ST_H_BS4 (REG_HVD_BASE + ((0x005A) << 1)) 364 #define HVD_REG_NAL_RPTR_HI_BS4 (REG_HVD_BASE + ((0x005B) << 1)) 365 #define HVD_REG_NAL_WPTR_HI_BS4 (REG_HVD_BASE + ((0x005C) << 1)) 366 #define HVD_REG_NAL_TAB_LEN_BS4 (REG_HVD_BASE + ((0x005D) << 1)) 367 368 //------------------------------------------------------------------------------ 369 // EVD Reg 370 //------------------------------------------------------------------------------ 371 #define EVD_REG_RESET (REG_EVD_BASE + ((0x0001) << 1)) 372 #define EVD_REG_RESET_SWRST BIT(0) 373 #define EVD_REG_RESET_SWRST_FIN BIT(2) 374 #define EVD_REG_RESET_STOP_BBU BIT(3) 375 #define EVD_REG_RESET_MIU_RDY BIT(4) 376 #define EVD_REG_RESET_HK_HEVC_MODE BIT(8) 377 #define EVD_REG_RESET_HK_TSP2EVD_EN BIT(9) 378 #define EVD_REG_RESET_MIU_256 BIT(10) 379 #define EVD_REG_RESET_MIU_128 BIT(11) 380 #define EVD_REG_RESET_CPUIF_SEL BIT(12) 381 #define EVD_REG_RESET_ALL_SRAM_SD_EN BIT(13) 382 #define EVD_REG_RESET_BOND_UHD BIT(14) 383 #define EVD_REG_RESET_BOND_HD BIT(15) 384 385 //------------------------------------------------------------------------------ 386 // ChipTop Reg 387 //------------------------------------------------------------------------------ 388 389 #define CHIPTOP_REG_BASE (0x1E00 ) 390 #define CLKGEN0_REG_BASE (0x0B00 ) 391 392 #define REG_TOP_PSRAM0_1_MIUMUX (CHIPTOP_REG_BASE+(0x002D<<1)) //TODO 393 #define TOP_CKG_PSRAM0_MASK BMASK(1:0) 394 #define TOP_CKG_PSRAM0_DIS BIT(0) 395 #define TOP_CKG_PSRAM0_INV BIT(1) 396 #define TOP_CKG_PSRAM1_MASK BMASK(3:2) 397 #define TOP_CKG_PSRAM1_DIS BIT(0) 398 #define TOP_CKG_PSRAM1_INV BIT(1) 399 #define TOP_MIU_MUX_G07_MASK BMASK(7:6) 400 #define TOP_MIU_MUX_G07_OD_LSB_R BITS(7:6,0) 401 #define TOP_MIU_MUX_G07_GOP2_R BITS(7:6,1) 402 #define TOP_MIU_MUX_G08_MASK BMASK(9:8) 403 #define TOP_MIU_MUX_G08_OD_LSB_W BITS(9:8,0) 404 #define TOP_MIU_MUX_G08_VE_W BITS(9:8,1) 405 #define TOP_MIU_MUX_G15_MASK BMASK(11:10) 406 #define TOP_MIU_MUX_G15_GOP2_R BITS(11:10,0) 407 #define TOP_MIU_MUX_G15_OD_LSB_R BITS(11:10,1) 408 #define TOP_MIU_MUX_G1A_MASK BMASK(13:12) 409 #define TOP_MIU_MUX_G1A_VE_W BITS(13:12,0) 410 #define TOP_MIU_MUX_G1A_OD_LSB_W BITS(13:12,1) 411 #define TOP_MIU_MUX_G26_MASK BMASK(15:14) 412 #define TOP_MIU_MUX_G26_RVD_RW BITS(15:14,0) 413 #define TOP_MIU_MUX_G26_SVD_INTP_R BITS(15:14,1) 414 #define TOP_MIU_MUX_G26_MVD_R BITS(15:14,2) 415 416 #define REG_TOP_VPU (CLKGEN0_REG_BASE+(0x0030<<1)) 417 #define TOP_CKG_VPU_MASK BMASK(4:0) 418 #define TOP_CKG_VPU_DIS BIT(0) 419 #define TOP_CKG_VPU_INV BIT(1) 420 #define TOP_CKG_VPU_CLK_MASK BMASK(4:2) 421 #define TOP_CKG_VPU_216MHZ BITS(4:2, 0) 422 #define TOP_CKG_VPU_192MHZ BITS(4:2, 1) 423 #define TOP_CKG_VPU_160MHZ BITS(4:2, 2) 424 #define TOP_CKG_VPU_144MHZ BITS(4:2, 3) 425 #define TOP_CKG_VPU_320MHZ BITS(4:2, 4) 426 #define TOP_CKG_VPU_288MHZ BITS(4:2, 5) 427 428 #define REG_TOP_HVD_IDB (CLKGEN0_REG_BASE+(0x0030<<1)) 429 #define TOP_CKG_HVD_IDB_MASK BMASK(10:8) 430 #define TOP_CKG_HVD_IDB_DIS BIT(8) 431 #define TOP_CKG_HVD_IDB_INV BIT(9) 432 #define TOP_CKG_HVD_IDB_CLK_HVD_MIU BIT(10) //0:HVD, 1:MIU 433 434 435 436 #define REG_TOP_HVD (CLKGEN0_REG_BASE+(0x0031<<1)) 437 #define TOP_CKG_HVD_MASK BMASK(4:0) 438 #define TOP_CKG_HVD_DIS BIT(0) 439 #define TOP_CKG_HVD_INV BIT(1) 440 #define TOP_CKG_HVD_CLK_MASK BMASK(4:2) 441 #define TOP_CKG_HVD_345MHZ BITS(4:2,0) 442 #define TOP_CKG_HVD_320MHZ BITS(4:2,1) 443 #define TOP_CKG_HVD_288MHZ BITS(4:2,2) 444 #define TOP_CKG_HVD_240MHZ BITS(4:2,3) 445 #define TOP_CKG_HVD_216MHZ BITS(4:2,4) 446 #define TOP_CKG_HVD_172MHZ BITS(4:2,5) 447 #define TOP_CKG_HVD_144MHZ BITS(4:2,6) 448 449 #define TOP_CKG_VP8_MASK BMASK(11:8) 450 #define TOP_CKG_VP8_DIS BIT(8) 451 #define TOP_CKG_VP8_INV BIT(9) 452 #define TOP_CKG_VP8_216MHZ BITS(11:10, 0) 453 #define TOP_CKG_VP8_172MHZ BITS(11:10, 1) 454 #define TOP_CKG_VP8_144MHZ BITS(11:10, 2) 455 #define TOP_CKG_VP8_240MHZ BITS(11:10, 3) 456 457 458 #define REG_TOP_VP6 (CLKGEN0_REG_BASE+(0x0032<<1)) 459 #define TOP_CKG_VP6_MASK BMASK(3:0) 460 #define TOP_CKG_VP6_DIS BIT(0) 461 #define TOP_CKG_VP6_INV BIT(1) 462 #define TOP_CKG_VP6_CLK_MASK BMASK(3:2) 463 #define TOP_CKG_VP6_192MHZ BITS(3:2,0) 464 #define TOP_CKG_VP6_172MHZ BITS(3:2,1) 465 #define TOP_CKG_VP6_160MHZ BITS(3:2,2) 466 #define TOP_CKG_VP6_144MHZ BITS(3:2,3) 467 468 469 470 471 472 473 474 475 #define REG_TOP_MVD (CLKGEN0_REG_BASE+(0x0039<<1)) 476 #define TOP_CKG_MVD_MASK BMASK(3:0) 477 #define TOP_CKG_MHVD_DIS BIT(0) 478 #define TOP_CKG_MVD_INV BIT(1) 479 #define TOP_CKG_MVD_CLK_MASK BMASK(3:2) 480 #define TOP_CKG_MVD_144MHZ BITS(3:2, 0) 481 #define TOP_CKG_MVD_123MHZ BITS(3:2, 1) 482 #define TOP_CKG_MVD_MIU BITS(3:2, 2) 483 #define TOP_CKG_MVD_XTAL BITS(3:2, 3) 484 485 #define REG_TOP_MVD2 (CLKGEN0_REG_BASE+(0x0039<<1)) 486 #define TOP_CKG_MVD2_MASK BMASK(11:8) 487 #define TOP_CKG_MHVD2_DIS BIT(8) 488 #define TOP_CKG_MVD2_INV BIT(9) 489 #define TOP_CKG_MVD2_CLK_MASK BMASK(11:10) 490 #define TOP_CKG_MVD2_170MHZ BITS(11:10, 0) 491 #define TOP_CKG_MVD2_144MHZ BITS(11:10, 1) 492 #define TOP_CKG_MVD2_160MHZ BITS(11:10, 1) 493 #define TOP_CKG_MVD2_CLK_MIU_P BITS(11:10, 1) 494 495 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) 496 #define TOP_CLK_HVD_VP8_MASK BMASK(1:0) 497 #define TOP_CLK_HVD_VP8_DIS BIT(0) 498 #define TOP_CLK_HVD_VP8_INV BIT(1) 499 #define TOP_CLK_MIU_HVD_MASK BMASK(5:4) 500 #define TOP_CLK_MIU_HVD_DIS BIT(0) 501 #define TOP_CLK_MIU_HVD_INV BIT(1) 502 #define TOP_CLK_RM_MIU_HVD_MASK BMASK(9:8) 503 #define TOP_CLK_RM_MIU_HVD_DIS BIT(0) 504 #define TOP_CLK_RM_MIU_HVD_INV BIT(1) 505 #define TOP_CLK_MIU_HVD_VP8_MASK BMASK(13:12) 506 #define TOP_CLK_MIU_HVD_VP8_DIS BIT(0) 507 #define TOP_CLK_MIU_HVD_VP8_INV BIT(1) 508 509 #define REG_TOP_CKG_EVD_PPU (CLKGEN0_REG_BASE+(0x0033<<1)) 510 #define TOP_CKG_EVD_PPU_MASK BMASK(12:10) 511 #define TOP_CKG_EVD_PPU_DIS BIT(8) 512 #define TOP_CKG_EVD_PPU_INV BIT(9) 513 #define TOP_CKG_EVD_PPU_345MHZ BITS(12:10, 0) 514 #define TOP_CKG_EVD_PPU_320MHZ BITS(12:10, 1) 515 #define TOP_CKG_EVD_PPU_288MHZ BITS(12:10, 2) 516 #define TOP_CKG_EVD_PPU_240MHZ BITS(12:10, 3) 517 #define TOP_CKG_EVD_PPU_216MHZ BITS(12:10, 4) 518 #define TOP_CKG_EVD_PPU_192MHZ BITS(12:10, 5) 519 #define TOP_CKG_EVD_PPU_160MHZ BITS(12:10, 6) 520 521 #define REG_TOP_CKG_EVD (CLKGEN0_REG_BASE+(0x0034<<1)) 522 #define TOP_CKG_EVD_MASK BMASK(12:10) 523 #define TOP_CKG_EVD_DIS BIT(8) 524 #define TOP_CKG_EVD_INV BIT(9) 525 #define TOP_CKG_EVD_345MHZ BITS(12:10, 0) 526 #define TOP_CKG_EVD_320MHZ BITS(12:10, 1) 527 #define TOP_CKG_EVD_288MHZ BITS(12:10, 2) 528 #define TOP_CKG_EVD_240MHZ BITS(12:10, 3) 529 #define TOP_CKG_EVD_216MHZ BITS(12:10, 4) 530 #define TOP_CKG_EVD_192MHZ BITS(12:10, 5) 531 #define TOP_CKG_EVD_160MHZ BITS(12:10, 6) 532 533 #define REG_TOP_UART_SEL0 (CHIPTOP_REG_BASE+(0x0053<<1)) 534 #define REG_TOP_UART_SEL_0_MASK BMASK(3:0) 535 #define REG_TOP_UART_SEL_MHEG5 BITS(3:0, 1) 536 #define REG_TOP_UART_SEL_VD_MHEG5 BITS(3:0, 2) 537 #define REG_TOP_UART_SEL_TSP BITS(3:0, 3) 538 #define REG_TOP_UART_SEL_PIU_0 BITS(3:0, 4) 539 #define REG_TOP_UART_SEL_PIU_1 BITS(3:0, 5) 540 #define REG_TOP_UART_SEL_PIU_FAST BITS(3:0, 7) 541 #define REG_TOP_UART_SEL_VD_MCU_51_TXD0 BITS(3:0, 10) 542 #define REG_TOP_UART_SEL_VD_MCU_51_TXD1 BITS(3:0, 11) 543 544 //------------------------------------------------------------------------------ 545 // MIU Reg 546 //------------------------------------------------------------------------------ 547 #define MIU0_REG_HVD_BASE (0x1200) 548 #define MIU1_REG_HVD_BASE (0x0600) 549 550 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1)) 551 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1)) 552 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1)) 553 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1)) 554 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) 555 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1)) 556 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1)) 557 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1)) 558 559 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1)) 560 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1)) 561 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1)) 562 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) 563 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1)) 564 565 566 #define MIU_HVD_RW (BIT(10)|BIT(11)) 567 #define MIU_MVD_RW (BIT(5)|BIT(6)) 568 569 //------------------------------------------------------------------------------------------------- 570 // Type and Structure 571 //------------------------------------------------------------------------------------------------- 572 573 574 #endif // _REG_HVD_H_ 575 576