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Searched refs:T2L1_REG_BASE (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBT2.c1711 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1713 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1764 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1766 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1837 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1839 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1891 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1893 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1974 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1997 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
[all …]
H A DhalDMD_INTERN_common.h115 #define T2L1_REG_BASE 0x2b00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBT2.c1711 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1713 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1764 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1766 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1837 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1839 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1891 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1893 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1974 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1997 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
[all …]
H A DhalDMD_INTERN_common.h115 #define T2L1_REG_BASE 0x2b00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBT2.c1759 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1761 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1812 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1885 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1887 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1939 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1941 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
2022 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2045 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
[all …]
H A DhalDMD_INTERN_common.h116 #define T2L1_REG_BASE 0x2b00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBT2.c1711 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1713 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1764 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1766 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1837 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1839 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1891 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1893 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1974 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1997 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
[all …]
H A DhalDMD_INTERN_common.h115 #define T2L1_REG_BASE 0x2b00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBT2.c1711 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1713 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1764 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1766 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1837 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1839 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1891 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1893 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1974 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1997 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
[all …]
H A DhalDMD_INTERN_common.h115 #define T2L1_REG_BASE 0x2b00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBT2.c1711 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1713 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1764 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1766 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1837 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1839 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1891 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1893 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1974 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1997 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
[all …]
H A DhalDMD_INTERN_common.h116 #define T2L1_REG_BASE 0x2b00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBT2.c1711 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1713 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1764 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1766 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1837 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1839 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1891 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1893 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1974 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1997 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
[all …]
H A DhalDMD_INTERN_common.h115 #define T2L1_REG_BASE 0x2b00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBT2.c1759 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1761 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1812 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
1885 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1887 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1939 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7]
1941 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7]
2022 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2045 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
[all …]
H A DhalDMD_INTERN_common.h116 #define T2L1_REG_BASE 0x2b00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBT2.c1719 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1795 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1797 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1877 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1900 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1908 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1916 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1924 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x36 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1932 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
[all …]
H A DhalDMD_INTERN_common.h115 #define T2L1_REG_BASE 0x2b00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBT2.c1753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1755 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1829 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1831 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1911 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1934 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1942 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1950 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1958 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x36 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1966 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
[all …]
H A DhalDMD_INTERN_common.h116 #define T2L1_REG_BASE 0x2b00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT2.c1760 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1762 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1836 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1838 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1918 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1941 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1949 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1957 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1965 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x36 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1973 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
[all …]
H A DhalDMD_INTERN_common.h113 #define T2L1_REG_BASE 0x2b00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBT2.c1660 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1662 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPostLdpcBer()
1736 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1738 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, &reg); //FEC Type[8:7] in INTERN_DVBT2_GetPreLdpcBer()
1818 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1825 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1833 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1841 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1849 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x36 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
1857 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
[all …]
H A DhalDMD_INTERN_common.h112 #define T2L1_REG_BASE 0x2b00 macro